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vexriscv_mem_mapped_example
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Thorsten Knoll 5df08904e9 update readme 4 years ago
c_project first tiny mem-mapped example is working 4 years ago
vexriscv first tiny mem-mapped example is working 4 years ago
README.md update readme 4 years ago

README.md

vexriscv_mem_mapped_example

Tools:

Use the Virtual Machine 1.5 from: https://random-oracles.org/risc-v/ GitHub

Starting the Vexriscv Simulation

Open console, change to folder 'vexriscv' and run ''' sbt "runMain mupq.PQVexRiscvSim" '''

Connecting openocd-vexriscv

Open new console, change to folder 'vexriscv' and run ''' openocd-vexriscv -f vexriscvsim.cfg '''

Compile and run the C code

Open new console (the third one), change to folder 'c_project' and compile the project: ''' make ''' Then load the created ELF file into the simulation via GDB: ''' riscv64-unknown-elf-gdb -tui -ex 'set remotetimeout 15' -ex 'target remote :3333' -ex 'load' -ex 'break main' -ex 'continue' main ''' Set some more breakpoints and step through the code with 'c' (continue). You will see the UART output in console 1 (vexriscv sim).