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vexriscv_mem_mapped_example
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  • 5e6247a (HEAD -> master) reworked Makefiles, project structure and unified the codebase by Thorsten Knoll 2021-02-04 15:55:08 +0100
  • 5ab026d the XOR module works with ULX3S too! by Thorsten Knoll 2021-01-30 18:19:02 +0100
  • 933b52e struct(C) and bundle(spinal) now equal and w/r enabled from both sides by Thorsten Knoll 2021-01-30 18:10:02 +0100
  • 935ecd6 bigger mem on the bus (128 bit) by Thorsten Knoll 2021-01-29 20:13:56 +0100
  • d5c6abc init file for RAM by Thorsten Knoll 2021-01-28 10:57:53 +0100
  • d7b372a tested mem-mapped example for sim and ulx3s by Thorsten Knoll 2021-01-27 15:06:34 +0100
  • eae126e cleaned project for C in sim and ulx3s by Thorsten Knoll 2021-01-27 14:54:11 +0100
  • 78b34dd working c for ulx3s and sim by Thorsten Knoll 2021-01-27 14:18:53 +0100
  • a0e1fdb update readme by Thorsten Knoll 2021-01-18 08:17:28 +0100
  • c44cd23 update readme by Thorsten Knoll 2021-01-18 08:12:20 +0100
  • e4e90fd update readme by Thorsten Knoll 2021-01-18 08:11:18 +0100
  • 01cfcc4 update readme by Thorsten Knoll 2021-01-18 08:09:59 +0100
  • 52e9f96 update readme by Thorsten Knoll 2021-01-18 08:09:12 +0100
  • 5df0890 update readme by Thorsten Knoll 2021-01-18 08:07:30 +0100
  • 4486690 first tiny mem-mapped example is working by Thorsten Knoll 2021-01-17 20:30:08 +0100
  • b9cccf9 added MyMem template by Thorsten Knoll 2021-01-14 16:13:58 +0100
  • ce9f47e Initial commit by Thorsten 2021-01-14 13:31:50 +0100