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7803 lines
610 KiB
7803 lines
610 KiB
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
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-- Parsing `PQVexRiscvUlx3s.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend: PQVexRiscvUlx3s.v
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Parsing Verilog input from `PQVexRiscvUlx3s.v' to AST representation.
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Generating RTLIL representation for module `\BufferCC'.
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Generating RTLIL representation for module `\BufferCC_1_'.
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Generating RTLIL representation for module `\UartCtrlTx'.
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Generating RTLIL representation for module `\UartCtrlRx'.
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Generating RTLIL representation for module `\StreamFifoLowLatency'.
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Generating RTLIL representation for module `\FlowCCByToggle'.
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Generating RTLIL representation for module `\UartCtrl'.
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Generating RTLIL representation for module `\StreamFifo'.
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Generating RTLIL representation for module `\Prescaler'.
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Generating RTLIL representation for module `\Timer'.
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Generating RTLIL representation for module `\InterruptCtrl'.
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Generating RTLIL representation for module `\StreamArbiter'.
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Generating RTLIL representation for module `\StreamFork'.
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Generating RTLIL representation for module `\StreamFifoLowLatency_1_'.
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Generating RTLIL representation for module `\BufferCC_2_'.
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Generating RTLIL representation for module `\VexRiscv'.
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Generating RTLIL representation for module `\JtagBridge'.
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Generating RTLIL representation for module `\SystemDebugger'.
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Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'.
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Generating RTLIL representation for module `\Apb3UartCtrl'.
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Generating RTLIL representation for module `\MuraxApb3Timer'.
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Generating RTLIL representation for module `\MyMem'.
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Generating RTLIL representation for module `\Apb3Decoder'.
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Generating RTLIL representation for module `\Apb3Router'.
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Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_1_'.
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Generating RTLIL representation for module `\PQVexRiscvUlx3s'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -top PQVexRiscvUlx3s -json PQVexRiscvUlx3s.json' --
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2. Executing SYNTH_ECP5 pass.
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2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_SLICE'.
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Generating RTLIL representation for module `\DP16KD'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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2.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\DCUA'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Successfully finished Verilog frontend.
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2.3. Executing HIERARCHY pass (managing design hierarchy).
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2.3.1. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \MuraxApb3Timer
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Used module: \InterruptCtrl
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Used module: \Timer
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Used module: \Prescaler
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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2.3.2. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \MuraxApb3Timer
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Used module: \InterruptCtrl
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Used module: \Timer
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Used module: \Prescaler
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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Removed 0 unused modules.
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2.4. Executing PROC pass (convert processes to netlists).
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2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'.
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Cleaned up 1 empty switch.
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2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494 in module TRELLIS_FF.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8216$1266 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8157$1253 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8106$1246 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8084$1241 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8077$1240 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7489$1233 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7482$1232 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7306$1228 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7294$1210 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7281$1206 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7268$1202 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7256$1199 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7184$1191 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7172$1170 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7159$1166 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7146$1162 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7133$1158 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7118$1155 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7042$1143 in module PipelinedMemoryBusRamUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6938$1109 in module Apb3Router.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6885$1108 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6877$1107 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6815$1081 in module MyMem.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6715$1079 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6680$1076 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6649$1070 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6620$1069 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6610$1068 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6579$1062 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6550$1061 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6540$1060 in module MuraxApb3Timer.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6511$1059 in module MuraxApb3Timer.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6469$1046 in module MuraxApb3Timer.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6323$1037 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6303$1036 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6286$1035 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6269$1034 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6252$1033 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6235$1032 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6215$1027 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6207$1026 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6200$1025 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6180$1024 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6144$1009 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5954$1004 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5944$1001 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5930$999 in module PipelinedMemoryBusToApbBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5875$995 in module SystemDebugger.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5849$991 in module SystemDebugger.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5738$974 in module JtagBridge.
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Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5710$971 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5656$954 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5432$946 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4817$790 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4808$781 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4801$780 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4794$779 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4787$778 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4779$777 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4771$776 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4762$775 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4753$774 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4744$773 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4725$772 in module VexRiscv.
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Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4657$718 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4646$716 in module VexRiscv.
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Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4623$715 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4599$703 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4590$700 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4581$699 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4564$694 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4550$693 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4521$688 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4441$682 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4429$675 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4393$666 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4365$664 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4285$656 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4268$655 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4203$652 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4189$651 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4175$647 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4166$645 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4130$624 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4116$608 in module VexRiscv.
|
|
Marked 16 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4069$603 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4056$601 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4045$600 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4035$597 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4020$591 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4006$590 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3939$583 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3923$581 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3908$580 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3898$570 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3874$561 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3839$549 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3818$543 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3792$525 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3774$519 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3765$517 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3758$516 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3750$514 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3739$510 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3732$508 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3725$507 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3709$506 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3699$505 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3692$504 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3681$502 in module VexRiscv.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3660$501 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3646$500 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3638$499 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3629$498 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3621$497 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3608$487 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3599$486 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3590$485 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3583$484 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3576$483 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3564$475 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3555$474 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3542$464 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3523$463 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3512$462 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3484$459 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3469$458 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3462$456 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3454$454 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3416$453 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3385$451 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3355$449 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1421$231 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1413$227 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1393$216 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1384$213 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1377$212 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1366$210 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1357$207 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1350$206 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1343$205 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1270$195 in module StreamFork.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1250$188 in module StreamFork.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1202$185 in module StreamArbiter.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1138$167 in module InterruptCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1101$163 in module Timer.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1038$150 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1020$132 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1011$129 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1004$128 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:997$126 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:988$123 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:981$122 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:974$121 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:899$111 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:884$110 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:877$109 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:780$106 in module FlowCCByToggle.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:706$99 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:697$97 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:689$96 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:680$95 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:665$87 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:658$86 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:649$84 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:642$83 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:635$82 in module StreamFifoLowLatency.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:553$61 in module UartCtrlRx.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:474$43 in module UartCtrlRx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:461$41 in module UartCtrlRx.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:431$39 in module UartCtrlRx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:260$14 in module UartCtrlTx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:238$13 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:219$11 in module UartCtrlTx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:208$9 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:198$6 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:97$1 in module BufferCC.
|
|
Removed a total of 0 dead cases.
|
|
|
|
2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 30 redundant assignments.
|
|
Promoted 417 assignments to connections.
|
|
|
|
2.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'.
|
|
Set init value: \Q = 1'0
|
|
Found init rule in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'.
|
|
Set init value: \jtag_tap_fsm_state = 4'0000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'.
|
|
Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'.
|
|
Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Set init value: \inputArea_target = 1'0
|
|
|
|
2.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
Found async reset \resetCtrl_mainClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'.
|
|
Found async reset \resetCtrl_systemClockReset in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
Found async reset \resetCtrl_systemClockReset in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
Found async reset \resetCtrl_mainClockReset in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
Found async reset \resetCtrl_mainClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
Found async reset \resetCtrl_systemClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'.
|
|
Found async reset \resetCtrl_systemClockReset in `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'.
|
|
Found async reset \resetCtrl_systemClockReset in `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found async reset \resetCtrl_mainClockReset in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found async reset \resetCtrl_systemClockReset in `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
|
|
2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'.
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'.
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
1/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_EN[3:0]$1473
|
|
2/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_DATA[3:0]$1472
|
|
3/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_ADDR[3:0]$1471
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'.
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
1/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_EN[3:0]$1417
|
|
2/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_DATA[3:0]$1416
|
|
3/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_ADDR[3:0]$1415
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'.
|
|
1/1: $0\_zz_35_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
1/16: $0\_zz_34_[3:0]
|
|
2/16: $0\_zz_33_[31:0]
|
|
3/16: $0\_zz_32_[31:0]
|
|
4/16: $0\_zz_31_[0:0]
|
|
5/16: $0\_zz_28_[3:0]
|
|
6/16: $0\_zz_27_[31:0]
|
|
7/16: $0\_zz_26_[31:0]
|
|
8/16: $0\_zz_25_[0:0]
|
|
9/16: $0\_zz_15_[3:0]
|
|
10/16: $0\_zz_14_[31:0]
|
|
11/16: $0\_zz_13_[31:0]
|
|
12/16: $0\_zz_12_[0:0]
|
|
13/16: $0\_zz_9_[3:0]
|
|
14/16: $0\_zz_8_[31:0]
|
|
15/16: $0\_zz_7_[31:0]
|
|
16/16: $0\_zz_6_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
1/4: $0\_zz_30_[0:0]
|
|
2/4: $0\_zz_24_[0:0]
|
|
3/4: $0\_zz_11_[0:0]
|
|
4/4: $0\_zz_5_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'.
|
|
1/1: $0\resetCtrl_systemClockReset[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'.
|
|
1/1: $1\_zz_22_[3:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'.
|
|
1/1: $1\core_externalInterrupt[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'.
|
|
1/1: $1\core_timerInterrupt[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'.
|
|
1/2: $0\logic_rspHits_1[0:0]
|
|
2/2: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'.
|
|
1/1: $1\_zz_3_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
1/3: $0\logic_rspHits_2[0:0]
|
|
2/3: $0\logic_rspHits_1[0:0]
|
|
3/3: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'.
|
|
1/1: $1\io_outputs_2_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'.
|
|
1/1: $1\_zz_4_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA[7:0]$1123
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_ADDR[13:0]$1122
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA[7:0]$1126
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_ADDR[13:0]$1125
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA[7:0]$1129
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_ADDR[13:0]$1128
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA[7:0]$1132
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_ADDR[13:0]$1131
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
|
|
1/3: $1\_zz_5_[0:0]
|
|
2/3: $1\_zz_4_[31:0]
|
|
3/3: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'.
|
|
1/1: $1\io_input_PSLVERROR[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'.
|
|
1/1: $1\io_input_PREADY[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'.
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'.
|
|
1/1: $0\myReg[31:0]
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'.
|
|
1/1: $1\io_bus_PRDATA[31:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
1/3: $0\timerB_io_limit_driver[15:0]
|
|
2/3: $0\timerA_io_limit_driver[15:0]
|
|
3/3: $0\_zz_1_[15:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
1/5: $0\interruptCtrl_1__io_masks_driver[1:0]
|
|
2/5: $0\timerBBridge_clearsEnable[0:0]
|
|
3/5: $0\timerBBridge_ticksEnable[1:0]
|
|
4/5: $0\timerABridge_clearsEnable[0:0]
|
|
5/5: $0\timerABridge_ticksEnable[1:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'.
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'.
|
|
1/2: $2\_zz_12_[1:0]
|
|
2/2: $1\_zz_12_[1:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'.
|
|
1/2: $2\_zz_6_[0:0]
|
|
2/2: $1\_zz_6_[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'.
|
|
1/2: $2\_zz_5_[0:0]
|
|
2/2: $1\_zz_5_[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'.
|
|
1/2: $2\timerBBridge_busClearing[0:0]
|
|
2/2: $1\timerBBridge_busClearing[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'.
|
|
1/2: $2\_zz_4_[0:0]
|
|
2/2: $1\_zz_4_[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'.
|
|
1/2: $2\_zz_3_[0:0]
|
|
2/2: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'.
|
|
1/2: $2\timerABridge_busClearing[0:0]
|
|
2/2: $1\timerABridge_busClearing[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'.
|
|
1/2: $2\_zz_2_[0:0]
|
|
2/2: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'.
|
|
1/3: $1\io_apb_PRDATA[16:0] [16]
|
|
2/3: $1\io_apb_PRDATA[16:0] [15:2]
|
|
3/3: $1\io_apb_PRDATA[16:0] [1:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
1/6: $0\bridge_misc_doBreak[0:0]
|
|
2/6: $0\bridge_misc_breakDetected[0:0]
|
|
3/6: $0\bridge_misc_readOverflowError[0:0]
|
|
4/6: $0\bridge_misc_readError[0:0]
|
|
5/6: $0\bridge_interruptCtrl_readIntEnable[0:0]
|
|
6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'.
|
|
1/2: $2\_zz_6_[0:0]
|
|
2/2: $1\_zz_6_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'.
|
|
1/2: $2\_zz_5_[0:0]
|
|
2/2: $1\_zz_5_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'.
|
|
1/2: $2\_zz_4_[0:0]
|
|
2/2: $1\_zz_4_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'.
|
|
1/2: $2\_zz_3_[0:0]
|
|
2/2: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'.
|
|
1/2: $2\_zz_2_[0:0]
|
|
2/2: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'.
|
|
1/2: $2\bridge_read_streamBreaked_ready[0:0]
|
|
2/2: $1\bridge_read_streamBreaked_ready[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'.
|
|
1/1: $1\_zz_8_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'.
|
|
1/1: $1\bridge_read_streamBreaked_valid[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'.
|
|
1/2: $2\_zz_1_[0:0]
|
|
2/2: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'.
|
|
1/9: $2\io_apb_PRDATA[20:15] [5:2]
|
|
2/9: $1\io_apb_PRDATA[9:0] [7:2]
|
|
3/9: $2\io_apb_PRDATA[20:15] [1]
|
|
4/9: $1\io_apb_PRDATA[9:0] [8]
|
|
5/9: $2\io_apb_PRDATA[20:15] [0]
|
|
6/9: $1\io_apb_PRDATA[9:0] [1]
|
|
7/9: $3\io_apb_PRDATA[28:24]
|
|
8/9: $1\io_apb_PRDATA[9:0] [9]
|
|
9/9: $1\io_apb_PRDATA[9:0] [0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'.
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
1/2: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0]
|
|
2/2: $0\state[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'.
|
|
1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'.
|
|
1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'.
|
|
1/2: $0\dispatcher_headerShifter[7:0]
|
|
2/2: $0\dispatcher_dataShifter[66:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
1/3: $0\dispatcher_counter[2:0]
|
|
2/3: $0\dispatcher_headerLoaded[0:0]
|
|
3/3: $0\dispatcher_dataLoaded[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
1/4: $0\jtag_readArea_shifter[33:0]
|
|
2/4: $0\jtag_idcodeArea_shifter[31:0]
|
|
3/4: $0\jtag_tap_instructionShift[3:0]
|
|
4/4: $0\jtag_tap_instruction[3:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
1/3: $0\system_rsp_payload_data[31:0]
|
|
2/3: $0\system_rsp_payload_error[0:0]
|
|
3/3: $0\system_rsp_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'.
|
|
1/2: $2\jtag_writeArea_source_valid[0:0]
|
|
2/2: $1\jtag_writeArea_source_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'.
|
|
1/5: $5\jtag_tap_tdoUnbufferd[0:0]
|
|
2/5: $4\jtag_tap_tdoUnbufferd[0:0]
|
|
3/5: $3\jtag_tap_tdoUnbufferd[0:0]
|
|
4/5: $2\jtag_tap_tdoUnbufferd[0:0]
|
|
5/5: $1\jtag_tap_tdoUnbufferd[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'.
|
|
1/1: $1\_zz_1_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
1/8: $0\DebugPlugin_hardwareBreakpoints_2_valid[0:0]
|
|
2/8: $0\DebugPlugin_hardwareBreakpoints_1_valid[0:0]
|
|
3/8: $0\DebugPlugin_hardwareBreakpoints_0_valid[0:0]
|
|
4/8: $0\DebugPlugin_haltedByBreak[0:0]
|
|
5/8: $0\DebugPlugin_godmode[0:0]
|
|
6/8: $0\DebugPlugin_stepIt[0:0]
|
|
7/8: $0\DebugPlugin_haltIt[0:0]
|
|
8/8: $0\DebugPlugin_resetIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
1/5: $0\DebugPlugin_firstCycle[0:0]
|
|
2/5: $0\DebugPlugin_busReadDataReg[31:0]
|
|
3/5: $0\DebugPlugin_hardwareBreakpoints_2_pc[30:0]
|
|
4/5: $0\DebugPlugin_hardwareBreakpoints_1_pc[30:0]
|
|
5/5: $0\DebugPlugin_hardwareBreakpoints_0_pc[30:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
1/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [32]
|
|
2/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [31:0]
|
|
3/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [64:32]
|
|
4/92: $0\execute_CsrPlugin_csr_2946[0:0]
|
|
5/92: $0\execute_CsrPlugin_csr_2818[0:0]
|
|
6/92: $0\execute_CsrPlugin_csr_2944[0:0]
|
|
7/92: $0\execute_CsrPlugin_csr_2816[0:0]
|
|
8/92: $0\execute_CsrPlugin_csr_834[0:0]
|
|
9/92: $0\execute_CsrPlugin_csr_773[0:0]
|
|
10/92: $0\execute_CsrPlugin_csr_772[0:0]
|
|
11/92: $0\execute_CsrPlugin_csr_836[0:0]
|
|
12/92: $0\execute_CsrPlugin_csr_768[0:0]
|
|
13/92: $0\decode_to_execute_RS1[31:0]
|
|
14/92: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
|
|
15/92: $0\execute_to_memory_MEMORY_ENABLE[0:0]
|
|
16/92: $0\decode_to_execute_MEMORY_ENABLE[0:0]
|
|
17/92: $0\execute_to_memory_BRANCH_DO[0:0]
|
|
18/92: $0\decode_to_execute_IS_RS2_SIGNED[0:0]
|
|
19/92: $0\execute_to_memory_MUL_HH[31:0]
|
|
20/92: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
|
|
21/92: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
|
|
22/92: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
|
|
23/92: $0\decode_to_execute_ALU_CTRL[1:0]
|
|
24/92: $0\decode_to_execute_IS_CSR[0:0]
|
|
25/92: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
|
|
26/92: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
|
|
27/92: $0\execute_to_memory_IS_DIV[0:0]
|
|
28/92: $0\decode_to_execute_IS_DIV[0:0]
|
|
29/92: $0\execute_to_memory_MUL_LH[31:0]
|
|
30/92: $0\memory_to_writeBack_MEMORY_STORE[0:0]
|
|
31/92: $0\execute_to_memory_MEMORY_STORE[0:0]
|
|
32/92: $0\decode_to_execute_MEMORY_STORE[0:0]
|
|
33/92: $0\execute_to_memory_MUL_HL[31:0]
|
|
34/92: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
|
|
35/92: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
|
|
36/92: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
|
|
37/92: $0\execute_to_memory_BRANCH_CALC[31:0]
|
|
38/92: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
|
|
39/92: $0\execute_to_memory_SHIFT_RIGHT[31:0]
|
|
40/92: $0\memory_to_writeBack_PC[31:0]
|
|
41/92: $0\execute_to_memory_PC[31:0]
|
|
42/92: $0\decode_to_execute_PC[31:0]
|
|
43/92: $0\decode_to_execute_IS_RS1_SIGNED[0:0]
|
|
44/92: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
|
|
45/92: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
|
|
46/92: $0\memory_to_writeBack_MUL[63:0]
|
|
47/92: $0\memory_to_writeBack_SRC2[31:0]
|
|
48/92: $0\execute_to_memory_SRC2[31:0]
|
|
49/92: $0\decode_to_execute_SRC2[31:0]
|
|
50/92: $0\execute_to_memory_INSTRUCTION[31:0]
|
|
51/92: $0\decode_to_execute_INSTRUCTION[31:0]
|
|
52/92: $0\memory_to_writeBack_IS_MUL[0:0]
|
|
53/92: $0\execute_to_memory_IS_MUL[0:0]
|
|
54/92: $0\decode_to_execute_IS_MUL[0:0]
|
|
55/92: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
56/92: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
57/92: $0\decode_to_execute_BRANCH_CTRL[1:0]
|
|
58/92: $0\decode_to_execute_DO_EBREAK[0:0]
|
|
59/92: $0\memory_to_writeBack_SRC1[31:0]
|
|
60/92: $0\execute_to_memory_SRC1[31:0]
|
|
61/92: $0\decode_to_execute_SRC1[31:0]
|
|
62/92: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
|
|
63/92: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
|
|
64/92: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
|
|
65/92: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
|
|
66/92: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
|
|
67/92: $0\decode_to_execute_RS2[31:0]
|
|
68/92: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
|
|
69/92: $0\execute_to_memory_SHIFT_CTRL[1:0]
|
|
70/92: $0\decode_to_execute_SHIFT_CTRL[1:0]
|
|
71/92: $0\memory_to_writeBack_ENV_CTRL[0:0]
|
|
72/92: $0\execute_to_memory_ENV_CTRL[0:0]
|
|
73/92: $0\decode_to_execute_ENV_CTRL[0:0]
|
|
74/92: $0\execute_to_memory_MUL_LL[31:0]
|
|
75/92: $0\memory_MulDivIterativePlugin_div_result[31:0]
|
|
76/92: $0\memory_MulDivIterativePlugin_div_done[0:0]
|
|
77/92: $0\memory_MulDivIterativePlugin_div_needRevert[0:0]
|
|
78/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [31:0]
|
|
79/92: $0\memory_MulDivIterativePlugin_rs2[31:0]
|
|
80/92: $0\CsrPlugin_mip_MSIP[0:0]
|
|
81/92: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
82/92: $0\CsrPlugin_interrupt_code[3:0]
|
|
83/92: $0\CsrPlugin_minstret[63:0]
|
|
84/92: $0\CsrPlugin_mcause_exceptionCode[3:0]
|
|
85/92: $0\CsrPlugin_mcause_interrupt[0:0]
|
|
86/92: $0\CsrPlugin_mepc[31:0]
|
|
87/92: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0]
|
|
88/92: $0\_zz_63_[0:0]
|
|
89/92: $0\_zz_62_[31:0]
|
|
90/92: $0\_zz_61_[0:0]
|
|
91/92: $0\_zz_60_[31:0]
|
|
92/92: $0\_zz_58_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
1/38: $0\memory_MulDivIterativePlugin_div_counter_value[5:0]
|
|
2/38: $0\_zz_100_[0:0]
|
|
3/38: $0\_zz_88_[0:0]
|
|
4/38: $0\execute_CsrPlugin_wfiWake[0:0]
|
|
5/38: $0\CsrPlugin_hadException[0:0]
|
|
6/38: $0\CsrPlugin_interrupt_valid[0:0]
|
|
7/38: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0]
|
|
8/38: $0\IBusSimplePlugin_pending_value[2:0]
|
|
9/38: $0\IBusSimplePlugin_fetchPc_booted[0:0]
|
|
10/38: $0\_zz_125_[2:0]
|
|
11/38: $0\memory_to_writeBack_INSTRUCTION[31:0]
|
|
12/38: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
|
|
13/38: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
|
|
14/38: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
|
|
15/38: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
|
|
16/38: $0\CsrPlugin_mie_MSIE[0:0]
|
|
17/38: $0\CsrPlugin_mie_MTIE[0:0]
|
|
18/38: $0\CsrPlugin_mie_MEIE[0:0]
|
|
19/38: $0\CsrPlugin_mstatus_MPP[1:0]
|
|
20/38: $0\CsrPlugin_mstatus_MPIE[0:0]
|
|
21/38: $0\CsrPlugin_mstatus_MIE[0:0]
|
|
22/38: $0\CsrPlugin_mtvec_base[29:0]
|
|
23/38: $0\CsrPlugin_mtvec_mode[1:0]
|
|
24/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0]
|
|
25/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0]
|
|
26/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0]
|
|
27/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0]
|
|
28/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0]
|
|
29/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0]
|
|
30/38: $0\_zz_59_[0:0]
|
|
31/38: $0\_zz_57_[0:0]
|
|
32/38: $0\_zz_55_[0:0]
|
|
33/38: $0\IBusSimplePlugin_fetchPc_inc[0:0]
|
|
34/38: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0]
|
|
35/38: $0\IBusSimplePlugin_fetchPc_pcReg[31:0]
|
|
36/38: $0\writeBack_arbitration_isValid[0:0]
|
|
37/38: $0\memory_arbitration_isValid[0:0]
|
|
38/38: $0\execute_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'.
|
|
1/1: $1\_zz_134_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'.
|
|
1/1: $1\_zz_133_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'.
|
|
1/1: $1\_zz_132_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'.
|
|
1/1: $1\_zz_131_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'.
|
|
1/2: $1\_zz_130_[3:0]
|
|
2/2: $2\_zz_130_[31:31]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'.
|
|
1/2: $1\_zz_129_[31:0] [31:2]
|
|
2/2: $1\_zz_129_[31:0] [1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'.
|
|
1/3: $1\_zz_128_[3:3]
|
|
2/3: $2\_zz_128_[7:7]
|
|
3/3: $3\_zz_128_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'.
|
|
1/3: $1\_zz_127_[3:3]
|
|
2/3: $2\_zz_127_[7:7]
|
|
3/3: $3\_zz_127_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'.
|
|
1/3: $1\_zz_126_[3:3]
|
|
2/3: $2\_zz_126_[7:7]
|
|
3/3: $3\_zz_126_[12:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'.
|
|
1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'.
|
|
1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'.
|
|
1/5: $1\debug_bus_rsp_data[4:0] [4]
|
|
2/5: $1\debug_bus_rsp_data[4:0] [2]
|
|
3/5: $1\debug_bus_rsp_data[4:0] [1]
|
|
4/5: $1\debug_bus_rsp_data[4:0] [0]
|
|
5/5: $1\debug_bus_rsp_data[4:0] [3]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'.
|
|
1/3: $3\debug_bus_cmd_ready[0:0]
|
|
2/3: $2\debug_bus_cmd_ready[0:0]
|
|
3/3: $1\debug_bus_cmd_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'.
|
|
1/1: $1\memory_MulDivIterativePlugin_div_counter_willClear[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'.
|
|
1/1: $1\writeBack_Mul16Plugin_bSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'.
|
|
1/1: $1\writeBack_Mul16Plugin_aSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'.
|
|
1/1: $1\_zz_118_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'.
|
|
1/1: $1\_zz_111_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'.
|
|
1/3: $3\_zz_110_[0:0]
|
|
2/3: $2\_zz_110_[0:0]
|
|
3/3: $1\_zz_110_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'.
|
|
1/10: $10\_zz_99_[0:0]
|
|
2/10: $9\_zz_99_[0:0]
|
|
3/10: $8\_zz_99_[0:0]
|
|
4/10: $7\_zz_99_[0:0]
|
|
5/10: $6\_zz_99_[0:0]
|
|
6/10: $5\_zz_99_[0:0]
|
|
7/10: $4\_zz_99_[0:0]
|
|
8/10: $3\_zz_99_[0:0]
|
|
9/10: $2\_zz_99_[0:0]
|
|
10/10: $1\_zz_99_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'.
|
|
1/10: $10\_zz_98_[0:0]
|
|
2/10: $9\_zz_98_[0:0]
|
|
3/10: $8\_zz_98_[0:0]
|
|
4/10: $7\_zz_98_[0:0]
|
|
5/10: $6\_zz_98_[0:0]
|
|
6/10: $5\_zz_98_[0:0]
|
|
7/10: $4\_zz_98_[0:0]
|
|
8/10: $3\_zz_98_[0:0]
|
|
9/10: $2\_zz_98_[0:0]
|
|
10/10: $1\_zz_98_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'.
|
|
1/1: $1\execute_SrcPlugin_addSub[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'.
|
|
1/1: $1\_zz_95_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'.
|
|
1/1: $1\_zz_90_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'.
|
|
1/1: $1\_zz_89_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'.
|
|
1/1: $1\execute_IntAluPlugin_bitwise[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'.
|
|
1/1: $1\lastStageRegFileWrite_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'.
|
|
1/1: $1\execute_CsrPlugin_writeData[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'.
|
|
1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
|
|
2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'.
|
|
1/16: $16\execute_CsrPlugin_illegalAccess[0:0]
|
|
2/16: $15\execute_CsrPlugin_illegalAccess[0:0]
|
|
3/16: $14\execute_CsrPlugin_illegalAccess[0:0]
|
|
4/16: $13\execute_CsrPlugin_illegalAccess[0:0]
|
|
5/16: $12\execute_CsrPlugin_illegalAccess[0:0]
|
|
6/16: $11\execute_CsrPlugin_illegalAccess[0:0]
|
|
7/16: $10\execute_CsrPlugin_illegalAccess[0:0]
|
|
8/16: $9\execute_CsrPlugin_illegalAccess[0:0]
|
|
9/16: $8\execute_CsrPlugin_illegalAccess[0:0]
|
|
10/16: $7\execute_CsrPlugin_illegalAccess[0:0]
|
|
11/16: $6\execute_CsrPlugin_illegalAccess[0:0]
|
|
12/16: $5\execute_CsrPlugin_illegalAccess[0:0]
|
|
13/16: $4\execute_CsrPlugin_illegalAccess[0:0]
|
|
14/16: $3\execute_CsrPlugin_illegalAccess[0:0]
|
|
15/16: $2\execute_CsrPlugin_illegalAccess[0:0]
|
|
16/16: $1\execute_CsrPlugin_illegalAccess[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'.
|
|
1/1: $1\CsrPlugin_xtvec_base[29:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'.
|
|
1/1: $1\CsrPlugin_xtvec_mode[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'.
|
|
1/1: $1\CsrPlugin_pipelineLiberator_done[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'.
|
|
1/1: $1\CsrPlugin_privilege[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'.
|
|
1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'.
|
|
1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
|
|
2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'.
|
|
1/1: $1\_zz_67_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'.
|
|
1/1: $1\_zz_66_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'.
|
|
1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'.
|
|
1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'.
|
|
1/1: $1\decode_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'.
|
|
1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'.
|
|
1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'.
|
|
1/1: $1\CsrPlugin_allowException[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'.
|
|
1/1: $1\CsrPlugin_allowInterrupts[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'.
|
|
1/1: $1\CsrPlugin_forceMachineWire[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'.
|
|
1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
|
|
2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
|
|
3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'.
|
|
1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
|
|
2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'.
|
|
1/1: $1\CsrPlugin_thirdPartyWake[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'.
|
|
1/2: $2\IBusSimplePlugin_incomingInstruction[0:0]
|
|
2/2: $1\IBusSimplePlugin_incomingInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'.
|
|
1/6: $6\IBusSimplePlugin_fetcherHalt[0:0]
|
|
2/6: $5\IBusSimplePlugin_fetcherHalt[0:0]
|
|
3/6: $4\IBusSimplePlugin_fetcherHalt[0:0]
|
|
4/6: $3\IBusSimplePlugin_fetcherHalt[0:0]
|
|
5/6: $2\IBusSimplePlugin_fetcherHalt[0:0]
|
|
6/6: $1\IBusSimplePlugin_fetcherHalt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'.
|
|
1/2: $2\writeBack_arbitration_flushNext[0:0]
|
|
2/2: $1\writeBack_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'.
|
|
1/1: $1\writeBack_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'.
|
|
1/1: $1\memory_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'.
|
|
1/1: $1\memory_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'.
|
|
1/3: $3\memory_arbitration_haltItself[0:0]
|
|
2/3: $2\memory_arbitration_haltItself[0:0]
|
|
3/3: $1\memory_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'.
|
|
1/2: $2\execute_arbitration_flushNext[0:0]
|
|
2/2: $1\execute_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'.
|
|
1/2: $2\execute_arbitration_flushIt[0:0]
|
|
2/2: $1\execute_arbitration_flushIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'.
|
|
1/1: $1\execute_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'.
|
|
1/1: $1\execute_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'.
|
|
1/3: $3\execute_arbitration_haltItself[0:0]
|
|
2/3: $2\execute_arbitration_haltItself[0:0]
|
|
3/3: $1\execute_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'.
|
|
1/1: $1\decode_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'.
|
|
1/3: $3\decode_arbitration_haltByOther[0:0]
|
|
2/3: $2\decode_arbitration_haltByOther[0:0]
|
|
3/3: $1\decode_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'.
|
|
1/1: $1\decode_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'.
|
|
1/1: $1\_zz_48_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'.
|
|
1/3: $3\_zz_47_[31:0]
|
|
2/3: $2\_zz_47_[31:0]
|
|
3/3: $1\_zz_47_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'.
|
|
1/1: $1\_zz_43_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'.
|
|
1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'.
|
|
1/1: $1\_zz_35_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'.
|
|
1/3: $3\_zz_23_[31:0]
|
|
2/3: $2\_zz_23_[31:0]
|
|
3/3: $1\_zz_23_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'.
|
|
1/11: $11\decode_RS1[31:0]
|
|
2/11: $10\decode_RS1[31:0]
|
|
3/11: $9\decode_RS1[31:0]
|
|
4/11: $8\decode_RS1[31:0]
|
|
5/11: $7\decode_RS1[31:0]
|
|
6/11: $6\decode_RS1[31:0]
|
|
7/11: $5\decode_RS1[31:0]
|
|
8/11: $4\decode_RS1[31:0]
|
|
9/11: $3\decode_RS1[31:0]
|
|
10/11: $2\decode_RS1[31:0]
|
|
11/11: $1\decode_RS1[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'.
|
|
1/11: $11\decode_RS2[31:0]
|
|
2/11: $10\decode_RS2[31:0]
|
|
3/11: $9\decode_RS2[31:0]
|
|
4/11: $8\decode_RS2[31:0]
|
|
5/11: $7\decode_RS2[31:0]
|
|
6/11: $6\decode_RS2[31:0]
|
|
7/11: $5\decode_RS2[31:0]
|
|
8/11: $4\decode_RS2[31:0]
|
|
9/11: $3\decode_RS2[31:0]
|
|
10/11: $2\decode_RS2[31:0]
|
|
11/11: $1\decode_RS2[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
1/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420
|
|
2/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_DATA[31:0]$419
|
|
3/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_ADDR[4:0]$418
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'.
|
|
1/1: $0\_zz_138_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'.
|
|
1/1: $0\_zz_137_[31:0]
|
|
Creating decoders for process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'.
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
1/3: $0\popPtr_value[2:0]
|
|
2/3: $0\pushPtr_value[2:0]
|
|
3/3: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'.
|
|
1/1: $1\io_occupancy[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'.
|
|
1/2: $2\popPtr_valueNext[2:0]
|
|
2/2: $1\popPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'.
|
|
1/2: $2\pushPtr_valueNext[2:0]
|
|
2/2: $1\pushPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
1/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204
|
|
2/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_DATA[1:0]$203
|
|
3/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_ADDR[2:0]$202
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'.
|
|
1/1: $0\pendings[1:0]
|
|
Creating decoders for process `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'.
|
|
1/1: $0\counter[15:0]
|
|
Creating decoders for process `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'.
|
|
1/1: $0\inhibitFull[0:0]
|
|
Creating decoders for process `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'.
|
|
1/1: $0\counter[15:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
1/4: $0\_zz_2_[0:0]
|
|
2/4: $0\logic_popPtr_value[3:0]
|
|
3/4: $0\logic_pushPtr_value[3:0]
|
|
4/4: $0\logic_risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
1/1: $1\logic_popPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
1/1: $1\logic_popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
1/1: $1\logic_popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
1/1: $1\logic_pushPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
1/1: $1\logic_pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
1/1: $1\logic_pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
1/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
2/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA[7:0]$119
|
|
3/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR[3:0]$118
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
1/1: $0\_zz_3_[7:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
1/1: $0\clockDivider_counter[19:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
1/1: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
1/1: $1\io_write_thrown_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
1/1: $0\outputArea_flow_regNext_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
1/3: $0\inputArea_data_fragment[0:0]
|
|
2/3: $0\inputArea_data_last[0:0]
|
|
3/3: $0\inputArea_target[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
1/1: $0\_zz_3_[32:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
1/1: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
1/1: $1\io_pop_payload_inst[31:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
1/1: $1\io_pop_payload_error[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
1/1: $1\io_pop_valid[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
1/9: $2$lookahead\stateMachine_shifter$60[7:0]$74
|
|
2/9: $2$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$73
|
|
3/9: $2$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$72
|
|
4/9: $1$lookahead\stateMachine_shifter$60[7:0]$70
|
|
5/9: $1$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$69
|
|
6/9: $1$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$68
|
|
7/9: $0\bitCounter_value[2:0]
|
|
8/9: $0\bitTimer_counter[2:0]
|
|
9/9: $0\stateMachine_parity[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
1/8: $0\stateMachine_validReg[0:0]
|
|
2/8: $0\sampler_tick[0:0]
|
|
3/8: $0\sampler_value[0:0]
|
|
4/8: $0\_zz_1_[0:0]
|
|
5/8: $0\break_counter[6:0]
|
|
6/8: $0\sampler_samples_2[0:0]
|
|
7/8: $0\sampler_samples_1[0:0]
|
|
8/8: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
1/2: $2\bitTimer_tick[0:0]
|
|
2/2: $1\bitTimer_tick[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
1/5: $5\io_error[0:0]
|
|
2/5: $4\io_error[0:0]
|
|
3/5: $3\io_error[0:0]
|
|
4/5: $2\io_error[0:0]
|
|
5/5: $1\io_error[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
1/2: $0\stateMachine_parity[0:0]
|
|
2/2: $0\tickCounter_value[2:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
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1/3: $0\_zz_1_[0:0]
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2/3: $0\clockDivider_counter_value[2:0]
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3/3: $0\stateMachine_state[2:0]
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|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
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1/3: $3\io_write_ready[0:0]
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2/3: $2\io_write_ready[0:0]
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3/3: $1\io_write_ready[0:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
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1/1: $1\stateMachine_txd[0:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
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1/2: $2\clockDivider_counter_valueNext[2:0]
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2/2: $1\clockDivider_counter_valueNext[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
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1/1: $1\clockDivider_counter_willIncrement[0:0]
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|
Creating decoders for process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
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|
Creating decoders for process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
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1/2: $0\buffers_1[0:0]
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2/2: $0\buffers_0[0:0]
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2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
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No latch inferred for signal `\PQVexRiscvUlx3s.\_zz_22_' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'.
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No latch inferred for signal `\PQVexRiscvUlx3s.\core_externalInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'.
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No latch inferred for signal `\PQVexRiscvUlx3s.\core_timerInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'.
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|
No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\_zz_3_' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_2_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\_zz_4_' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'.
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|
No latch inferred for signal `\PipelinedMemoryBusRamUlx3s.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'.
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|
No latch inferred for signal `\Apb3Router.\_zz_3_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
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|
No latch inferred for signal `\Apb3Router.\_zz_4_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
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|
No latch inferred for signal `\Apb3Router.\_zz_5_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
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|
No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'.
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|
No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'.
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|
No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'.
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|
No latch inferred for signal `\MyMem.\io_bus_PRDATA' from process `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'.
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|
No latch inferred for signal `\MuraxApb3Timer.\_zz_11_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'.
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|
No latch inferred for signal `\MuraxApb3Timer.\_zz_12_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'.
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|
No latch inferred for signal `\MuraxApb3Timer.\_zz_6_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'.
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|
No latch inferred for signal `\MuraxApb3Timer.\_zz_5_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'.
|
|
No latch inferred for signal `\MuraxApb3Timer.\timerBBridge_busClearing' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'.
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|
No latch inferred for signal `\MuraxApb3Timer.\_zz_4_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'.
|
|
No latch inferred for signal `\MuraxApb3Timer.\_zz_3_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'.
|
|
No latch inferred for signal `\MuraxApb3Timer.\timerABridge_busClearing' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'.
|
|
No latch inferred for signal `\MuraxApb3Timer.\_zz_2_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'.
|
|
No latch inferred for signal `\MuraxApb3Timer.\io_apb_PRDATA' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'.
|
|
No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6175$1006$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'.
|
|
No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6175$1007$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_6_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_5_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_4_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_3_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_2_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_8_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_1_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'.
|
|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'.
|
|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'.
|
|
No latch inferred for signal `\JtagBridge.\jtag_writeArea_source_valid' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'.
|
|
No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'.
|
|
No latch inferred for signal `\JtagBridge.\_zz_1_' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_134_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'.
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|
No latch inferred for signal `\VexRiscv.\_zz_132_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_129_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_127_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'.
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|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'.
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|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'.
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|
No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'.
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|
No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'.
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|
No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'.
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|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_valueNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'.
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|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willClear' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'.
|
|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_bSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'.
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|
No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_aSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_118_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_117_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_115_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_113_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_99_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_98_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_97_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_96_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'.
|
|
No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_95_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_94_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_92_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_90_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_89_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'.
|
|
No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'.
|
|
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_71_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_69_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_67_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_66_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'.
|
|
No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_48_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_47_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_43_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'.
|
|
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_35_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_23_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\io_occupancy' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\_zz_1_' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'.
|
|
No latch inferred for signal `\StreamFork.\io_input_ready' from process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
No latch inferred for signal `\StreamFifo.\_zz_1_' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\_zz_1_' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
|
|
2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'.
|
|
created $dff cell `$procdff$3812' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
created $dff cell `$procdff$3813' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
created $dff cell `$procdff$3814' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
created $dff cell `$procdff$3815' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
created $dff cell `$procdff$3816' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
created $dff cell `$procdff$3817' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
created $dff cell `$procdff$3818' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_35_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'.
|
|
created $adff cell `$procdff$3819' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\core_cpu_debug_resetOut_regNext' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'.
|
|
created $dff cell `$procdff$3820' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_6_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3821' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_7_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3822' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_8_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3823' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_9_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3824' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_12_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3825' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_13_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3826' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_14_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3827' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_15_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3828' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_25_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3829' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_26_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3830' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_27_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3831' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_28_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3832' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_31_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3833' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_32_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3834' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_33_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3835' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_34_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
created $dff cell `$procdff$3836' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_5_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
created $adff cell `$procdff$3837' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_11_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
created $adff cell `$procdff$3838' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_24_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
created $adff cell `$procdff$3839' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_30_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
created $adff cell `$procdff$3840' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_systemClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'.
|
|
created $dff cell `$procdff$3841' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_mainClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'.
|
|
created $dff cell `$procdff$3842' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'.
|
|
created $dff cell `$procdff$3843' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'.
|
|
created $dff cell `$procdff$3844' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'.
|
|
created $adff cell `$procdff$3845' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
created $dff cell `$procdff$3846' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
created $dff cell `$procdff$3847' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_2' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
created $dff cell `$procdff$3848' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'.
|
|
created $adff cell `$procdff$3849' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'.
|
|
created $adff cell `$procdff$3850' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3851' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3852' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3853' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3854' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3855' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3856' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3857' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3858' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3859' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3860' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3861' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
created $dff cell `$procdff$3862' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
created $dff cell `$procdff$3863' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
created $dff cell `$procdff$3864' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
created $dff cell `$procdff$3865' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
created $dff cell `$procdff$3866' with positive edge clock.
|
|
Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'.
|
|
created $dff cell `$procdff$3867' with positive edge clock.
|
|
Creating register for signal `\MyMem.\myReg' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'.
|
|
created $dff cell `$procdff$3868' with positive edge clock.
|
|
Creating register for signal `\MuraxApb3Timer.\_zz_1_' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
created $dff cell `$procdff$3869' with positive edge clock.
|
|
Creating register for signal `\MuraxApb3Timer.\timerA_io_limit_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
created $dff cell `$procdff$3870' with positive edge clock.
|
|
Creating register for signal `\MuraxApb3Timer.\timerB_io_limit_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
created $dff cell `$procdff$3871' with positive edge clock.
|
|
Creating register for signal `\MuraxApb3Timer.\timerABridge_ticksEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
created $adff cell `$procdff$3872' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MuraxApb3Timer.\timerABridge_clearsEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
created $adff cell `$procdff$3873' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MuraxApb3Timer.\timerBBridge_ticksEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
created $adff cell `$procdff$3874' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MuraxApb3Timer.\timerBBridge_clearsEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
created $adff cell `$procdff$3875' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MuraxApb3Timer.\interruptCtrl_1__io_masks_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
created $adff cell `$procdff$3876' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\uartCtrl_1__io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'.
|
|
created $dff cell `$procdff$3877' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3878' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3879' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3880' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3881' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3882' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
created $adff cell `$procdff$3883' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'.
|
|
created $dff cell `$procdff$3884' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
created $adff cell `$procdff$3885' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
created $adff cell `$procdff$3886' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'.
|
|
created $dff cell `$procdff$3887' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'.
|
|
created $dff cell `$procdff$3888' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
created $adff cell `$procdff$3889' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
created $adff cell `$procdff$3890' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
created $adff cell `$procdff$3891' with positive edge clock and positive level reset.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'.
|
|
created $dff cell `$procdff$3892' with negative edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3893' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3894' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3895' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3896' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3897' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_readArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
created $dff cell `$procdff$3898' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
created $dff cell `$procdff$3899' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
created $dff cell `$procdff$3900' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
created $dff cell `$procdff$3901' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3902' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3903' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3904' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3905' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3906' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3907' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3908' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
created $adff cell `$procdff$3909' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3910' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3911' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3912' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3913' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3914' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3915' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3916' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_124_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3917' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
created $dff cell `$procdff$3918' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_58_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3919' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_60_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3920' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_61_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3921' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_62_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3922' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_63_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3923' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3924' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3925' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3926' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3927' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3928' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3929' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3930' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3931' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3932' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3933' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3934' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3935' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_102_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3936' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3937' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3938' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_accumulator' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3939' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_needRevert' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3940' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_done' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3941' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_result' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3942' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3943' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3944' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3945' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3946' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3947' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3948' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3949' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3950' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3951' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3952' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3953' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3954' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3955' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3956' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3957' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3958' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3959' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3960' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3961' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3962' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3963' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3964' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3965' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3966' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3967' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3968' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3969' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3970' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3971' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3972' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3973' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3974' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3975' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3976' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3977' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3978' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3979' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3980' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3981' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3982' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3983' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3984' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3985' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3986' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3987' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3988' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3989' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3990' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3991' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3992' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3993' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3994' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3995' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3996' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3997' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3998' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$3999' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4000' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4001' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4002' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4003' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4004' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4005' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4006' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4007' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4008' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4009' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2816' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4010' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2944' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4011' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2818' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4012' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2946' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
created $dff cell `$procdff$4013' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4014' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4015' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4016' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4017' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4018' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4019' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4020' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_55_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4021' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_57_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4022' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_59_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4023' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4024' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4025' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4026' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4027' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4028' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4029' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4030' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4031' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4032' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4033' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4034' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4035' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4036' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4037' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4038' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4039' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4040' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4041' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4042' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4043' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4044' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4045' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_88_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4046' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_100_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4047' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4048' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4049' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4050' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_125_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
created $adff cell `$procdff$4051' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_ADDR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
created $dff cell `$procdff$4052' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
created $dff cell `$procdff$4053' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
created $dff cell `$procdff$4054' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_138_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'.
|
|
created $dff cell `$procdff$4055' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_137_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'.
|
|
created $dff cell `$procdff$4056' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_0' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'.
|
|
created $dff cell `$procdff$4057' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_1' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'.
|
|
created $dff cell `$procdff$4058' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\risingOccupancy' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
created $adff cell `$procdff$4059' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\pushPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
created $adff cell `$procdff$4060' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\popPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
created $adff cell `$procdff$4061' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_ADDR' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
created $dff cell `$procdff$4062' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_DATA' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
created $dff cell `$procdff$4063' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
created $dff cell `$procdff$4064' with positive edge clock.
|
|
Creating register for signal `\StreamFork.\_zz_2_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
created $adff cell `$procdff$4065' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork.\_zz_1_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
created $adff cell `$procdff$4066' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_0' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'.
|
|
created $dff cell `$procdff$4067' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_1' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'.
|
|
created $dff cell `$procdff$4068' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\locked' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'.
|
|
created $adff cell `$procdff$4069' with positive edge clock and positive level reset.
|
|
Creating register for signal `\InterruptCtrl.\pendings' using process `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'.
|
|
created $adff cell `$procdff$4070' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Timer.\counter' using process `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'.
|
|
created $dff cell `$procdff$4071' with positive edge clock.
|
|
Creating register for signal `\Timer.\inhibitFull' using process `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'.
|
|
created $adff cell `$procdff$4072' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Prescaler.\counter' using process `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'.
|
|
created $dff cell `$procdff$4073' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.\_zz_2_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4074' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4075' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4076' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4077' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4078' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4079' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4080' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.\_zz_3_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
created $dff cell `$procdff$4081' with positive edge clock.
|
|
Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
created $adff cell `$procdff$4082' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_valid' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
created $adff cell `$procdff$4083' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4084' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4085' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4086' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4087' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4088' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4089' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\_zz_3_' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
created $dff cell `$procdff$4090' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
created $adff cell `$procdff$4091' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4092' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4093' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4094' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4095' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4096' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$data$PQVexRiscvUlx3s.v:580$28' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4097' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$60' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4098' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4099' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\_zz_1_' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4100' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4101' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4102' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4103' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4104' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4105' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4106' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$4107' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$4108' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4109' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4110' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\_zz_1_' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4111' with positive edge clock and positive level reset.
|
|
Creating register for signal `\BufferCC_1_.\buffers_0' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$4112' with positive edge clock.
|
|
Creating register for signal `\BufferCC_1_.\buffers_1' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$4113' with positive edge clock.
|
|
Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$4114' with positive edge clock and positive level non-const reset.
|
|
Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$4121' with positive edge clock and positive level non-const reset.
|
|
|
|
2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'.
|
|
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'.
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'.
|
|
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'.
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'.
|
|
Found and cleaned up 4 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'.
|
|
Found and cleaned up 6 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'.
|
|
Found and cleaned up 2 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'.
|
|
Found and cleaned up 1 empty switch in `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'.
|
|
Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'.
|
|
Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'.
|
|
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'.
|
|
Found and cleaned up 1 empty switch in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'.
|
|
Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'.
|
|
Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'.
|
|
Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'.
|
|
Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'.
|
|
Found and cleaned up 7 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'.
|
|
Found and cleaned up 5 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'.
|
|
Found and cleaned up 1 empty switch in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'.
|
|
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'.
|
|
Found and cleaned up 8 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'.
|
|
Found and cleaned up 90 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'.
|
|
Found and cleaned up 61 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'.
|
|
Found and cleaned up 16 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'.
|
|
Found and cleaned up 6 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'.
|
|
Removing empty process `BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'.
|
|
Removing empty process `InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'.
|
|
Found and cleaned up 2 empty switches in `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'.
|
|
Removing empty process `Timer.$proc$PQVexRiscvUlx3s.v:1114$164'.
|
|
Found and cleaned up 2 empty switches in `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'.
|
|
Removing empty process `Timer.$proc$PQVexRiscvUlx3s.v:1101$163'.
|
|
Found and cleaned up 1 empty switch in `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'.
|
|
Removing empty process `Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
Removing empty process `BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Cleaned up 579 empty switches.
|
|
|
|
2.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module PipelinedMemoryBusArbiter_1_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter.
|
|
Deleting now unused module PipelinedMemoryBusDecoder_1_.
|
|
Deleting now unused module PipelinedMemoryBusDecoder.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s.
|
|
Deleting now unused module Apb3Router.
|
|
Deleting now unused module Apb3Decoder.
|
|
Deleting now unused module MyMem.
|
|
Deleting now unused module MuraxApb3Timer.
|
|
Deleting now unused module Apb3UartCtrl.
|
|
Deleting now unused module PipelinedMemoryBusToApbBridge.
|
|
Deleting now unused module SystemDebugger.
|
|
Deleting now unused module JtagBridge.
|
|
Deleting now unused module VexRiscv.
|
|
Deleting now unused module BufferCC_2_.
|
|
Deleting now unused module StreamFifoLowLatency_1_.
|
|
Deleting now unused module StreamFork.
|
|
Deleting now unused module StreamArbiter.
|
|
Deleting now unused module InterruptCtrl.
|
|
Deleting now unused module Timer.
|
|
Deleting now unused module Prescaler.
|
|
Deleting now unused module StreamFifo.
|
|
Deleting now unused module UartCtrl.
|
|
Deleting now unused module FlowCCByToggle.
|
|
Deleting now unused module StreamFifoLowLatency.
|
|
Deleting now unused module UartCtrlRx.
|
|
Deleting now unused module UartCtrlTx.
|
|
Deleting now unused module BufferCC_1_.
|
|
Deleting now unused module BufferCC.
|
|
<suppressed ~33 debug messages>
|
|
|
|
2.6. Executing TRIBUF pass.
|
|
|
|
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
2.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~457 debug messages>
|
|
|
|
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 299 unused cells and 2697 unused wires.
|
|
<suppressed ~385 debug messages>
|
|
|
|
2.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~525 debug messages>
|
|
Removed a total of 175 cells.
|
|
|
|
2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port A of cell $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2009: \pipelinedMemoryBusToApbBridge_1_.state -> 1'1
|
|
Replacing known input bits on port B of cell $flatten\systemDebugger_1_.$procmux$2050: \systemDebugger_1_.dispatcher_headerLoaded -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\systemDebugger_1_.$procmux$2048: \systemDebugger_1_.dispatcher_headerLoaded -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3560.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3685.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3694.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1896.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1905.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3716.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3718.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3724.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1914.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1923.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3783.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3785.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3792.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1932.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1943.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1962.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2711.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2713.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2722.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2750.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2752.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2761.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2779.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2805.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2808.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2814.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2827.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2829.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2835.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2845.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2847.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2853.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2871.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2884.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2886.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2892.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2902.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2904.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2910.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2928.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3109.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3142.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3172.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3184.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3193.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3208.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3240.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3265.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3275.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3277.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3283.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3293.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3295.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3301.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3313.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3319.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3328.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3338.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3340.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3346.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3356.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3358.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3364.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3376.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3382.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3391.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2096.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2105.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2114.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1719.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1731.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1745.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1768.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1788.
|
|
dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1817.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2018.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2027.
|
|
Removed 85 multiplexer ports.
|
|
<suppressed ~431 debug messages>
|
|
|
|
2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3503:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2789: $auto$opt_reduce.cc:134:opt_mux$4129
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2797: { $flatten\core_cpu.$procmux$2800_CMP $auto$opt_reduce.cc:134:opt_mux$4131 }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2874: { }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2931: { }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3072: $auto$opt_reduce.cc:134:opt_mux$4133
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3396:
|
|
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420
|
|
New ports: A=1'0, B=1'1, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0]
|
|
New connections: $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [31:1] = { $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] }
|
|
New ctrl vector for $pmux cell $flatten\apb3Router_1_.$procmux$1657: { }
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3503:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1616:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1622:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1628:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1634:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3440:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0]
|
|
New connections: $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [1] = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1616:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1622:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1628:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1634:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3440:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0]
|
|
New connections: $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [1] = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0]
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3727: { $auto$opt_reduce.cc:134:opt_mux$4135 $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP }
|
|
New ctrl vector for $mux cell $flatten\io_apb_decoder.$procmux$1664: { }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 21 changes.
|
|
|
|
2.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~93 debug messages>
|
|
Removed a total of 31 cells.
|
|
|
|
2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4121 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4114 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$4044 ($adff) from module PQVexRiscvUlx3s.
|
|
|
|
2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 2 unused cells and 318 unused wires.
|
|
<suppressed ~50 debug messages>
|
|
|
|
2.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~416 debug messages>
|
|
|
|
2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3593: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP $auto$opt_reduce.cc:134:opt_mux$4137 }
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3744: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP $auto$opt_reduce.cc:134:opt_mux$4139 }
|
|
New ctrl vector for $pmux cell $flatten\jtagBridge_1_.$procmux$2124: { $flatten\jtagBridge_1_.$procmux$2138_CMP $auto$opt_reduce.cc:134:opt_mux$4145 $flatten\jtagBridge_1_.$procmux$2135_CMP $flatten\jtagBridge_1_.$procmux$2134_CMP $flatten\jtagBridge_1_.$procmux$2133_CMP $flatten\jtagBridge_1_.$procmux$2131_CMP $auto$opt_reduce.cc:134:opt_mux$4143 $flatten\jtagBridge_1_.$procmux$2128_CMP $flatten\jtagBridge_1_.$procmux$2127_CMP $flatten\jtagBridge_1_.$procmux$2126_CMP $auto$opt_reduce.cc:134:opt_mux$4141 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 3 changes.
|
|
|
|
2.11.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 4 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.11.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~416 debug messages>
|
|
|
|
2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.11.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.11.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_8_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_9_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state.
|
|
Not marking PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_code as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_targetPrivilege.
|
|
Not marking PQVexRiscvUlx3s.core_cpu._zz_125_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.jtagBridge_1_.jtag_tap_fsm_state as FSM state register:
|
|
Register has an initialization value.
|
|
|
|
2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4099
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
found state code: 3'010
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
found state code: 3'001
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP }
|
|
transition: 3'000 6'-0---- -> 3'000 7'0000001
|
|
transition: 3'000 6'-1---- -> 3'001 7'0010001
|
|
transition: 3'100 6'----0- -> 3'100 7'1000000
|
|
transition: 3'100 6'---01- -> 3'000 7'0000000
|
|
transition: 3'100 6'---110 -> 3'100 7'1000000
|
|
transition: 3'100 6'---111 -> 3'000 7'0000000
|
|
transition: 3'010 6'----0- -> 3'010 7'0101000
|
|
transition: 3'010 6'--0-1- -> 3'010 7'0101000
|
|
transition: 3'010 6'--1-1- -> 3'100 7'1001000
|
|
transition: 3'001 6'----0- -> 3'001 7'0010010
|
|
transition: 3'001 6'---01- -> 3'010 7'0100010
|
|
transition: 3'001 6'---11- -> 3'000 7'0000010
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procdff$4110
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
found state code: 3'001
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
found state code: 3'010
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP }
|
|
transition: 3'000 5'---0- -> 3'000 7'0000001
|
|
transition: 3'000 5'---1- -> 3'001 7'0010001
|
|
transition: 3'100 5'--0-- -> 3'100 7'1000000
|
|
transition: 3'100 5'--1-0 -> 3'100 7'1000000
|
|
transition: 3'100 5'0-1-1 -> 3'000 7'0000000
|
|
transition: 3'100 5'1-1-1 -> 3'001 7'0010000
|
|
transition: 3'010 5'--0-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-01-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-11-- -> 3'100 7'1000010
|
|
transition: 3'001 5'--0-- -> 3'001 7'0011000
|
|
transition: 3'001 5'--1-- -> 3'010 7'0101000
|
|
Extracting FSM `\core_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\PQVexRiscvUlx3s'.
|
|
found $dff cell for state register: $flatten\core_cpu.$procdff$3934
|
|
root of input selection tree: $flatten\core_cpu.$0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
found ctrl input: \core_cpu.CsrPlugin_mstatus_MIE
|
|
found ctrl input: \core_cpu._zz_164_
|
|
found ctrl input: \core_cpu._zz_163_
|
|
found ctrl input: \core_cpu._zz_162_
|
|
found state code: 2'11
|
|
fsm extraction failed: at least two states are required.
|
|
|
|
2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'.
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused input signal \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_.
|
|
|
|
2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 30 unused cells and 30 unused wires.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [2].
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [2].
|
|
|
|
2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
|
|
2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146 (\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
1: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP
|
|
3: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'0---- -> 0 4'0001
|
|
1: 0 5'1---- -> 3 4'0001
|
|
2: 1 5'--111 -> 0 4'0000
|
|
3: 1 5'--01- -> 0 4'0000
|
|
4: 1 5'--110 -> 1 4'0000
|
|
5: 1 5'---0- -> 1 4'0000
|
|
6: 2 5'-1-1- -> 1 4'1000
|
|
7: 2 5'---0- -> 2 4'1000
|
|
8: 2 5'-0-1- -> 2 4'1000
|
|
9: 3 5'--11- -> 0 4'0010
|
|
10: 3 5'--01- -> 2 4'0010
|
|
11: 3 5'---0- -> 3 4'0010
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152 (\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 3
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'---0- -> 0 3'000
|
|
1: 0 5'---1- -> 3 3'000
|
|
2: 1 5'0-1-1 -> 0 3'000
|
|
3: 1 5'--1-0 -> 1 3'000
|
|
4: 1 5'--0-- -> 1 3'000
|
|
5: 1 5'1-1-1 -> 3 3'000
|
|
6: 2 5'-11-- -> 1 3'001
|
|
7: 2 5'--0-- -> 2 3'001
|
|
8: 2 5'-01-- -> 2 3'001
|
|
9: 3 5'--1-- -> 2 3'100
|
|
10: 3 5'--0-- -> 3 3'100
|
|
|
|
-------------------------------------
|
|
|
|
2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'.
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~13 debug messages>
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3627.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3627.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3629.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3629.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3631.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3714.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3714.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3722.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3722.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3727.
|
|
dead port 1/4 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3799.
|
|
Removed 11 multiplexer ports.
|
|
<suppressed ~414 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$3841 ($dff) from module PQVexRiscvUlx3s (D = \asyncReset_buffercc.buffers_1, Q = \resetCtrl_systemClockReset, rval = 1'1).
|
|
Adding EN signal on $procdff$3840 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8180$1255_Y, Q = \_zz_30_).
|
|
Adding EN signal on $procdff$3839 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_24_[0:0], Q = \_zz_24_).
|
|
Adding EN signal on $procdff$3838 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8171$1254_Y, Q = \_zz_11_).
|
|
Adding EN signal on $procdff$3837 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_5_[0:0], Q = \_zz_5_).
|
|
Adding EN signal on $procdff$3836 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8208$1264_Y, Q = \_zz_34_).
|
|
Adding EN signal on $procdff$3835 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8207$1263_Y, Q = \_zz_33_).
|
|
Adding EN signal on $procdff$3834 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8206$1262_Y, Q = \_zz_32_).
|
|
Adding EN signal on $procdff$3833 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8205$1261_Y, Q = \_zz_31_).
|
|
Adding EN signal on $procdff$3832 ($dff) from module PQVexRiscvUlx3s (D = \_zz_21_, Q = \_zz_28_).
|
|
Adding EN signal on $procdff$3831 ($dff) from module PQVexRiscvUlx3s (D = \_zz_20_, Q = \_zz_27_).
|
|
Adding EN signal on $procdff$3830 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB, Q = \_zz_26_).
|
|
Adding EN signal on $procdff$3829 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \_zz_25_).
|
|
Adding EN signal on $procdff$3828 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8196$1260_Y, Q = \_zz_15_).
|
|
Adding EN signal on $procdff$3827 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8195$1259_Y, Q = \_zz_14_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4284 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_8_, Q = \_zz_14_, rval = 0).
|
|
Adding EN signal on $procdff$3826 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8194$1258_Y, Q = \_zz_13_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4286 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_7_ [1:0], Q = \_zz_13_ [1:0], rval = 2'00).
|
|
Adding EN signal on $procdff$3825 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8193$1257_Y, Q = \_zz_12_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4288 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_6_, Q = \_zz_12_, rval = 1'0).
|
|
Adding EN signal on $procdff$3824 ($dff) from module PQVexRiscvUlx3s (D = 4'xxxx, Q = \_zz_9_).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3823 ($dff) from module PQVexRiscvUlx3s (D = 0, Q = \_zz_8_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3822 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, Q = \_zz_7_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4292 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4292 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3821 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \_zz_6_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4293 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3891 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$procmux$2044_Y, Q = \systemDebugger_1_.dispatcher_counter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3890 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_headerLoaded[0:0], Q = \systemDebugger_1_.dispatcher_headerLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3889 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_dataLoaded[0:0], Q = \systemDebugger_1_.dispatcher_dataLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3888 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_headerShifter [7:1] }, Q = \systemDebugger_1_.dispatcher_headerShifter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3887 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_dataShifter [66:1] }, Q = \systemDebugger_1_.dispatcher_dataShifter).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3868 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_.myReg).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.\timerB.$procdff$4072 ($adff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$0\inhibitFull[0:0], Q = \muraxApb3Timer_1_.timerB.inhibitFull).
|
|
Adding SRST signal on $flatten\muraxApb3Timer_1_.\timerB.$procdff$4071 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$procmux$3468_Y, Q = \muraxApb3Timer_1_.timerB.counter, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4323 ($sdff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165_Y, Q = \muraxApb3Timer_1_.timerB.counter).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.\timerA.$procdff$4072 ($adff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$0\inhibitFull[0:0], Q = \muraxApb3Timer_1_.timerA.inhibitFull).
|
|
Adding SRST signal on $flatten\muraxApb3Timer_1_.\timerA.$procdff$4071 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$procmux$3468_Y, Q = \muraxApb3Timer_1_.timerA.counter, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4328 ($sdff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165_Y, Q = \muraxApb3Timer_1_.timerA.counter).
|
|
Adding SRST signal on $flatten\muraxApb3Timer_1_.\prescaler_1_.$procdff$4073 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156_Y, Q = \muraxApb3Timer_1_.prescaler_1_.counter, rval = 16'0000000000000000).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3876 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.interruptCtrl_1__io_masks_driver).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3875 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [16], Q = \muraxApb3Timer_1_.timerBBridge_clearsEnable).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3874 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.timerBBridge_ticksEnable).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3873 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [16], Q = \muraxApb3Timer_1_.timerABridge_clearsEnable).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3872 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.timerABridge_ticksEnable).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3871 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_.timerB_io_limit_driver).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3870 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_.timerA_io_limit_driver).
|
|
Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3869 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4059 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4066 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4065 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4069 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4068 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4067 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3866 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120_DATA, Q = \memory_ramBlocks_1._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3865 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119_DATA, Q = \memory_ramBlocks_1._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3864 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118_DATA, Q = \memory_ramBlocks_1._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3863 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117_DATA, Q = \memory_ramBlocks_1._zz_5_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4059 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4066 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4065 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4069 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4068 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4067 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3866 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120_DATA, Q = \memory_ramBlocks_0._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3865 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119_DATA, Q = \memory_ramBlocks_0._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3864 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118_DATA, Q = \memory_ramBlocks_0._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3863 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117_DATA, Q = \memory_ramBlocks_0._zz_5_).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4089 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tdi, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_fragment).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4088 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tms, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_last).
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Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4087 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.\flowCCByToggle_1_.$logic_not$PQVexRiscvUlx3s.v:768$104_Y, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_target).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3901 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.DebugPlugin_busReadDataReg [31:5] \jtagBridge_1_.io_remote_rsp_payload_data [4:0] }, Q = \jtagBridge_1_.system_rsp_payload_data).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3900 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_payload_error).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4391 ($dffe) from module PQVexRiscvUlx3s.
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3899 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2088_Y, Q = \jtagBridge_1_.system_rsp_valid, rval = 1'1).
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Adding EN signal on $auto$opt_dff.cc:702:run$4392 ($sdff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_valid).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3898 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2066_Y, Q = \jtagBridge_1_.jtag_readArea_shifter).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3897 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2072_Y, Q = \jtagBridge_1_.jtag_idcodeArea_shifter, rval = 268443647).
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Adding EN signal on $auto$opt_dff.cc:702:run$4399 ($sdff) from module PQVexRiscvUlx3s (D = { \io_jtag_tdi \jtagBridge_1_.jtag_idcodeArea_shifter [31:1] }, Q = \jtagBridge_1_.jtag_idcodeArea_shifter).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3895 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$0\jtag_tap_instructionShift[3:0], Q = \jtagBridge_1_.jtag_tap_instructionShift).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3894 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2080_Y, Q = \jtagBridge_1_.jtag_tap_instruction, rval = 4'0001).
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Adding EN signal on $auto$opt_dff.cc:702:run$4406 ($sdff) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_tap_instructionShift, Q = \jtagBridge_1_.jtag_tap_instruction).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$3844 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_1, Q = \core_ibus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$3843 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_0, Q = \core_ibus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3848 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_2, Q = \core_dbus_decoder.logic_rspHits_2).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3847 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_1, Q = \core_dbus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3846 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_0, Q = \core_dbus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4091 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.pushing, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.risingOccupancy).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4090 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_payload_inst 1'0 }, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c._zz_3_).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4414 ($dffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$4051 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_125_[2:0], Q = \core_cpu._zz_125_).
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Adding EN signal on $flatten\core_cpu.$procdff$4043 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_2).
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Adding EN signal on $flatten\core_cpu.$procdff$4042 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_1).
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Adding EN signal on $flatten\core_cpu.$procdff$4041 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_0).
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Adding EN signal on $flatten\core_cpu.$procdff$4039 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mie_MSIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4038 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [7], Q = \core_cpu.CsrPlugin_mie_MTIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4037 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [11], Q = \core_cpu.CsrPlugin_mie_MEIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4033 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [31:2], Q = \core_cpu.CsrPlugin_mtvec_base).
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Adding EN signal on $flatten\core_cpu.$procdff$4032 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [1:0], Q = \core_cpu.CsrPlugin_mtvec_mode).
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Adding EN signal on $flatten\core_cpu.$procdff$4023 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_59_[0:0], Q = \core_cpu._zz_59_).
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Adding EN signal on $flatten\core_cpu.$procdff$4022 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_57_[0:0], Q = \core_cpu._zz_57_).
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Adding EN signal on $flatten\core_cpu.$procdff$4021 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_55_[0:0], Q = \core_cpu._zz_55_).
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Adding EN signal on $flatten\core_cpu.$procdff$4020 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \core_cpu.IBusSimplePlugin_fetchPc_inc).
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Adding EN signal on $flatten\core_cpu.$procdff$4017 ($adff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \core_cpu.IBusSimplePlugin_fetchPc_pcReg).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4468 ($adffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4468 ($adffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$4015 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_arbitration_isValid[0:0], Q = \core_cpu.memory_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$4014 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\execute_arbitration_isValid[0:0], Q = \core_cpu.execute_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$4013 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5381$942_Y, Q = \core_cpu.execute_CsrPlugin_csr_2946).
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Adding EN signal on $flatten\core_cpu.$procdff$4012 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5378$940_Y, Q = \core_cpu.execute_CsrPlugin_csr_2818).
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Adding EN signal on $flatten\core_cpu.$procdff$4011 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5375$938_Y, Q = \core_cpu.execute_CsrPlugin_csr_2944).
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Adding EN signal on $flatten\core_cpu.$procdff$4010 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5372$936_Y, Q = \core_cpu.execute_CsrPlugin_csr_2816).
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Adding EN signal on $flatten\core_cpu.$procdff$4009 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5369$934_Y, Q = \core_cpu.execute_CsrPlugin_csr_834).
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Adding EN signal on $flatten\core_cpu.$procdff$4008 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5366$932_Y, Q = \core_cpu.execute_CsrPlugin_csr_773).
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Adding EN signal on $flatten\core_cpu.$procdff$4007 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5363$930_Y, Q = \core_cpu.execute_CsrPlugin_csr_772).
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Adding EN signal on $flatten\core_cpu.$procdff$4006 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5360$928_Y, Q = \core_cpu.execute_CsrPlugin_csr_836).
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Adding EN signal on $flatten\core_cpu.$procdff$4005 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5357$926_Y, Q = \core_cpu.execute_CsrPlugin_csr_768).
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Adding EN signal on $flatten\core_cpu.$procdff$4004 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_29_, Q = \core_cpu.decode_to_execute_RS1).
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Adding EN signal on $flatten\core_cpu.$procdff$4002 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_ENABLE, Q = \core_cpu.execute_to_memory_MEMORY_ENABLE).
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Adding EN signal on $flatten\core_cpu.$procdff$4001 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_ENABLE, Q = \core_cpu.decode_to_execute_MEMORY_ENABLE).
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Adding EN signal on $flatten\core_cpu.$procdff$4000 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_BRANCH_DO, Q = \core_cpu.execute_to_memory_BRANCH_DO).
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Adding EN signal on $flatten\core_cpu.$procdff$3999 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS2_SIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3998 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HH, Q = \core_cpu.execute_to_memory_MUL_HH).
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Adding EN signal on $flatten\core_cpu.$procdff$3994 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_252_ \core_cpu._zz_253_ }, Q = \core_cpu.decode_to_execute_ALU_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3993 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_CSR, Q = \core_cpu.decode_to_execute_IS_CSR).
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Adding EN signal on $flatten\core_cpu.$procdff$3992 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_387_ \core_cpu._zz_388_ }, Q = \core_cpu.decode_to_execute_ALU_BITWISE_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3991 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2_FORCE_ZERO, Q = \core_cpu.decode_to_execute_SRC2_FORCE_ZERO).
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Adding EN signal on $flatten\core_cpu.$procdff$3990 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_DIV, Q = \core_cpu.execute_to_memory_IS_DIV).
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Adding EN signal on $flatten\core_cpu.$procdff$3989 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_DIV, Q = \core_cpu.decode_to_execute_IS_DIV).
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Adding EN signal on $flatten\core_cpu.$procdff$3988 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LH, Q = \core_cpu.execute_to_memory_MUL_LH).
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Adding EN signal on $flatten\core_cpu.$procdff$3986 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \core_cpu.execute_to_memory_MEMORY_STORE).
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Adding EN signal on $flatten\core_cpu.$procdff$3985 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_STORE, Q = \core_cpu.decode_to_execute_MEMORY_STORE).
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Adding EN signal on $flatten\core_cpu.$procdff$3984 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HL, Q = \core_cpu.execute_to_memory_MUL_HL).
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Adding EN signal on $flatten\core_cpu.$procdff$3982 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_VALID).
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Adding EN signal on $flatten\core_cpu.$procdff$3981 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_REGFILE_WRITE_VALID, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID).
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Adding SRST signal on $auto$opt_dff.cc:764:run$4501 ($dffe) from module PQVexRiscvUlx3s (D = \core_cpu._zz_191_, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
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Adding EN signal on $flatten\core_cpu.$procdff$3980 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \core_cpu.execute_to_memory_BRANCH_CALC).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4503 ($dffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$3979 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_CSR_WRITE_OPCODE, Q = \core_cpu.decode_to_execute_CSR_WRITE_OPCODE).
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Adding EN signal on $flatten\core_cpu.$procdff$3978 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_173_ [31:0], Q = \core_cpu.execute_to_memory_SHIFT_RIGHT).
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Adding EN signal on $flatten\core_cpu.$procdff$3975 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.decode_to_execute_PC).
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Adding EN signal on $flatten\core_cpu.$procdff$3974 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS1_SIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3973 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_EXECUTE_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3972 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_USE_SUB_LESS, Q = \core_cpu.decode_to_execute_SRC_USE_SUB_LESS).
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Adding EN signal on $flatten\core_cpu.$procdff$3969 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC2, Q = \core_cpu.execute_to_memory_SRC2).
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Adding EN signal on $flatten\core_cpu.$procdff$3968 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2, Q = \core_cpu.decode_to_execute_SRC2).
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Adding EN signal on $flatten\core_cpu.$procdff$3967 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_INSTRUCTION, Q = \core_cpu.execute_to_memory_INSTRUCTION).
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Adding EN signal on $flatten\core_cpu.$procdff$3966 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_62_, Q = \core_cpu.decode_to_execute_INSTRUCTION).
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Adding EN signal on $flatten\core_cpu.$procdff$3964 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_MUL, Q = \core_cpu.execute_to_memory_IS_MUL).
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Adding EN signal on $flatten\core_cpu.$procdff$3963 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_MUL, Q = \core_cpu.decode_to_execute_IS_MUL).
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Adding EN signal on $flatten\core_cpu.$procdff$3962 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.execute_to_memory_BYPASSABLE_MEMORY_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3961 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3960 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_255_ \core_cpu._zz_256_ }, Q = \core_cpu.decode_to_execute_BRANCH_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3959 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_DO_EBREAK, Q = \core_cpu.decode_to_execute_DO_EBREAK).
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Adding EN signal on $flatten\core_cpu.$procdff$3957 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC1, Q = \core_cpu.execute_to_memory_SRC1).
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Adding EN signal on $flatten\core_cpu.$procdff$3956 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC1, Q = \core_cpu.decode_to_execute_SRC1).
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Adding EN signal on $flatten\core_cpu.$procdff$3955 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_LESS_UNSIGNED, Q = \core_cpu.decode_to_execute_SRC_LESS_UNSIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3953 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB [1:0], Q = \core_cpu.execute_to_memory_MEMORY_ADDRESS_LOW).
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Adding EN signal on $flatten\core_cpu.$procdff$3950 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_27_, Q = \core_cpu.decode_to_execute_RS2).
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Adding EN signal on $flatten\core_cpu.$procdff$3949 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_43_, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_DATA).
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Adding EN signal on $flatten\core_cpu.$procdff$3948 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SHIFT_CTRL, Q = \core_cpu.execute_to_memory_SHIFT_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3947 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_277_ \core_cpu._zz_13_ [0] }, Q = \core_cpu.decode_to_execute_SHIFT_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3945 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_ENV_CTRL, Q = \core_cpu.execute_to_memory_ENV_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3944 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_20_, Q = \core_cpu.decode_to_execute_ENV_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3943 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LL, Q = \core_cpu.execute_to_memory_MUL_LL).
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Adding EN signal on $flatten\core_cpu.$procdff$3942 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_228_ [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_div_result).
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Adding SRST signal on $flatten\core_cpu.$procdff$3941 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2417_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_done, rval = 1'0).
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Adding EN signal on $auto$opt_dff.cc:702:run$4536 ($sdff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.memory_MulDivIterativePlugin_div_done).
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Adding EN signal on $flatten\core_cpu.$procdff$3940 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$logic_and$PQVexRiscvUlx3s.v:5165$861_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_needRevert).
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Adding SRST signal on $flatten\core_cpu.$procdff$3939 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2263_Y, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0], rval = 0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3939 ($dff) from module PQVexRiscvUlx3s (D = 33'000000000000000000000000000000000, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [64:32]).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4539 ($sdff) from module PQVexRiscvUlx3s (D = \core_cpu.memory_MulDivIterativePlugin_div_stage_0_outRemainder, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3938 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852_Y, Q = \core_cpu.memory_MulDivIterativePlugin_rs2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3937 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849_Y [32], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [32]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3937 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0] [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3934 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2439_Y, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4559 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege, rval = 2'11).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4562 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4562 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3933 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2447_Y, Q = \core_cpu.CsrPlugin_interrupt_code).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2445_Y [3], Q = \core_cpu.CsrPlugin_interrupt_code [3], rval = 1'1).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2443_Y [2], Q = \core_cpu.CsrPlugin_interrupt_code [2], rval = 1'0).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_code [1:0], rval = 2'11).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4574 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4574 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3932 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842_Y, Q = \core_cpu.CsrPlugin_minstret).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3930 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.CsrPlugin_interrupt_code, Q = \core_cpu.CsrPlugin_mcause_exceptionCode).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3929 ($dff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.CsrPlugin_mcause_interrupt).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4581 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$3928 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mip_MSIP, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3925 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.CsrPlugin_mepc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3922 ($dff) from module PQVexRiscvUlx3s (D = { $flatten\core_cpu.$0\_zz_62_[31:0] [31:25] $flatten\core_cpu.$0\_zz_62_[31:0] [14:0] }, Q = { \core_cpu._zz_62_ [31:25] \core_cpu._zz_62_ [14:0] }).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3920 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_58_, Q = \core_cpu._zz_60_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3919 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_fetchPc_pcReg, Q = \core_cpu._zz_58_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3916 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\DebugPlugin_busReadDataReg[31:0], Q = \core_cpu.DebugPlugin_busReadDataReg).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3915 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3914 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3913 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3909 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3908 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3907 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3904 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [36], Q = \core_cpu.DebugPlugin_stepIt).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3902 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2224_Y, Q = \core_cpu.DebugPlugin_resetIt).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4077 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4105 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\break_counter[6:0], Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.break_counter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4102 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_2).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4101 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.io_rxd_buffercc.buffers_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4095 ($dff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$or$PQVexRiscvUlx3s.v:0$80_Y, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_shifter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4077 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3881 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readOverflowError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readOverflowError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3880 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3879 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_readIntEnable).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3878 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_writeIntEnable).
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 230 unused cells and 258 unused wires.
|
|
<suppressed ~235 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~33 debug messages>
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~272 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~45 debug messages>
|
|
Removed a total of 15 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4592 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4592 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4578 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4578 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4289 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4287 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4287 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 23 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.13.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~273 debug messages>
|
|
|
|
2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4591 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4591 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~273 debug messages>
|
|
|
|
2.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4587 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4587 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4506 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4506 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~273 debug messages>
|
|
|
|
2.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4595 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2234_Y [1:0], Q = \core_cpu.DebugPlugin_busReadDataReg [1:0], rval = 2'00).
|
|
|
|
2.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.37. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~274 debug messages>
|
|
|
|
2.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.40. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.41. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.43. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.44. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1550 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1556 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4551 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4457 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4219 ($eq).
|
|
Removed top 31 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4054 ($dff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4050 ($adff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$auto$opt_dff.cc:764:run$4512 ($dffe).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3400 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3398 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3264_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3062_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3055_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2952_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2948_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2943_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2939_CMP0 ($eq).
|
|
Removed top 12 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2793 ($pmux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2787_CMP0 ($eq).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2712_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2645 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2641 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2625 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2617 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2613 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2519 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2517 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2513 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2511 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2507 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2498 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2497_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2496_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2495_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2493 ($mux).
|
|
Removed top 7 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2469 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2443 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2425 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2423 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2234 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2222 ($mux).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2158_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2150_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2143_CMP0 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5369$934 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5366$932 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5363$930 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5360$928 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5357$926 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add).
|
|
Removed top 1 bits (of 33) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:5163$848 ($mux).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5163$847 ($not).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5163$847 ($not).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842 ($add).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813 ($sub).
|
|
Removed top 20 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$783 ($or).
|
|
Removed top 19 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or).
|
|
Removed top 20 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or).
|
|
Removed top 19 bits (of 32) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705 ($sub).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4432$677 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4329$661 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4147$643 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4147$642 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4146$638 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4146$637 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4144$634 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4144$633 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4143$632 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4143$631 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4142$630 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4142$629 ($and).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550 ($sub).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:3294$427 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2683$412 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2682$410 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2682$409 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2680$408 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2678$407 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2672$402 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2670$401 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2670$400 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2668$399 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2667$397 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2667$396 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2665$395 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2663$393 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2662$392 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2662$391 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2660$390 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2651$386 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2651$385 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2648$384 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2647$383 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2647$382 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2645$381 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2643$380 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2641$379 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2634$376 ($eq).
|
|
Removed top 3 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2634$375 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2632$374 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2630$373 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2628$372 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2627$371 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2626$370 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2625$369 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2625$368 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2618$365 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2617$364 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2614$363 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2614$362 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2611$361 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2609$360 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2602$354 ($eq).
|
|
Removed top 11 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2602$353 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2600$352 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2599$351 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2599$350 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2598$349 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2598$348 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2597$347 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2597$346 ($and).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2595$345 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2593$344 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2585$341 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2582$340 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2581$339 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2580$338 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2579$336 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2579$335 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2578$334 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2576$332 ($and).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2569$328 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2568$327 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2568$326 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2567$325 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2567$324 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2559$320 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2555$314 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2553$313 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2548$309 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2548$308 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2547$307 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2547$306 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2546$305 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2546$304 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2544$303 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2537$299 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2537$298 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2536$297 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2535$295 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2534$293 ($and).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 ($add).
|
|
Removed top 31 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:2497$283 ($mux).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273 ($not).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273 ($not).
|
|
Removed top 15 bits (of 48) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sshr$PQVexRiscvUlx3s.v:2458$266 ($sshr).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2139_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2138_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2135_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2134_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2133_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2079_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2078_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2064 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5752$976 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5737$973 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5736$972 ($eq).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5704$970 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5695$967 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5674$960 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5665$957 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2060 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2058 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2054 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2042 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4418 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4376 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4360 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4245 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3505 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3507 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4080 ($dff).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3505 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3507 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4080 ($dff).
|
|
Removed top 19 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4201 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4197 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3641 ($mux).
|
|
Removed top 7 bits (of 8) from port A of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$shl$PQVexRiscvUlx3s.v:0$77 ($shl).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
Removed top 6 bits (of 7) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
Removed top 2 bits (of 5) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1887_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1880 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1878 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1874 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1872 ($mux).
|
|
Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerB.$procmux$3472 ($mux).
|
|
Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerA.$procmux$3472 ($mux).
|
|
Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156 ($add).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1769_CMP0 ($eq).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1732_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1720_CMP0 ($eq).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1707_CMP0 ($eq).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1696_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1691_CMP0 ($eq).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1681_CMP0 ($eq).
|
|
Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1676_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1669_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6874$1105 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6873$1102 ($eq).
|
|
Removed top 3 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6872$1099 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\apb3Router_1_.$procmux$1654_CMP0 ($eq).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3862 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3859 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3856 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3853 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1638 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1636 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1632 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1630 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1626 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1624 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1620 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1618 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3862 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3859 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3856 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3853 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1638 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1636 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1632 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1630 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1626 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1624 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1620 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1618 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$procmux$1614_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3442 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3444 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4064 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3446 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3450 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1196$182 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procmux$3464 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3442 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3444 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4064 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3446 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3450 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1196$182 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procmux$3464 ($mux).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub).
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0].
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849_Y.
|
|
Removed top 1 bits (of 2) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273_Y.
|
|
Removed top 19 bits (of 32) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5665$957_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5674$960_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5695$967_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5704$970_Y.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3UartCtrl_1__io_apb_PRDATA.
|
|
Removed top 15 bits (of 32) from wire PQVexRiscvUlx3s.muraxApb3Timer_1__io_apb_PRDATA.
|
|
|
|
2.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 77 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.17. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.21. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.3. Continuing TECHMAP pass.
|
|
Using template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\_80_mul for cells of type $mul.
|
|
Using template $paramod\$__MUL18X18\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=32\A_SIGNED=0\B_SIGNED=0 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~98 debug messages>
|
|
|
|
2.22. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module PQVexRiscvUlx3s:
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2494$280 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2505$286 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852 ($add).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813 ($sub).
|
|
creating $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 ($add).
|
|
creating $macc model for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192 ($sub).
|
|
creating $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 ($add).
|
|
creating $macc model for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add).
|
|
creating $macc model for $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156 ($add).
|
|
creating $macc model for $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165 ($add).
|
|
creating $macc model for $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165 ($add).
|
|
creating $macc model for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992 ($add).
|
|
merging $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 into $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229.
|
|
merging $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 into $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 into $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2505$286 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2494$280 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704.
|
|
creating $alu model for $macc $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292.
|
|
creating $alu model for $macc $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165.
|
|
creating $alu model for $macc $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156.
|
|
creating $alu model for $macc $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008.
|
|
creating $macc cell for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192: $auto$alumacc.cc:365:replace_macc$4675
|
|
creating $macc cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550: $auto$alumacc.cc:365:replace_macc$4676
|
|
creating $macc cell for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229: $auto$alumacc.cc:365:replace_macc$4677
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279: $auto$alumacc.cc:365:replace_macc$4678
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284: $auto$alumacc.cc:365:replace_macc$4679
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269: $auto$alumacc.cc:365:replace_macc$4680
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008: $auto$alumacc.cc:485:replace_alu$4681
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4684
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4687
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4690
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112: $auto$alumacc.cc:485:replace_alu$4695
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56: $auto$alumacc.cc:485:replace_alu$4698
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66: $auto$alumacc.cc:485:replace_alu$4701
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65: $auto$alumacc.cc:485:replace_alu$4704
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10: $auto$alumacc.cc:485:replace_alu$4707
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24: $auto$alumacc.cc:485:replace_alu$4710
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4713
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4716
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4719
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217: $auto$alumacc.cc:485:replace_alu$4724
|
|
creating $alu cell for $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165: $auto$alumacc.cc:485:replace_alu$4727
|
|
creating $alu cell for $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156: $auto$alumacc.cc:485:replace_alu$4730
|
|
creating $alu cell for $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165: $auto$alumacc.cc:485:replace_alu$4733
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292: $auto$alumacc.cc:485:replace_alu$4736
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518: $auto$alumacc.cc:485:replace_alu$4739
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689: $auto$alumacc.cc:485:replace_alu$4742
|
|
creating $alu cell for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992: $auto$alumacc.cc:485:replace_alu$4745
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704: $auto$alumacc.cc:485:replace_alu$4748
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841: $auto$alumacc.cc:485:replace_alu$4751
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842: $auto$alumacc.cc:485:replace_alu$4754
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849: $auto$alumacc.cc:485:replace_alu$4757
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852: $auto$alumacc.cc:485:replace_alu$4760
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275: $auto$alumacc.cc:485:replace_alu$4763
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705: $auto$alumacc.cc:485:replace_alu$4766
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813: $auto$alumacc.cc:485:replace_alu$4769
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211: $auto$alumacc.cc:485:replace_alu$4772
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173: $auto$alumacc.cc:485:replace_alu$4775
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173: $auto$alumacc.cc:485:replace_alu$4778
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211: $auto$alumacc.cc:485:replace_alu$4781
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217: $auto$alumacc.cc:485:replace_alu$4784
|
|
created 34 $alu and 6 $macc cells.
|
|
|
|
2.23. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.23.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~24 debug messages>
|
|
Removed a total of 8 cells.
|
|
|
|
2.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~244 debug messages>
|
|
|
|
2.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.23.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3861 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3858 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3855 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3861 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3858 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3855 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4398 ($dffe) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_readArea_shifter [2], Q = \jtagBridge_1_.jtag_readArea_shifter [1], rval = 1'0).
|
|
|
|
2.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 9 unused cells and 75 unused wires.
|
|
<suppressed ~38 debug messages>
|
|
|
|
2.23.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~238 debug messages>
|
|
|
|
2.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.23.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.23.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.24. Executing MEMORY pass.
|
|
|
|
2.24.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.24.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:0$949' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1147' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1148' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1149' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1150' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$233' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1147' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1148' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1149' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1150' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$233' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2686$414' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2692$416' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1336$200' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1336$200' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
|
|
2.24.3. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 43 unused cells and 55 unused wires.
|
|
<suppressed ~44 debug messages>
|
|
|
|
2.24.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.24.6. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.25. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol0:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol0.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol1:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol1.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol2:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol2.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol3:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol3.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol0:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol0.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol1:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol1.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol2:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol2.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol3:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol3.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
|
|
2.27. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
|
|
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.27.2. Continuing TECHMAP pass.
|
|
Using template $paramod$38262e435a9f54db3b5bdc33b5e39b1fffa1b883\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
No more expansions possible.
|
|
<suppressed ~89 debug messages>
|
|
|
|
2.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.2.
|
|
Updated properties: dups=2 waste=0 efficiency=50
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: core_cpu.RegFilePlugin_regFile.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: core_cpu.RegFilePlugin_regFile.0.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: core_cpu.RegFilePlugin_regFile.0.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: core_cpu.RegFilePlugin_regFile.0.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: core_cpu.RegFilePlugin_regFile.1.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: core_cpu.RegFilePlugin_regFile.1.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: core_cpu.RegFilePlugin_regFile.1.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: core_cpu.RegFilePlugin_regFile.1.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: core_cpu.RegFilePlugin_regFile.2.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: core_cpu.RegFilePlugin_regFile.2.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: core_cpu.RegFilePlugin_regFile.2.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: core_cpu.RegFilePlugin_regFile.2.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: core_cpu.RegFilePlugin_regFile.3.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: core_cpu.RegFilePlugin_regFile.3.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: core_cpu.RegFilePlugin_regFile.3.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: core_cpu.RegFilePlugin_regFile.3.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: core_cpu.RegFilePlugin_regFile.4.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: core_cpu.RegFilePlugin_regFile.4.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: core_cpu.RegFilePlugin_regFile.4.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: core_cpu.RegFilePlugin_regFile.4.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: core_cpu.RegFilePlugin_regFile.5.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: core_cpu.RegFilePlugin_regFile.5.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: core_cpu.RegFilePlugin_regFile.5.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: core_cpu.RegFilePlugin_regFile.5.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: core_cpu.RegFilePlugin_regFile.6.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: core_cpu.RegFilePlugin_regFile.6.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: core_cpu.RegFilePlugin_regFile.6.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: core_cpu.RegFilePlugin_regFile.6.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: core_cpu.RegFilePlugin_regFile.7.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: core_cpu.RegFilePlugin_regFile.7.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: core_cpu.RegFilePlugin_regFile.7.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: core_cpu.RegFilePlugin_regFile.7.1.1
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
|
|
2.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.29.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~52 debug messages>
|
|
|
|
2.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~721 debug messages>
|
|
|
|
2.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~273 debug messages>
|
|
Removed a total of 91 cells.
|
|
|
|
2.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 3 unused cells and 1247 unused wires.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.30.5. Finished fast OPT passes.
|
|
|
|
2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
2.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~303 debug messages>
|
|
|
|
2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2445:
|
|
Old ports: A=4'0111, B=4'0011, Y=$flatten\core_cpu.$procmux$2445_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\core_cpu.$procmux$2445_Y [2]
|
|
New connections: { $flatten\core_cpu.$procmux$2445_Y [3] $flatten\core_cpu.$procmux$2445_Y [1:0] } = 3'011
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2662:
|
|
Old ports: A=4'0000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3:2] 2'11 }, Y=\core_cpu._zz_130_ [3:0]
|
|
New ports: A=3'000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3:2] 1'1 }, Y={ \core_cpu._zz_130_ [3:2] \core_cpu._zz_130_ [0] }
|
|
New connections: \core_cpu._zz_130_ [1] = \core_cpu._zz_130_ [0]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2793:
|
|
Old ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [30:25] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [30:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31:20] }, Y=\core_cpu.execute_BranchPlugin_branch_src2 [19:0]
|
|
New ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [24:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [24:20] }, Y={ \core_cpu.execute_BranchPlugin_branch_src2 [19:11] \core_cpu.execute_BranchPlugin_branch_src2 [4:0] }
|
|
New connections: \core_cpu.execute_BranchPlugin_branch_src2 [10:5] = \core_cpu.decode_to_execute_INSTRUCTION [30:25]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3044:
|
|
Old ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_69_ [7:0] \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated
|
|
New ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated [31:8]
|
|
New connections: \core_cpu.writeBack_DBusSimplePlugin_rspFormated [7:0] = \core_cpu._zz_69_ [7:0]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3061:
|
|
Old ports: A=\core_cpu.decode_to_execute_RS2, B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:0] }, Y=\_zz_20_
|
|
New ports: A=\core_cpu.decode_to_execute_RS2 [31:8], B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:8] }, Y=\_zz_20_ [31:8]
|
|
New connections: \_zz_20_ [7:0] = \core_cpu.decode_to_execute_RS2 [7:0]
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3115:
|
|
Old ports: A=0, B={ \core_cpu.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=30'000000000000000000000000000000, B=\core_cpu.CsrPlugin_mtvec_base, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955:
|
|
Old ports: A=4'0001, B=4'1001, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y [2:0] = 3'001
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956:
|
|
Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$4657 [1:0]
|
|
New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$4657 [0]
|
|
New connections: $auto$wreduce.cc:454:run$4657 [1] = $auto$wreduce.cc:454:run$4657 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959:
|
|
Old ports: A=4'0110, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [3] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [1] }
|
|
New connections: { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [2] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [0] } = { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961:
|
|
Old ports: A=4'0100, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y
|
|
New ports: A=2'01, B=2'10, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y [3:2]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963:
|
|
Old ports: A=4'1010, B=4'0010, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y [2:0] = 3'010
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964:
|
|
Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$4660 [2:0]
|
|
New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$4660 [2] $auto$wreduce.cc:454:run$4660 [0] }
|
|
New connections: $auto$wreduce.cc:454:run$4660 [1] = $auto$wreduce.cc:454:run$4660 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966:
|
|
Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:454:run$4661 [1:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4661 [1]
|
|
New connections: $auto$wreduce.cc:454:run$4661 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968:
|
|
Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:454:run$4663 [2:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4663 [2]
|
|
New connections: $auto$wreduce.cc:454:run$4663 [1:0] = 2'11
|
|
Consolidated identical input bits for $pmux cell $procmux$1563:
|
|
Old ports: A=4'1111, B=8'00010011, Y=\_zz_22_
|
|
New ports: A=2'11, B=4'0001, Y=\_zz_22_ [2:1]
|
|
New connections: { \_zz_22_ [3] \_zz_22_ [0] } = { \_zz_22_ [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $ternary$PQVexRiscvUlx3s.v:8194$1258:
|
|
Old ports: A={ \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \_zz_7_ [31:2] 2'00 }, Y=$ternary$PQVexRiscvUlx3s.v:8194$1258_Y
|
|
New ports: A=\core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2], B=\_zz_7_ [31:2], Y=$ternary$PQVexRiscvUlx3s.v:8194$1258_Y [31:2]
|
|
New connections: $ternary$PQVexRiscvUlx3s.v:8194$1258_Y [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3107:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B={ \core_cpu.CsrPlugin_mepc [31:2] 2'00 }, Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=\core_cpu.CsrPlugin_mepc [31:2], Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3112:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0], Y=\core_cpu.CsrPlugin_jumpInterface_payload
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\core_cpu.CsrPlugin_jumpInterface_payload [31:2]
|
|
New connections: \core_cpu.CsrPlugin_jumpInterface_payload [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:3749$513:
|
|
Old ports: A={ \core_cpu.execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\core_cpu.CsrPlugin_jumpInterface_payload, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload
|
|
New ports: A=\core_cpu.execute_to_memory_BRANCH_CALC [31:1], B={ \core_cpu.CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1]
|
|
New connections: \core_cpu.IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3088:
|
|
Old ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518_Y [31:2] 2'00 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload, Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] }
|
|
New ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518_Y [31:2] 1'0 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1] }
|
|
New connections: $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 20 changes.
|
|
|
|
2.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
2.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 8 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~302 debug messages>
|
|
|
|
2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ecp5_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Using extmapper simplemap for cells of type $adff.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $adffe.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc.
|
|
add \core_ibus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_valid (1 bits, unsigned)
|
|
add bits \core_ibus_decoder._zz_5_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
|
|
add { \core_cpu.execute_to_memory_MUL_HH \core_cpu.execute_to_memory_MUL_LL [31:16] } (48 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_LH (32 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_HL (32 bits, unsigned)
|
|
add \core_cpu.memory_to_writeBack_MUL [63:32] (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2506$287_Y (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2505$285_Y (32 bits, unsigned)
|
|
add 2 (32 bits, unsigned)
|
|
packed 2 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=33\B_WIDTH=32\Y_WIDTH=33 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
|
|
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
|
|
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=11 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=1\Y_WIDTH=20 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
|
|
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.77. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~2366 debug messages>
|
|
|
|
2.33.78. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~35 debug messages>
|
|
Removed 0 unused cells and 8 unused wires.
|
|
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu.
|
|
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=9 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=5 for cells of type $pmux.
|
|
add \core_dbus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.dBus_rsp_ready (1 bits, unsigned)
|
|
add bits \core_dbus_decoder._zz_6_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
add \core_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned)
|
|
add bits \core_cpu.IBusSimplePlugin_pending_inc (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
add \core_cpu.decode_to_execute_SRC1 (32 bits, signed)
|
|
add { 1'0 \core_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
|
|
add \core_cpu._zz_211_ (32 bits, signed)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=48 for cells of type $fa.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=2 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa.
|
|
Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=3 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~2966 debug messages>
|
|
|
|
2.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~3443 debug messages>
|
|
|
|
2.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~2103 debug messages>
|
|
Removed a total of 701 cells.
|
|
|
|
2.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1315 unused cells and 4250 unused wires.
|
|
<suppressed ~1321 debug messages>
|
|
|
|
2.34.5. Finished fast OPT passes.
|
|
|
|
2.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
2.37. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.37.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
|
|
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
|
|
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
|
|
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
|
|
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
|
|
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
|
|
Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_.
|
|
Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_.
|
|
Using template \$_DFFE_PP1N_ for cells of type $_DFFE_PP1N_.
|
|
No more expansions possible.
|
|
<suppressed ~2402 debug messages>
|
|
|
|
2.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~71 debug messages>
|
|
|
|
2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.40. Executing ECP5_GSR pass (implement FF init values).
|
|
Handling GSR in PQVexRiscvUlx3s.
|
|
|
|
2.41. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
2.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 11101 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.44. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.44.1. Extracting gate netlist of module `\PQVexRiscvUlx3s' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 6537 gates and 8799 wires to a netlist network with 2260 inputs and 1531 outputs.
|
|
|
|
2.44.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + dress
|
|
ABC: Total number of equiv classes = 2068.
|
|
ABC: Participating nodes from both networks = 4475.
|
|
ABC: Participating nodes from the first network = 2143. ( 76.62 % of nodes)
|
|
ABC: Participating nodes from the second network = 2332. ( 83.38 % of nodes)
|
|
ABC: Node pairs (any polarity) = 2143. ( 76.62 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 1679. ( 60.03 % of names can be moved)
|
|
ABC: Total runtime = 0.27 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.44.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 2795
|
|
ABC RESULTS: internal signals: 5008
|
|
ABC RESULTS: input signals: 2260
|
|
ABC RESULTS: output signals: 1531
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 5077 unused wires.
|
|
|
|
2.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.45.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429470991 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011101100000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11100000000000001111000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10110000000010110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001010001001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663244 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=48911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100110011001111000010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$33c350b0c33c8d11c06e32a4943a9c25a543a6b7\$lut for cells of type $lut.
|
|
Using template $paramod$89dd30d619d00b12368cbcf6b88c08bd89e1c657\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2147450880 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=386990080 for cells of type $lut.
|
|
Using template $paramod$1922694d1ba66dc9e8c99f5f26ba1b86bfc1d372\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod$ef003d70d3febf7a5568510cba4a0111646430ac\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429409791 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
|
|
Using template $paramod$f6783b5b9c23cd67232c94ac1b12661d5b0309d0\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196131771 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110101110001 for cells of type $lut.
|
|
Using template $paramod$c708770091716d95e2d30be87305b107dccb9e26\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16777216 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65536 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268500992 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
|
|
Using template $paramod$b1bd2a921ec0f1ea0cc7578a2bcf32d761c7f62f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut.
|
|
Using template $paramod$f340a7e85fbe3e11c384ecf1cd11a7f6ad674e2c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=218103821 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011000010110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000010010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=218103808 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=47883 for cells of type $lut.
|
|
Using template $paramod$31a944f0c6934f915f24e075bcacadd2906c8e5f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100000001000000010000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=251986703 for cells of type $lut.
|
|
Using template $paramod$078354ad4f08d5c6e8687216ff1586f28ff6611c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=285212671 for cells of type $lut.
|
|
Using template $paramod$1519fab0160880cb5431b6d4859cd9e32e014092\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101100111111111010000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001110101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001011010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2035471 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663091 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101000110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011010001001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100111111110000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549387 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011100000 for cells of type $lut.
|
|
Using template $paramod$d6a97cece58353cd8de5b6e824f1d055bdb32a45\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111110001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=458752 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111110101111000011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000011101111111111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=3003 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001000110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0110111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=31 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=7697919 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111110000000001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
|
|
Using template $paramod$1823a31c85f9522086df2e636a0e5ffeb1bbf92b\$lut for cells of type $lut.
|
|
Using template $paramod$6e8e9a95aa7012438678197fd66a79121b4bccb4\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268435456 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65408 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011111000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268398592 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065336832 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073709056 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000011111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111001100000001101111000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1142743210 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1333248160 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101011011100001111000011100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196148992 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011001111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101011100110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65344 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1099049025 for cells of type $lut.
|
|
Using template $paramod$ea79ac074ef5daf30bdd86a73922fd1b4427f4d0\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=33488896 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2004287600 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065304064 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001111101011110000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=8355711 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=267444928 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=125239296 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10100011 for cells of type $lut.
|
|
Using template $paramod$fa50846fb39690c96e73e2bf7881b0c024a78beb\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000000100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252641501 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111011100000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut.
|
|
Using template $paramod$f19bb2391741f41ed6688663c633088d08e018c2\$lut for cells of type $lut.
|
|
Using template $paramod$2a0a976802391efa54393fb43c1a1243cd176ffd\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111101001111111100000000 for cells of type $lut.
|
|
Using template $paramod$063f7b90c9d87abb5e00dc22f30b48c5d12e80b3\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101111111111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111000000001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100100010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001000100011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16639 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110111000010001110111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001100101010101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001100111111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111110111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110111011101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00011110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000101010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010101010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=866840816 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000100010000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429467376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252654421 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10001111111110001000100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111101011111100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut.
|
|
Using template $paramod$176d9ae664c431997aaa426f223ab1bcc6188d13\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=251723656 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101110 for cells of type $lut.
|
|
Using template $paramod$18ef73fafbda5af11588c66ef5f31f738568c5c8\$lut for cells of type $lut.
|
|
Using template $paramod$2ff21013616bea2c768a52e378d46babb5d3dc5a\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101111010000001100110011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111110100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100011100001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110110110010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001111111101 for cells of type $lut.
|
|
Using template $paramod$c6d51bbba2974d40075f64507965a1fed88c7c87\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101001010110100 for cells of type $lut.
|
|
Using template $paramod$9abd567e56fa5e5fe88aefab580dea7b3d3324a7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1431683900 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~6440 debug messages>
|
|
|
|
2.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in PQVexRiscvUlx3s.
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27959.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27961.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27978.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27965.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27988.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27984.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27976.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27980.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27986.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27990.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27996.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28000.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut2 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut3 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut4 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut5 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut6 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut7 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut2 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut3 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28099.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28096.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28108.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28100.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28103.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28117.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28104.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28105.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28120.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28125.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28135.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28413.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27770.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27794.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26189.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27791.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26128.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27314.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27780.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27768.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27788.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27137.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27138.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27297.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27058.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27280.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28131.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28101.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28097.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28085.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27331.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27790.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27779.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27774.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27769.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27348.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27246.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27631.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27643.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27614.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut6 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut7 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut6 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut7 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut2 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut3 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27497.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27501.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26942.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27492.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27493.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27505.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27476.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27439.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26214.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26960.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26964.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26963.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27039.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27060.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27119.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut6 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut7 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27101.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut6 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut7 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26905.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26127.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut3 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26926.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26927.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut6 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut7 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26222.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26222.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26016.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26833.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26821.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26820.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26819.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut2 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut4 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut5 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut6 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut7 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26884.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26866.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut3 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut4 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut5 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut7 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut2 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut3 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut4 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut5 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut5 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut6 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut2 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut3 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut4 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut5 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27000.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26982.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25885.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25887.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25889.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25898.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25912.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25923.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25934.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25939.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25974.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26011.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26824.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26998.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26129.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26127.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26146.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26189.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26196.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26244.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26300.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26305.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26311.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26354.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27045.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26175.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26579.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26579.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26664.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26659.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26662.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26665.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27765.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26724.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26725.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27038.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26723.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26757.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26978.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26785.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26800.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26817.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26818.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26823.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27020.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26819.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26820.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26827.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26829.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26833.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26837.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26841.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26843.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26848.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26999.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26864.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26865.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26866.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26869.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26869.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26871.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26855.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26865.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26879.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26881.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26883.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26883.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26884.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26885.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26888.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26890.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26885.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26888.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26901.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26903.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26903.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26904.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26905.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26904.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26908.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26908.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26910.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26923.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26925.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26925.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26926.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26927.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26930.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26930.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26932.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26942.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26944.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26945.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26946.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26945.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26949.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26949.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26951.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26946.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26944.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26960.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26962.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26963.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26964.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26967.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26967.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26969.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26962.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26978.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26980.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26981.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26982.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26985.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26985.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26987.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26981.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26980.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26998.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27000.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27007.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27007.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27010.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27020.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27022.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27022.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27029.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27038.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27040.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27045.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27048.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27058.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27060.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27040.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27100.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27065.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27068.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27065.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27080.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27089.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27082.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27099.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27106.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27106.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27109.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27119.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27121.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27080.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27121.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27128.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27137.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27139.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27140.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27144.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27144.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27147.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27157.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27159.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27169.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27181.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27183.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27190.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27201.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27203.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27210.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27221.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27766.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27230.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27241.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27242.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27243.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27583.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27246.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27248.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27258.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27259.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27260.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27263.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27265.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27259.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27275.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27276.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27277.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27595.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27280.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27282.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27276.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27292.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27293.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27294.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27297.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27299.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27293.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27309.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27310.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27311.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27314.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27316.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27310.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27326.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27327.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27328.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27331.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27333.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27343.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27344.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27345.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27348.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27350.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27360.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27362.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27626.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27369.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27380.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27381.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27382.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27385.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27387.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27397.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27399.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27406.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27417.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27418.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27419.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27422.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27424.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26822.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27418.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27434.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27435.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27436.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27439.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27441.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27448.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27435.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27451.lut1 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27476.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27483.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27483.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27484.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27487.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27513.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27492.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27493.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27496.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27496.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27497.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27500.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27500.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27501.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27504.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27504.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27505.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27507.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27507.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27509.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27509.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27512.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27512.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27513.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27515.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27515.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27517.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27517.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27518.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27520.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27520.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27522.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27524.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27526.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27528.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27528.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27530.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27532.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27532.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut0 (4 -> 2)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27551.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27159.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27524.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27558.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27565.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27572.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27583.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27584.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27963.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27595.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27596.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27603.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27614.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27615.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27626.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27631.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27632.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27664.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27676.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27688.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27099.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27745.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27787.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27782.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27772.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27905.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27783.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27990.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27996.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28000.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28006.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28008.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28010.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28012.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28006.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28010.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28098.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28063.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28087.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28102.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28087.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28107.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28096.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28097.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28098.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28099.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28100.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28101.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28102.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28103.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28104.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28105.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28106.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28107.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28108.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28106.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28111.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28114.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28111.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28117.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28114.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28137.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28120.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28121.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28142.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28125.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28128.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28138.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28121.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28131.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28128.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28143.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28134.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28135.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28137.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28138.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28139.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28140.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28141.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28142.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28143.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28141.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28139.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28134.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28140.lut1 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28237.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28235.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28418.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut1 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28413.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut0 (4 -> 0)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28417.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28418.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28420.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28420.lut0 (4 -> 3)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28446.lut0 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28451.lut1 (4 -> 1)
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Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28451.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28508.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28552.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28480.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28480.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28569.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28565.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28504.lut0 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28507.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28508.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28446.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28517.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28517.lut0 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28507.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28534.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28534.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28562.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28540.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28540.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28504.lut1 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28546.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28546.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28567.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28552.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28557.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28560.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28562.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28557.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28565.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28567.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28569.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28571.lut0 (4 -> 3)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28560.lut1 (4 -> 1)
|
|
Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28571.lut1 (4 -> 1)
|
|
Removed 0 unused cells and 5990 unused wires.
|
|
|
|
2.47. Executing AUTONAME pass.
|
|
Renamed 120855 objects in module PQVexRiscvUlx3s (99 iterations).
|
|
<suppressed ~9012 debug messages>
|
|
|
|
2.48. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.48.1. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
|
|
2.48.2. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Removed 0 unused modules.
|
|
|
|
2.49. Printing statistics.
|
|
|
|
=== PQVexRiscvUlx3s ===
|
|
|
|
Number of wires: 4103
|
|
Number of wire bits: 22419
|
|
Number of public wires: 4103
|
|
Number of public wire bits: 22419
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 6522
|
|
CCU2C 260
|
|
DP16KD 64
|
|
L6MUX21 70
|
|
LUT4 3303
|
|
MULT18X18D 4
|
|
PFUMX 512
|
|
TRELLIS_DPR16X4 38
|
|
TRELLIS_FF 2271
|
|
|
|
2.50. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.51. Executing JSON backend.
|
|
|
|
Warnings: 1 unique messages, 2 total
|
|
End of script. Logfile hash: 86ff1874c2, CPU: user 11.28s system 0.12s, MEM: 316.02 MB peak
|
|
Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
|
|
Time spent: 16% 1x abc (2 sec), 15% 28x opt_clean (2 sec), ...
|