You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
7798 lines
610 KiB
7798 lines
610 KiB
|
|
/----------------------------------------------------------------------------\
|
|
| |
|
|
| yosys -- Yosys Open SYnthesis Suite |
|
|
| |
|
|
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
|
|
| |
|
|
| Permission to use, copy, modify, and/or distribute this software for any |
|
|
| purpose with or without fee is hereby granted, provided that the above |
|
|
| copyright notice and this permission notice appear in all copies. |
|
|
| |
|
|
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
|
|
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
|
|
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
|
|
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
|
|
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
|
|
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
|
|
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
|
|
| |
|
|
\----------------------------------------------------------------------------/
|
|
|
|
Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
|
|
|
|
|
|
-- Parsing `PQVexRiscvUlx3s.v' using frontend `verilog' --
|
|
|
|
1. Executing Verilog-2005 frontend: PQVexRiscvUlx3s.v
|
|
Parsing Verilog input from `PQVexRiscvUlx3s.v' to AST representation.
|
|
Generating RTLIL representation for module `\BufferCC'.
|
|
Generating RTLIL representation for module `\BufferCC_1_'.
|
|
Generating RTLIL representation for module `\UartCtrlTx'.
|
|
Generating RTLIL representation for module `\UartCtrlRx'.
|
|
Generating RTLIL representation for module `\StreamFifoLowLatency'.
|
|
Generating RTLIL representation for module `\FlowCCByToggle'.
|
|
Generating RTLIL representation for module `\UartCtrl'.
|
|
Generating RTLIL representation for module `\StreamFifo'.
|
|
Generating RTLIL representation for module `\StreamArbiter'.
|
|
Generating RTLIL representation for module `\StreamFork'.
|
|
Generating RTLIL representation for module `\StreamFifoLowLatency_1_'.
|
|
Generating RTLIL representation for module `\BufferCC_2_'.
|
|
Generating RTLIL representation for module `\VexRiscv'.
|
|
Generating RTLIL representation for module `\JtagBridge'.
|
|
Generating RTLIL representation for module `\SystemDebugger'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'.
|
|
Generating RTLIL representation for module `\Apb3UartCtrl'.
|
|
Generating RTLIL representation for module `\MyMem'.
|
|
Generating RTLIL representation for module `\Apb3Decoder'.
|
|
Generating RTLIL representation for module `\Apb3Router'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s_1_'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusDecoder'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusDecoder_1_'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusArbiter'.
|
|
Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_1_'.
|
|
Generating RTLIL representation for module `\PQVexRiscvUlx3s'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
-- Running command `synth_ecp5 -top PQVexRiscvUlx3s -json PQVexRiscvUlx3s.json' --
|
|
|
|
2. Executing SYNTH_ECP5 pass.
|
|
|
|
2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
|
|
Generating RTLIL representation for module `\LUT4'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT5'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT6'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT7'.
|
|
Generating RTLIL representation for module `\L6MUX21'.
|
|
Generating RTLIL representation for module `\CCU2C'.
|
|
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
|
|
Generating RTLIL representation for module `\PFUMX'.
|
|
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
|
|
Generating RTLIL representation for module `\DPR16X4C'.
|
|
Generating RTLIL representation for module `\LUT2'.
|
|
Generating RTLIL representation for module `\TRELLIS_FF'.
|
|
Generating RTLIL representation for module `\TRELLIS_IO'.
|
|
Generating RTLIL representation for module `\INV'.
|
|
Generating RTLIL representation for module `\TRELLIS_SLICE'.
|
|
Generating RTLIL representation for module `\DP16KD'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
|
|
Generating RTLIL representation for module `\MULT18X18D'.
|
|
Generating RTLIL representation for module `\ALU54B'.
|
|
Generating RTLIL representation for module `\EHXPLLL'.
|
|
Generating RTLIL representation for module `\DTR'.
|
|
Generating RTLIL representation for module `\OSCG'.
|
|
Generating RTLIL representation for module `\USRMCLK'.
|
|
Generating RTLIL representation for module `\JTAGG'.
|
|
Generating RTLIL representation for module `\DELAYF'.
|
|
Generating RTLIL representation for module `\DELAYG'.
|
|
Generating RTLIL representation for module `\IDDRX1F'.
|
|
Generating RTLIL representation for module `\IDDRX2F'.
|
|
Generating RTLIL representation for module `\IDDR71B'.
|
|
Generating RTLIL representation for module `\IDDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX1F'.
|
|
Generating RTLIL representation for module `\ODDRX2F'.
|
|
Generating RTLIL representation for module `\ODDR71B'.
|
|
Generating RTLIL representation for module `\OSHX2A'.
|
|
Generating RTLIL representation for module `\ODDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQSB'.
|
|
Generating RTLIL representation for module `\TSHX2DQA'.
|
|
Generating RTLIL representation for module `\TSHX2DQSA'.
|
|
Generating RTLIL representation for module `\DQSBUFM'.
|
|
Generating RTLIL representation for module `\DDRDLLA'.
|
|
Generating RTLIL representation for module `\CLKDIVF'.
|
|
Generating RTLIL representation for module `\ECLKSYNCB'.
|
|
Generating RTLIL representation for module `\ECLKBRIDGECS'.
|
|
Generating RTLIL representation for module `\DCCA'.
|
|
Generating RTLIL representation for module `\DCUA'.
|
|
Generating RTLIL representation for module `\EXTREFB'.
|
|
Generating RTLIL representation for module `\PCSCLKDIV'.
|
|
Generating RTLIL representation for module `\PUR'.
|
|
Generating RTLIL representation for module `\GSR'.
|
|
Generating RTLIL representation for module `\SGSR'.
|
|
Generating RTLIL representation for module `\PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.3. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.3.1. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Used module: \PipelinedMemoryBusArbiter_1_
|
|
Used module: \StreamFifoLowLatency_1_
|
|
Used module: \StreamFork
|
|
Used module: \StreamArbiter
|
|
Used module: \PipelinedMemoryBusArbiter
|
|
Used module: \PipelinedMemoryBusDecoder_1_
|
|
Used module: \PipelinedMemoryBusDecoder
|
|
Used module: \PipelinedMemoryBusRamUlx3s_1_
|
|
Used module: \PipelinedMemoryBusRamUlx3s
|
|
Used module: \Apb3Router
|
|
Used module: \Apb3Decoder
|
|
Used module: \MyMem
|
|
Used module: \Apb3UartCtrl
|
|
Used module: \StreamFifo
|
|
Used module: \UartCtrl
|
|
Used module: \UartCtrlRx
|
|
Used module: \BufferCC
|
|
Used module: \UartCtrlTx
|
|
Used module: \PipelinedMemoryBusToApbBridge
|
|
Used module: \SystemDebugger
|
|
Used module: \JtagBridge
|
|
Used module: \FlowCCByToggle
|
|
Used module: \BufferCC_1_
|
|
Used module: \VexRiscv
|
|
Used module: \StreamFifoLowLatency
|
|
Used module: \BufferCC_2_
|
|
|
|
2.3.2. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Used module: \PipelinedMemoryBusArbiter_1_
|
|
Used module: \StreamFifoLowLatency_1_
|
|
Used module: \StreamFork
|
|
Used module: \StreamArbiter
|
|
Used module: \PipelinedMemoryBusArbiter
|
|
Used module: \PipelinedMemoryBusDecoder_1_
|
|
Used module: \PipelinedMemoryBusDecoder
|
|
Used module: \PipelinedMemoryBusRamUlx3s_1_
|
|
Used module: \PipelinedMemoryBusRamUlx3s
|
|
Used module: \Apb3Router
|
|
Used module: \Apb3Decoder
|
|
Used module: \MyMem
|
|
Used module: \Apb3UartCtrl
|
|
Used module: \StreamFifo
|
|
Used module: \UartCtrl
|
|
Used module: \UartCtrlRx
|
|
Used module: \BufferCC
|
|
Used module: \UartCtrlTx
|
|
Used module: \PipelinedMemoryBusToApbBridge
|
|
Used module: \SystemDebugger
|
|
Used module: \JtagBridge
|
|
Used module: \FlowCCByToggle
|
|
Used module: \BufferCC_1_
|
|
Used module: \VexRiscv
|
|
Used module: \StreamFifoLowLatency
|
|
Used module: \BufferCC_2_
|
|
Removed 0 unused modules.
|
|
|
|
2.4. Executing PROC pass (convert processes to netlists).
|
|
|
|
2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1402'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:0$1100'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1483 in module TRELLIS_FF.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7722$1255 in module PQVexRiscvUlx3s.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7663$1242 in module PQVexRiscvUlx3s.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7613$1235 in module PQVexRiscvUlx3s.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7591$1230 in module PQVexRiscvUlx3s.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7033$1223 in module PipelinedMemoryBusArbiter_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7026$1222 in module PipelinedMemoryBusArbiter_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6850$1218 in module PipelinedMemoryBusDecoder_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6838$1200 in module PipelinedMemoryBusDecoder_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6825$1196 in module PipelinedMemoryBusDecoder_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6812$1192 in module PipelinedMemoryBusDecoder_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6800$1189 in module PipelinedMemoryBusDecoder_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6728$1181 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6716$1160 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6703$1156 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6690$1152 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6677$1148 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6662$1145 in module PipelinedMemoryBusDecoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6587$1133 in module PipelinedMemoryBusRamUlx3s_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6519$1088 in module PipelinedMemoryBusRamUlx3s.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6420$1054 in module Apb3Router.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6376$1053 in module Apb3Decoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6368$1052 in module Apb3Decoder.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6307$1029 in module MyMem.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6221$1020 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6201$1019 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6184$1018 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6167$1017 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6150$1016 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6133$1015 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6113$1010 in module Apb3UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6105$1009 in module Apb3UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6098$1008 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6078$1007 in module Apb3UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6042$992 in module Apb3UartCtrl.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5852$987 in module PipelinedMemoryBusToApbBridge.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5842$984 in module PipelinedMemoryBusToApbBridge.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5828$982 in module PipelinedMemoryBusToApbBridge.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5773$978 in module SystemDebugger.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5747$974 in module SystemDebugger.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5636$957 in module JtagBridge.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5608$954 in module JtagBridge.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5554$937 in module JtagBridge.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5330$929 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4715$773 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4706$764 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4699$763 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4692$762 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4685$761 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4677$760 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4669$759 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4660$758 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4651$757 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4642$756 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4623$755 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4555$701 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4544$699 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4521$698 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4497$686 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4488$683 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4479$682 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4462$677 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4448$676 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4419$671 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4339$665 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4327$658 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4291$649 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4263$647 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4183$639 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4166$638 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4101$635 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4087$634 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4073$630 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4064$628 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4028$606 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4014$590 in module VexRiscv.
|
|
Marked 16 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3967$585 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3954$583 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3943$582 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3933$579 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3918$573 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3904$572 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3837$565 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3821$563 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3806$562 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3796$552 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3772$543 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3737$531 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3716$525 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3690$507 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3672$501 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3663$499 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3656$498 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3648$496 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3637$492 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3630$490 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3623$489 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3607$488 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3597$487 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3590$486 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3579$484 in module VexRiscv.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3558$483 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3544$482 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3536$481 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3527$480 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3519$479 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3506$469 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3497$468 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3488$467 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3481$466 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3474$465 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3462$457 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3453$456 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3440$446 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3421$445 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3410$444 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3382$441 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3367$440 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3360$438 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3352$436 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3314$435 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3283$433 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3253$431 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1333$214 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1325$210 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1305$199 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1296$196 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1289$195 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1278$193 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1269$190 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1262$189 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1255$188 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1182$178 in module StreamFork.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1162$171 in module StreamFork.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1114$168 in module StreamArbiter.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1038$150 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1020$132 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1011$129 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1004$128 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:997$126 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:988$123 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:981$122 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:974$121 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:899$111 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:884$110 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:877$109 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:780$106 in module FlowCCByToggle.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:706$99 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:697$97 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:689$96 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:680$95 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:665$87 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:658$86 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:649$84 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:642$83 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:635$82 in module StreamFifoLowLatency.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:553$61 in module UartCtrlRx.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:474$43 in module UartCtrlRx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:461$41 in module UartCtrlRx.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:431$39 in module UartCtrlRx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:260$14 in module UartCtrlTx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:238$13 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:219$11 in module UartCtrlTx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:208$9 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:198$6 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:97$1 in module BufferCC.
|
|
Removed a total of 0 dead cases.
|
|
|
|
2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 30 redundant assignments.
|
|
Promoted 404 assignments to connections.
|
|
|
|
2.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1487'.
|
|
Set init value: \Q = 1'0
|
|
Found init rule in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5442$969'.
|
|
Set init value: \jtag_tap_fsm_state = 4'0000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2027$934'.
|
|
Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2026$933'.
|
|
Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Set init value: \inputArea_target = 1'0
|
|
|
|
2.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
Found async reset \resetCtrl_mainClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7722$1255'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6850$1218'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6728$1181'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6587$1133'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6519$1088'.
|
|
Found async reset \resetCtrl_systemClockReset in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
Found async reset \resetCtrl_mainClockReset in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
Found async reset \resetCtrl_mainClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
Found async reset \resetCtrl_systemClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found async reset \resetCtrl_mainClockReset in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found async reset \resetCtrl_systemClockReset in `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
|
|
2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1487'.
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1483'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1480'.
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
1/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_EN[3:0]$1462
|
|
2/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_DATA[3:0]$1461
|
|
3/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_ADDR[3:0]$1460
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1425'.
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
1/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_EN[3:0]$1406
|
|
2/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_DATA[3:0]$1405
|
|
3/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_ADDR[3:0]$1404
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1402'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7722$1255'.
|
|
1/1: $0\_zz_35_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7718$1254'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
1/16: $0\_zz_34_[3:0]
|
|
2/16: $0\_zz_33_[31:0]
|
|
3/16: $0\_zz_32_[31:0]
|
|
4/16: $0\_zz_31_[0:0]
|
|
5/16: $0\_zz_28_[3:0]
|
|
6/16: $0\_zz_27_[31:0]
|
|
7/16: $0\_zz_26_[31:0]
|
|
8/16: $0\_zz_25_[0:0]
|
|
9/16: $0\_zz_15_[3:0]
|
|
10/16: $0\_zz_14_[31:0]
|
|
11/16: $0\_zz_13_[31:0]
|
|
12/16: $0\_zz_12_[0:0]
|
|
13/16: $0\_zz_9_[3:0]
|
|
14/16: $0\_zz_8_[31:0]
|
|
15/16: $0\_zz_7_[31:0]
|
|
16/16: $0\_zz_6_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
1/4: $0\_zz_30_[0:0]
|
|
2/4: $0\_zz_24_[0:0]
|
|
3/4: $0\_zz_11_[0:0]
|
|
4/4: $0\_zz_5_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7655$1241'.
|
|
1/1: $0\resetCtrl_systemClockReset[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7613$1235'.
|
|
1/1: $1\_zz_22_[3:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7591$1230'.
|
|
1/1: $1\core_externalInterrupt[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7033$1223'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7026$1222'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6858$1220'.
|
|
1/2: $0\logic_rspHits_1[0:0]
|
|
2/2: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6850$1218'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6838$1200'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6825$1196'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6812$1192'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6800$1189'.
|
|
1/1: $1\_zz_3_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
1/3: $0\logic_rspHits_2[0:0]
|
|
2/3: $0\logic_rspHits_1[0:0]
|
|
3/3: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6728$1181'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6716$1160'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6703$1156'.
|
|
1/1: $1\io_outputs_2_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6690$1152'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6677$1148'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6662$1145'.
|
|
1/1: $1\_zz_4_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6587$1133'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_DATA[7:0]$1113
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_ADDR[13:0]$1112
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_DATA[7:0]$1116
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_ADDR[13:0]$1115
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_DATA[7:0]$1119
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_ADDR[13:0]$1118
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_DATA[7:0]$1122
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_ADDR[13:0]$1121
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6555$1105'.
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6519$1088'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_DATA[7:0]$1068
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_ADDR[13:0]$1067
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_DATA[7:0]$1071
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_ADDR[13:0]$1070
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_DATA[7:0]$1074
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_ADDR[13:0]$1073
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_DATA[7:0]$1077
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_ADDR[13:0]$1076
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6487$1060'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6449$1055'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
1/3: $1\_zz_4_[0:0]
|
|
2/3: $1\_zz_3_[31:0]
|
|
3/3: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6376$1053'.
|
|
1/1: $1\io_input_PSLVERROR[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6368$1052'.
|
|
1/1: $1\io_input_PREADY[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6363$1045'.
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6323$1042'.
|
|
1/1: $0\myReg[31:0]
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6307$1029'.
|
|
1/1: $1\io_bus_PRDATA[31:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1026'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6281$1025'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
1/6: $0\bridge_misc_doBreak[0:0]
|
|
2/6: $0\bridge_misc_breakDetected[0:0]
|
|
3/6: $0\bridge_misc_readOverflowError[0:0]
|
|
4/6: $0\bridge_misc_readError[0:0]
|
|
5/6: $0\bridge_interruptCtrl_readIntEnable[0:0]
|
|
6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6201$1019'.
|
|
1/2: $2\_zz_6_[0:0]
|
|
2/2: $1\_zz_6_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6184$1018'.
|
|
1/2: $2\_zz_5_[0:0]
|
|
2/2: $1\_zz_5_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6167$1017'.
|
|
1/2: $2\_zz_4_[0:0]
|
|
2/2: $1\_zz_4_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6150$1016'.
|
|
1/2: $2\_zz_3_[0:0]
|
|
2/2: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6133$1015'.
|
|
1/2: $2\_zz_2_[0:0]
|
|
2/2: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6113$1010'.
|
|
1/2: $2\bridge_read_streamBreaked_ready[0:0]
|
|
2/2: $1\bridge_read_streamBreaked_ready[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6105$1009'.
|
|
1/1: $1\_zz_8_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6098$1008'.
|
|
1/1: $1\bridge_read_streamBreaked_valid[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6078$1007'.
|
|
1/2: $2\_zz_1_[0:0]
|
|
2/2: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6074$1006'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6042$992'.
|
|
1/9: $2\io_apb_PRDATA[20:15] [5:2]
|
|
2/9: $1\io_apb_PRDATA[9:0] [7:2]
|
|
3/9: $2\io_apb_PRDATA[20:15] [1]
|
|
4/9: $1\io_apb_PRDATA[9:0] [8]
|
|
5/9: $2\io_apb_PRDATA[20:15] [0]
|
|
6/9: $1\io_apb_PRDATA[9:0] [1]
|
|
7/9: $3\io_apb_PRDATA[28:24]
|
|
8/9: $1\io_apb_PRDATA[9:0] [9]
|
|
9/9: $1\io_apb_PRDATA[9:0] [0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5868$988'.
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
1/2: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0]
|
|
2/2: $0\state[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5842$984'.
|
|
1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5828$982'.
|
|
1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5773$978'.
|
|
1/2: $0\dispatcher_headerShifter[7:0]
|
|
2/2: $0\dispatcher_dataShifter[66:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
1/3: $0\dispatcher_counter[2:0]
|
|
2/3: $0\dispatcher_headerLoaded[0:0]
|
|
3/3: $0\dispatcher_dataLoaded[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5442$969'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5697$968'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
1/4: $0\jtag_readArea_shifter[33:0]
|
|
2/4: $0\jtag_idcodeArea_shifter[31:0]
|
|
3/4: $0\jtag_tap_instructionShift[3:0]
|
|
4/4: $0\jtag_tap_instruction[3:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
1/3: $0\system_rsp_payload_data[31:0]
|
|
2/3: $0\system_rsp_payload_error[0:0]
|
|
3/3: $0\system_rsp_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5636$957'.
|
|
1/2: $2\jtag_writeArea_source_valid[0:0]
|
|
2/2: $1\jtag_writeArea_source_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5608$954'.
|
|
1/5: $5\jtag_tap_tdoUnbufferd[0:0]
|
|
2/5: $4\jtag_tap_tdoUnbufferd[0:0]
|
|
3/5: $3\jtag_tap_tdoUnbufferd[0:0]
|
|
4/5: $2\jtag_tap_tdoUnbufferd[0:0]
|
|
5/5: $1\jtag_tap_tdoUnbufferd[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5554$937'.
|
|
1/1: $1\_zz_1_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2027$934'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2026$933'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
1/8: $0\DebugPlugin_hardwareBreakpoints_2_valid[0:0]
|
|
2/8: $0\DebugPlugin_hardwareBreakpoints_1_valid[0:0]
|
|
3/8: $0\DebugPlugin_hardwareBreakpoints_0_valid[0:0]
|
|
4/8: $0\DebugPlugin_haltedByBreak[0:0]
|
|
5/8: $0\DebugPlugin_godmode[0:0]
|
|
6/8: $0\DebugPlugin_stepIt[0:0]
|
|
7/8: $0\DebugPlugin_haltIt[0:0]
|
|
8/8: $0\DebugPlugin_resetIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
1/5: $0\DebugPlugin_firstCycle[0:0]
|
|
2/5: $0\DebugPlugin_busReadDataReg[31:0]
|
|
3/5: $0\DebugPlugin_hardwareBreakpoints_2_pc[30:0]
|
|
4/5: $0\DebugPlugin_hardwareBreakpoints_1_pc[30:0]
|
|
5/5: $0\DebugPlugin_hardwareBreakpoints_0_pc[30:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
1/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [32]
|
|
2/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [31:0]
|
|
3/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [64:32]
|
|
4/92: $0\execute_CsrPlugin_csr_2946[0:0]
|
|
5/92: $0\execute_CsrPlugin_csr_2818[0:0]
|
|
6/92: $0\execute_CsrPlugin_csr_2944[0:0]
|
|
7/92: $0\execute_CsrPlugin_csr_2816[0:0]
|
|
8/92: $0\execute_CsrPlugin_csr_834[0:0]
|
|
9/92: $0\execute_CsrPlugin_csr_773[0:0]
|
|
10/92: $0\execute_CsrPlugin_csr_772[0:0]
|
|
11/92: $0\execute_CsrPlugin_csr_836[0:0]
|
|
12/92: $0\execute_CsrPlugin_csr_768[0:0]
|
|
13/92: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
|
|
14/92: $0\decode_to_execute_RS2[31:0]
|
|
15/92: $0\decode_to_execute_BRANCH_CTRL[1:0]
|
|
16/92: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
|
|
17/92: $0\memory_to_writeBack_SRC1[31:0]
|
|
18/92: $0\execute_to_memory_SRC1[31:0]
|
|
19/92: $0\decode_to_execute_SRC1[31:0]
|
|
20/92: $0\decode_to_execute_IS_CSR[0:0]
|
|
21/92: $0\memory_to_writeBack_SRC2[31:0]
|
|
22/92: $0\execute_to_memory_SRC2[31:0]
|
|
23/92: $0\decode_to_execute_SRC2[31:0]
|
|
24/92: $0\execute_to_memory_MUL_LL[31:0]
|
|
25/92: $0\memory_to_writeBack_ENV_CTRL[0:0]
|
|
26/92: $0\execute_to_memory_ENV_CTRL[0:0]
|
|
27/92: $0\decode_to_execute_ENV_CTRL[0:0]
|
|
28/92: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
|
|
29/92: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
|
|
30/92: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
|
|
31/92: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
|
|
32/92: $0\execute_to_memory_MUL_LH[31:0]
|
|
33/92: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
|
|
34/92: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
|
|
35/92: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
|
|
36/92: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
|
|
37/92: $0\memory_to_writeBack_PC[31:0]
|
|
38/92: $0\execute_to_memory_PC[31:0]
|
|
39/92: $0\decode_to_execute_PC[31:0]
|
|
40/92: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
|
|
41/92: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
|
|
42/92: $0\execute_to_memory_BRANCH_DO[0:0]
|
|
43/92: $0\execute_to_memory_SHIFT_CTRL[1:0]
|
|
44/92: $0\decode_to_execute_SHIFT_CTRL[1:0]
|
|
45/92: $0\decode_to_execute_IS_RS2_SIGNED[0:0]
|
|
46/92: $0\memory_to_writeBack_IS_MUL[0:0]
|
|
47/92: $0\execute_to_memory_IS_MUL[0:0]
|
|
48/92: $0\decode_to_execute_IS_MUL[0:0]
|
|
49/92: $0\execute_to_memory_MUL_HL[31:0]
|
|
50/92: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
|
|
51/92: $0\execute_to_memory_MEMORY_ENABLE[0:0]
|
|
52/92: $0\decode_to_execute_MEMORY_ENABLE[0:0]
|
|
53/92: $0\decode_to_execute_ALU_CTRL[1:0]
|
|
54/92: $0\execute_to_memory_INSTRUCTION[31:0]
|
|
55/92: $0\decode_to_execute_INSTRUCTION[31:0]
|
|
56/92: $0\decode_to_execute_DO_EBREAK[0:0]
|
|
57/92: $0\memory_to_writeBack_MEMORY_STORE[0:0]
|
|
58/92: $0\execute_to_memory_MEMORY_STORE[0:0]
|
|
59/92: $0\decode_to_execute_MEMORY_STORE[0:0]
|
|
60/92: $0\memory_to_writeBack_MUL[63:0]
|
|
61/92: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
62/92: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
63/92: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
|
|
64/92: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
|
|
65/92: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
|
|
66/92: $0\decode_to_execute_IS_RS1_SIGNED[0:0]
|
|
67/92: $0\decode_to_execute_RS1[31:0]
|
|
68/92: $0\execute_to_memory_BRANCH_CALC[31:0]
|
|
69/92: $0\execute_to_memory_IS_DIV[0:0]
|
|
70/92: $0\decode_to_execute_IS_DIV[0:0]
|
|
71/92: $0\execute_to_memory_SHIFT_RIGHT[31:0]
|
|
72/92: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
|
|
73/92: $0\execute_to_memory_MUL_HH[31:0]
|
|
74/92: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
|
|
75/92: $0\memory_MulDivIterativePlugin_div_result[31:0]
|
|
76/92: $0\memory_MulDivIterativePlugin_div_done[0:0]
|
|
77/92: $0\memory_MulDivIterativePlugin_div_needRevert[0:0]
|
|
78/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [31:0]
|
|
79/92: $0\memory_MulDivIterativePlugin_rs2[31:0]
|
|
80/92: $0\CsrPlugin_mip_MSIP[0:0]
|
|
81/92: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
82/92: $0\CsrPlugin_interrupt_code[3:0]
|
|
83/92: $0\CsrPlugin_minstret[63:0]
|
|
84/92: $0\CsrPlugin_mcause_exceptionCode[3:0]
|
|
85/92: $0\CsrPlugin_mcause_interrupt[0:0]
|
|
86/92: $0\CsrPlugin_mepc[31:0]
|
|
87/92: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0]
|
|
88/92: $0\_zz_63_[0:0]
|
|
89/92: $0\_zz_62_[31:0]
|
|
90/92: $0\_zz_61_[0:0]
|
|
91/92: $0\_zz_60_[31:0]
|
|
92/92: $0\_zz_58_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
1/38: $0\memory_MulDivIterativePlugin_div_counter_value[5:0]
|
|
2/38: $0\_zz_100_[0:0]
|
|
3/38: $0\_zz_88_[0:0]
|
|
4/38: $0\execute_CsrPlugin_wfiWake[0:0]
|
|
5/38: $0\CsrPlugin_hadException[0:0]
|
|
6/38: $0\CsrPlugin_interrupt_valid[0:0]
|
|
7/38: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0]
|
|
8/38: $0\IBusSimplePlugin_pending_value[2:0]
|
|
9/38: $0\IBusSimplePlugin_fetchPc_booted[0:0]
|
|
10/38: $0\_zz_125_[2:0]
|
|
11/38: $0\memory_to_writeBack_INSTRUCTION[31:0]
|
|
12/38: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
|
|
13/38: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
|
|
14/38: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
|
|
15/38: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
|
|
16/38: $0\CsrPlugin_mie_MSIE[0:0]
|
|
17/38: $0\CsrPlugin_mie_MTIE[0:0]
|
|
18/38: $0\CsrPlugin_mie_MEIE[0:0]
|
|
19/38: $0\CsrPlugin_mstatus_MPP[1:0]
|
|
20/38: $0\CsrPlugin_mstatus_MPIE[0:0]
|
|
21/38: $0\CsrPlugin_mstatus_MIE[0:0]
|
|
22/38: $0\CsrPlugin_mtvec_base[29:0]
|
|
23/38: $0\CsrPlugin_mtvec_mode[1:0]
|
|
24/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0]
|
|
25/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0]
|
|
26/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0]
|
|
27/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0]
|
|
28/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0]
|
|
29/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0]
|
|
30/38: $0\_zz_59_[0:0]
|
|
31/38: $0\_zz_57_[0:0]
|
|
32/38: $0\_zz_55_[0:0]
|
|
33/38: $0\IBusSimplePlugin_fetchPc_inc[0:0]
|
|
34/38: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0]
|
|
35/38: $0\IBusSimplePlugin_fetchPc_pcReg[31:0]
|
|
36/38: $0\writeBack_arbitration_isValid[0:0]
|
|
37/38: $0\memory_arbitration_isValid[0:0]
|
|
38/38: $0\execute_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4706$764'.
|
|
1/1: $1\_zz_134_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4699$763'.
|
|
1/1: $1\_zz_133_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4692$762'.
|
|
1/1: $1\_zz_132_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4685$761'.
|
|
1/1: $1\_zz_131_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4677$760'.
|
|
1/2: $1\_zz_130_[3:0]
|
|
2/2: $2\_zz_130_[31:31]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4669$759'.
|
|
1/2: $1\_zz_129_[31:0] [31:2]
|
|
2/2: $1\_zz_129_[31:0] [1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4660$758'.
|
|
1/3: $1\_zz_128_[3:3]
|
|
2/3: $2\_zz_128_[7:7]
|
|
3/3: $3\_zz_128_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4651$757'.
|
|
1/3: $1\_zz_127_[3:3]
|
|
2/3: $2\_zz_127_[7:7]
|
|
3/3: $3\_zz_127_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4642$756'.
|
|
1/3: $1\_zz_126_[3:3]
|
|
2/3: $2\_zz_126_[7:7]
|
|
3/3: $3\_zz_126_[12:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$755'.
|
|
1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4555$701'.
|
|
1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4544$699'.
|
|
1/5: $1\debug_bus_rsp_data[4:0] [4]
|
|
2/5: $1\debug_bus_rsp_data[4:0] [2]
|
|
3/5: $1\debug_bus_rsp_data[4:0] [1]
|
|
4/5: $1\debug_bus_rsp_data[4:0] [0]
|
|
5/5: $1\debug_bus_rsp_data[4:0] [3]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$698'.
|
|
1/3: $3\debug_bus_cmd_ready[0:0]
|
|
2/3: $2\debug_bus_cmd_ready[0:0]
|
|
3/3: $1\debug_bus_cmd_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4516$696'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4497$686'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4488$683'.
|
|
1/1: $1\memory_MulDivIterativePlugin_div_counter_willClear[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$682'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4462$677'.
|
|
1/1: $1\writeBack_Mul16Plugin_bSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4448$676'.
|
|
1/1: $1\writeBack_Mul16Plugin_aSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4419$671'.
|
|
1/1: $1\_zz_118_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4397$670'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4373$669'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4358$668'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4339$665'.
|
|
1/1: $1\_zz_111_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4327$658'.
|
|
1/3: $3\_zz_110_[0:0]
|
|
2/3: $2\_zz_110_[0:0]
|
|
3/3: $1\_zz_110_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4291$649'.
|
|
1/10: $10\_zz_99_[0:0]
|
|
2/10: $9\_zz_99_[0:0]
|
|
3/10: $8\_zz_99_[0:0]
|
|
4/10: $7\_zz_99_[0:0]
|
|
5/10: $6\_zz_99_[0:0]
|
|
6/10: $5\_zz_99_[0:0]
|
|
7/10: $4\_zz_99_[0:0]
|
|
8/10: $3\_zz_99_[0:0]
|
|
9/10: $2\_zz_99_[0:0]
|
|
10/10: $1\_zz_99_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4263$647'.
|
|
1/10: $10\_zz_98_[0:0]
|
|
2/10: $9\_zz_98_[0:0]
|
|
3/10: $8\_zz_98_[0:0]
|
|
4/10: $7\_zz_98_[0:0]
|
|
5/10: $6\_zz_98_[0:0]
|
|
6/10: $5\_zz_98_[0:0]
|
|
7/10: $4\_zz_98_[0:0]
|
|
8/10: $3\_zz_98_[0:0]
|
|
9/10: $2\_zz_98_[0:0]
|
|
10/10: $1\_zz_98_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4228$646'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4192$643'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4183$639'.
|
|
1/1: $1\execute_SrcPlugin_addSub[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$638'.
|
|
1/1: $1\_zz_95_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4143$637'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4119$636'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4101$635'.
|
|
1/1: $1\_zz_90_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4087$634'.
|
|
1/1: $1\_zz_89_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$630'.
|
|
1/1: $1\execute_IntAluPlugin_bitwise[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4064$628'.
|
|
1/1: $1\lastStageRegFileWrite_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4028$606'.
|
|
1/1: $1\execute_CsrPlugin_writeData[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4014$590'.
|
|
1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
|
|
2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3967$585'.
|
|
1/16: $16\execute_CsrPlugin_illegalAccess[0:0]
|
|
2/16: $15\execute_CsrPlugin_illegalAccess[0:0]
|
|
3/16: $14\execute_CsrPlugin_illegalAccess[0:0]
|
|
4/16: $13\execute_CsrPlugin_illegalAccess[0:0]
|
|
5/16: $12\execute_CsrPlugin_illegalAccess[0:0]
|
|
6/16: $11\execute_CsrPlugin_illegalAccess[0:0]
|
|
7/16: $10\execute_CsrPlugin_illegalAccess[0:0]
|
|
8/16: $9\execute_CsrPlugin_illegalAccess[0:0]
|
|
9/16: $8\execute_CsrPlugin_illegalAccess[0:0]
|
|
10/16: $7\execute_CsrPlugin_illegalAccess[0:0]
|
|
11/16: $6\execute_CsrPlugin_illegalAccess[0:0]
|
|
12/16: $5\execute_CsrPlugin_illegalAccess[0:0]
|
|
13/16: $4\execute_CsrPlugin_illegalAccess[0:0]
|
|
14/16: $3\execute_CsrPlugin_illegalAccess[0:0]
|
|
15/16: $2\execute_CsrPlugin_illegalAccess[0:0]
|
|
16/16: $1\execute_CsrPlugin_illegalAccess[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3954$583'.
|
|
1/1: $1\CsrPlugin_xtvec_base[29:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3943$582'.
|
|
1/1: $1\CsrPlugin_xtvec_mode[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3933$579'.
|
|
1/1: $1\CsrPlugin_pipelineLiberator_done[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3918$573'.
|
|
1/1: $1\CsrPlugin_privilege[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3904$572'.
|
|
1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3884$571'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3855$568'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3837$565'.
|
|
1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
|
|
2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3821$563'.
|
|
1/1: $1\_zz_67_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3806$562'.
|
|
1/1: $1\_zz_66_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$552'.
|
|
1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3772$543'.
|
|
1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$531'.
|
|
1/1: $1\decode_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3716$525'.
|
|
1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3690$507'.
|
|
1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3672$501'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3663$499'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3656$498'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3648$496'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$492'.
|
|
1/1: $1\CsrPlugin_allowException[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3630$490'.
|
|
1/1: $1\CsrPlugin_allowInterrupts[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3623$489'.
|
|
1/1: $1\CsrPlugin_forceMachineWire[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3607$488'.
|
|
1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
|
|
2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
|
|
3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3597$487'.
|
|
1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
|
|
2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$486'.
|
|
1/1: $1\CsrPlugin_thirdPartyWake[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3579$484'.
|
|
1/2: $2\IBusSimplePlugin_incomingInstruction[0:0]
|
|
2/2: $1\IBusSimplePlugin_incomingInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3558$483'.
|
|
1/6: $6\IBusSimplePlugin_fetcherHalt[0:0]
|
|
2/6: $5\IBusSimplePlugin_fetcherHalt[0:0]
|
|
3/6: $4\IBusSimplePlugin_fetcherHalt[0:0]
|
|
4/6: $3\IBusSimplePlugin_fetcherHalt[0:0]
|
|
5/6: $2\IBusSimplePlugin_fetcherHalt[0:0]
|
|
6/6: $1\IBusSimplePlugin_fetcherHalt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3544$482'.
|
|
1/2: $2\writeBack_arbitration_flushNext[0:0]
|
|
2/2: $1\writeBack_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3536$481'.
|
|
1/1: $1\writeBack_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3527$480'.
|
|
1/1: $1\memory_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3519$479'.
|
|
1/1: $1\memory_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3506$469'.
|
|
1/3: $3\memory_arbitration_haltItself[0:0]
|
|
2/3: $2\memory_arbitration_haltItself[0:0]
|
|
3/3: $1\memory_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3497$468'.
|
|
1/2: $2\execute_arbitration_flushNext[0:0]
|
|
2/2: $1\execute_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3488$467'.
|
|
1/2: $2\execute_arbitration_flushIt[0:0]
|
|
2/2: $1\execute_arbitration_flushIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3481$466'.
|
|
1/1: $1\execute_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3474$465'.
|
|
1/1: $1\execute_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$457'.
|
|
1/3: $3\execute_arbitration_haltItself[0:0]
|
|
2/3: $2\execute_arbitration_haltItself[0:0]
|
|
3/3: $1\execute_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3453$456'.
|
|
1/1: $1\decode_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3440$446'.
|
|
1/3: $3\decode_arbitration_haltByOther[0:0]
|
|
2/3: $2\decode_arbitration_haltByOther[0:0]
|
|
3/3: $1\decode_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3421$445'.
|
|
1/1: $1\decode_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3410$444'.
|
|
1/1: $1\_zz_48_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3382$441'.
|
|
1/3: $3\_zz_47_[31:0]
|
|
2/3: $2\_zz_47_[31:0]
|
|
3/3: $1\_zz_47_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3367$440'.
|
|
1/1: $1\_zz_43_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3360$438'.
|
|
1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3352$436'.
|
|
1/1: $1\_zz_35_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3314$435'.
|
|
1/3: $3\_zz_23_[31:0]
|
|
2/3: $2\_zz_23_[31:0]
|
|
3/3: $1\_zz_23_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3283$433'.
|
|
1/11: $11\decode_RS1[31:0]
|
|
2/11: $10\decode_RS1[31:0]
|
|
3/11: $9\decode_RS1[31:0]
|
|
4/11: $8\decode_RS1[31:0]
|
|
5/11: $7\decode_RS1[31:0]
|
|
6/11: $6\decode_RS1[31:0]
|
|
7/11: $5\decode_RS1[31:0]
|
|
8/11: $4\decode_RS1[31:0]
|
|
9/11: $3\decode_RS1[31:0]
|
|
10/11: $2\decode_RS1[31:0]
|
|
11/11: $1\decode_RS1[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3253$431'.
|
|
1/11: $11\decode_RS2[31:0]
|
|
2/11: $10\decode_RS2[31:0]
|
|
3/11: $9\decode_RS2[31:0]
|
|
4/11: $8\decode_RS2[31:0]
|
|
5/11: $7\decode_RS2[31:0]
|
|
6/11: $6\decode_RS2[31:0]
|
|
7/11: $5\decode_RS2[31:0]
|
|
8/11: $4\decode_RS2[31:0]
|
|
9/11: $3\decode_RS2[31:0]
|
|
10/11: $2\decode_RS2[31:0]
|
|
11/11: $1\decode_RS2[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
1/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402
|
|
2/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_DATA[31:0]$401
|
|
3/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_ADDR[4:0]$400
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2588$397'.
|
|
1/1: $0\_zz_138_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2582$395'.
|
|
1/1: $0\_zz_137_[31:0]
|
|
Creating decoders for process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1365$217'.
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
1/3: $0\popPtr_value[2:0]
|
|
2/3: $0\pushPtr_value[2:0]
|
|
3/3: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
1/1: $1\io_occupancy[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
1/2: $2\popPtr_valueNext[2:0]
|
|
2/2: $1\popPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
1/2: $2\pushPtr_valueNext[2:0]
|
|
2/2: $1\pushPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
1/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
2/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_DATA[1:0]$186
|
|
3/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_ADDR[2:0]$185
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
1/4: $0\_zz_2_[0:0]
|
|
2/4: $0\logic_popPtr_value[3:0]
|
|
3/4: $0\logic_pushPtr_value[3:0]
|
|
4/4: $0\logic_risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
1/1: $1\logic_popPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
1/1: $1\logic_popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
1/1: $1\logic_popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
1/1: $1\logic_pushPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
1/1: $1\logic_pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
1/1: $1\logic_pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
1/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
2/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA[7:0]$119
|
|
3/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR[3:0]$118
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
1/1: $0\_zz_3_[7:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
1/1: $0\clockDivider_counter[19:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
1/1: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
1/1: $1\io_write_thrown_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
1/1: $0\outputArea_flow_regNext_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
1/3: $0\inputArea_data_fragment[0:0]
|
|
2/3: $0\inputArea_data_last[0:0]
|
|
3/3: $0\inputArea_target[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
1/1: $0\_zz_3_[32:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
1/1: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
1/1: $1\io_pop_payload_inst[31:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
1/1: $1\io_pop_payload_error[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
1/1: $1\io_pop_valid[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
1/9: $2$lookahead\stateMachine_shifter$60[7:0]$74
|
|
2/9: $2$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$73
|
|
3/9: $2$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$72
|
|
4/9: $1$lookahead\stateMachine_shifter$60[7:0]$70
|
|
5/9: $1$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$69
|
|
6/9: $1$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$68
|
|
7/9: $0\bitCounter_value[2:0]
|
|
8/9: $0\bitTimer_counter[2:0]
|
|
9/9: $0\stateMachine_parity[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
1/8: $0\stateMachine_validReg[0:0]
|
|
2/8: $0\sampler_tick[0:0]
|
|
3/8: $0\sampler_value[0:0]
|
|
4/8: $0\_zz_1_[0:0]
|
|
5/8: $0\break_counter[6:0]
|
|
6/8: $0\sampler_samples_2[0:0]
|
|
7/8: $0\sampler_samples_1[0:0]
|
|
8/8: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
1/2: $2\bitTimer_tick[0:0]
|
|
2/2: $1\bitTimer_tick[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
1/5: $5\io_error[0:0]
|
|
2/5: $4\io_error[0:0]
|
|
3/5: $3\io_error[0:0]
|
|
4/5: $2\io_error[0:0]
|
|
5/5: $1\io_error[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
1/2: $0\stateMachine_parity[0:0]
|
|
2/2: $0\tickCounter_value[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
1/3: $0\_zz_1_[0:0]
|
|
2/3: $0\clockDivider_counter_value[2:0]
|
|
3/3: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
1/3: $3\io_write_ready[0:0]
|
|
2/3: $2\io_write_ready[0:0]
|
|
3/3: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
1/1: $1\stateMachine_txd[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
1/2: $2\clockDivider_counter_valueNext[2:0]
|
|
2/2: $1\clockDivider_counter_valueNext[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
1/1: $1\clockDivider_counter_willIncrement[0:0]
|
|
Creating decoders for process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
Creating decoders for process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
1/2: $0\buffers_1[0:0]
|
|
2/2: $0\buffers_0[0:0]
|
|
|
|
2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `\PQVexRiscvUlx3s.\_zz_22_' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7613$1235'.
|
|
No latch inferred for signal `\PQVexRiscvUlx3s.\core_externalInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7591$1230'.
|
|
No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7033$1223'.
|
|
No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7026$1222'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6838$1200'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6825$1196'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6812$1192'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\_zz_3_' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6800$1189'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6716$1160'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_2_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6703$1156'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6690$1152'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6677$1148'.
|
|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\_zz_4_' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6662$1145'.
|
|
No latch inferred for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6555$1105'.
|
|
No latch inferred for signal `\PipelinedMemoryBusRamUlx3s.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6487$1060'.
|
|
No latch inferred for signal `\Apb3Router.\_zz_2_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
No latch inferred for signal `\Apb3Router.\_zz_3_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
No latch inferred for signal `\Apb3Router.\_zz_4_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6376$1053'.
|
|
No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6368$1052'.
|
|
No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6363$1045'.
|
|
No latch inferred for signal `\MyMem.\io_bus_PRDATA' from process `\MyMem.$proc$PQVexRiscvUlx3s.v:6307$1029'.
|
|
No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6073$989$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1026'.
|
|
No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6073$990$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1026'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_6_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6201$1019'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_5_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6184$1018'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_4_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6167$1017'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_3_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6150$1016'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_2_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6133$1015'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6113$1010'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_8_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6105$1009'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6098$1008'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\_zz_1_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6078$1007'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6074$1006'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6042$992'.
|
|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5842$984'.
|
|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5828$982'.
|
|
No latch inferred for signal `\JtagBridge.\jtag_writeArea_source_valid' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5636$957'.
|
|
No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5608$954'.
|
|
No latch inferred for signal `\JtagBridge.\_zz_1_' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5554$937'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_134_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4706$764'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4699$763'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_132_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4692$762'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4685$761'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4677$760'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_129_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4669$759'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4660$758'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_127_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4651$757'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4642$756'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$755'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4555$701'.
|
|
No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4544$699'.
|
|
No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$698'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4516$696'.
|
|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_valueNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4497$686'.
|
|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willClear' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4488$683'.
|
|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$682'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_bSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4462$677'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_aSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4448$676'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_118_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4419$671'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_117_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4397$670'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_115_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4373$669'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_113_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4358$668'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4339$665'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4327$658'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_99_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4291$649'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_98_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4263$647'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_97_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4228$646'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_96_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4192$643'.
|
|
No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4183$639'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_95_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$638'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_94_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4143$637'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_92_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4119$636'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_90_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4101$635'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_89_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4087$634'.
|
|
No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$630'.
|
|
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4064$628'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4028$606'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4014$590'.
|
|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3967$585'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3954$583'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3943$582'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3933$579'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3918$573'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3904$572'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_71_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3884$571'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_69_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3855$568'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3837$565'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_67_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3821$563'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_66_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3806$562'.
|
|
No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$552'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3772$543'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$531'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3716$525'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3690$507'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3672$501'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3663$499'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3656$498'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3648$496'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$492'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3630$490'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3623$489'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3607$488'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3597$487'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$486'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3579$484'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3558$483'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3544$482'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3536$481'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3527$480'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3519$479'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3506$469'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3497$468'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3488$467'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3481$466'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3474$465'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$457'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3453$456'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3440$446'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3421$445'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_48_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3410$444'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_47_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3382$441'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_43_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3367$440'.
|
|
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3360$438'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_35_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3352$436'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_23_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3314$435'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3283$433'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3253$431'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\io_occupancy' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\_zz_1_' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
No latch inferred for signal `\StreamFork.\io_input_ready' from process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
No latch inferred for signal `\StreamFifo.\_zz_1_' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\_zz_1_' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
|
|
2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1483'.
|
|
created $dff cell `$procdff$3632' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1480'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
created $dff cell `$procdff$3633' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
created $dff cell `$procdff$3634' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1458_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
created $dff cell `$procdff$3635' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1425'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
created $dff cell `$procdff$3636' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
created $dff cell `$procdff$3637' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1401_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
created $dff cell `$procdff$3638' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1402'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_35_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7722$1255'.
|
|
created $adff cell `$procdff$3639' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\core_cpu_debug_resetOut_regNext' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7718$1254'.
|
|
created $dff cell `$procdff$3640' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_6_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3641' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_7_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3642' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_8_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3643' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_9_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3644' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_12_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3645' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_13_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3646' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_14_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3647' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_15_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3648' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_25_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3649' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_26_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3650' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_27_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3651' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_28_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3652' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_31_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3653' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_32_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3654' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_33_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3655' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_34_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
created $dff cell `$procdff$3656' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_5_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
created $adff cell `$procdff$3657' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_11_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
created $adff cell `$procdff$3658' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_24_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
created $adff cell `$procdff$3659' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_30_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
created $adff cell `$procdff$3660' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_systemClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7655$1241'.
|
|
created $dff cell `$procdff$3661' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_mainClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7655$1241'.
|
|
created $dff cell `$procdff$3662' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6858$1220'.
|
|
created $dff cell `$procdff$3663' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6858$1220'.
|
|
created $dff cell `$procdff$3664' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6850$1218'.
|
|
created $adff cell `$procdff$3665' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
created $dff cell `$procdff$3666' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
created $dff cell `$procdff$3667' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_2' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
created $dff cell `$procdff$3668' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6728$1181'.
|
|
created $adff cell `$procdff$3669' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6587$1133'.
|
|
created $adff cell `$procdff$3670' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3671' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3672' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3673' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3674' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3675' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3676' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3677' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3678' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3679' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3680' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3681' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
created $dff cell `$procdff$3682' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
created $dff cell `$procdff$3683' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
created $dff cell `$procdff$3684' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
created $dff cell `$procdff$3685' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
created $dff cell `$procdff$3686' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6519$1088'.
|
|
created $adff cell `$procdff$3687' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3688' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3689' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3690' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3691' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3692' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3693' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3694' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3695' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3696' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3697' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3698' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
created $dff cell `$procdff$3699' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
created $dff cell `$procdff$3700' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
created $dff cell `$procdff$3701' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
created $dff cell `$procdff$3702' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
created $dff cell `$procdff$3703' with positive edge clock.
|
|
Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6449$1055'.
|
|
created $dff cell `$procdff$3704' with positive edge clock.
|
|
Creating register for signal `\MyMem.\myReg' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6323$1042'.
|
|
created $dff cell `$procdff$3705' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\uartCtrl_1__io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6281$1025'.
|
|
created $dff cell `$procdff$3706' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3707' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3708' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3709' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3710' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3711' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
created $adff cell `$procdff$3712' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5868$988'.
|
|
created $dff cell `$procdff$3713' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
created $adff cell `$procdff$3714' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
created $adff cell `$procdff$3715' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5773$978'.
|
|
created $dff cell `$procdff$3716' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5773$978'.
|
|
created $dff cell `$procdff$3717' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
created $adff cell `$procdff$3718' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
created $adff cell `$procdff$3719' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
created $adff cell `$procdff$3720' with positive edge clock and positive level reset.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5697$968'.
|
|
created $dff cell `$procdff$3721' with negative edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3722' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3723' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3724' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3725' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3726' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_readArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
created $dff cell `$procdff$3727' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
created $dff cell `$procdff$3728' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
created $dff cell `$procdff$3729' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
created $dff cell `$procdff$3730' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3731' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3732' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3733' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3734' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3735' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3736' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3737' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
created $adff cell `$procdff$3738' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3739' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3740' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3741' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3742' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3743' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3744' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3745' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_124_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3746' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
created $dff cell `$procdff$3747' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_58_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3748' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_60_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3749' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_61_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3750' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_62_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3751' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_63_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3752' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3753' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3754' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3755' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3756' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3757' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3758' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3759' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3760' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3761' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3762' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3763' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3764' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_102_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3765' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3766' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3767' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_accumulator' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3768' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_needRevert' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3769' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_done' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3770' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_result' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3771' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3772' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3773' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3774' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3775' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3776' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3777' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3778' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3779' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3780' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3781' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3782' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3783' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3784' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3785' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3786' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3787' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3788' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3789' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3790' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3791' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3792' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3793' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3794' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3795' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3796' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3797' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3798' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3799' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3800' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3801' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3802' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3803' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3804' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3805' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3806' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3807' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3808' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3809' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3810' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3811' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3812' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3813' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3814' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3815' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3816' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3817' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3818' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3819' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3820' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3821' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3822' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3823' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3824' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3825' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3826' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3827' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3828' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3829' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3830' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3831' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3832' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3833' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3834' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3835' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3836' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3837' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3838' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2816' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3839' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2944' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3840' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2818' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3841' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2946' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
created $dff cell `$procdff$3842' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3843' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3844' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3845' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3846' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3847' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3848' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3849' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_55_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3850' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_57_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3851' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_59_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3852' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3853' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3854' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3855' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3856' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3857' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3858' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3859' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3860' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3861' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3862' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3863' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3864' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3865' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3866' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3867' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3868' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3869' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3870' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3871' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3872' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3873' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3874' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_88_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3875' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_100_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3876' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3877' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3878' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3879' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_125_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
created $adff cell `$procdff$3880' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_ADDR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
created $dff cell `$procdff$3881' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
created $dff cell `$procdff$3882' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
created $dff cell `$procdff$3883' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_138_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2588$397'.
|
|
created $dff cell `$procdff$3884' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_137_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2582$395'.
|
|
created $dff cell `$procdff$3885' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_0' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1365$217'.
|
|
created $dff cell `$procdff$3886' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_1' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1365$217'.
|
|
created $dff cell `$procdff$3887' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\risingOccupancy' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$3888' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\pushPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$3889' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\popPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$3890' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_ADDR' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$3891' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_DATA' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$3892' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$3893' with positive edge clock.
|
|
Creating register for signal `\StreamFork.\_zz_2_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
created $adff cell `$procdff$3894' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork.\_zz_1_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
created $adff cell `$procdff$3895' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_0' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
created $dff cell `$procdff$3896' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_1' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
created $dff cell `$procdff$3897' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\locked' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
created $adff cell `$procdff$3898' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\_zz_2_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$3899' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$3900' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$3901' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$3902' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$3903' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$3904' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$3905' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.\_zz_3_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
created $dff cell `$procdff$3906' with positive edge clock.
|
|
Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
created $adff cell `$procdff$3907' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_valid' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
created $adff cell `$procdff$3908' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$3909' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$3910' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$3911' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$3912' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$3913' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$3914' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\_zz_3_' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
created $dff cell `$procdff$3915' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
created $adff cell `$procdff$3916' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3917' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3918' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3919' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3920' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3921' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$data$PQVexRiscvUlx3s.v:580$28' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3922' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$60' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$3923' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3924' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\_zz_1_' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3925' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3926' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3927' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3928' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3929' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3930' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$3931' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$3932' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$3933' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$3934' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$3935' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\_zz_1_' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$3936' with positive edge clock and positive level reset.
|
|
Creating register for signal `\BufferCC_1_.\buffers_0' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$3937' with positive edge clock.
|
|
Creating register for signal `\BufferCC_1_.\buffers_1' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$3938' with positive edge clock.
|
|
Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$3939' with positive edge clock and positive level non-const reset.
|
|
Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$3946' with positive edge clock and positive level non-const reset.
|
|
|
|
2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1487'.
|
|
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1483'.
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1483'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1480'.
|
|
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1459'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1425'.
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1403'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1402'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7722$1255'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7718$1254'.
|
|
Found and cleaned up 4 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7691$1245'.
|
|
Found and cleaned up 6 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7663$1242'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7655$1241'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7655$1241'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7613$1235'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7613$1235'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7591$1230'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7591$1230'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7033$1223'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7033$1223'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7026$1222'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7026$1222'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6858$1220'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6858$1220'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6850$1218'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6838$1200'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6838$1200'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6825$1196'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6825$1196'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6812$1192'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6812$1192'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6800$1189'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:6800$1189'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6736$1183'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6728$1181'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6716$1160'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6716$1160'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6703$1156'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6703$1156'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6690$1152'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6690$1152'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6677$1148'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6677$1148'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6662$1145'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6662$1145'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6587$1133'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6567$1111'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6558$1106'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6555$1105'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6519$1088'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6499$1066'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6490$1061'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6487$1060'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6449$1055'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6420$1054'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6376$1053'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6376$1053'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6368$1052'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6368$1052'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6363$1045'.
|
|
Found and cleaned up 2 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:6323$1042'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6323$1042'.
|
|
Found and cleaned up 1 empty switch in `\MyMem.$proc$PQVexRiscvUlx3s.v:6307$1029'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6307$1029'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1026'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6281$1025'.
|
|
Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6221$1020'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6201$1019'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6201$1019'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6184$1018'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6184$1018'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6167$1017'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6167$1017'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6150$1016'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6150$1016'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6133$1015'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6133$1015'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6113$1010'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6113$1010'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6105$1009'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6105$1009'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6098$1008'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6098$1008'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6078$1007'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6078$1007'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6074$1006'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6042$992'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6042$992'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5868$988'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5852$987'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5842$984'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5842$984'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5828$982'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5828$982'.
|
|
Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5773$978'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5773$978'.
|
|
Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5747$974'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5442$969'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5697$968'.
|
|
Found and cleaned up 7 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5662$962'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5651$960'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5636$957'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5636$957'.
|
|
Found and cleaned up 5 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5608$954'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5608$954'.
|
|
Found and cleaned up 1 empty switch in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5554$937'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5554$937'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2027$934'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2026$933'.
|
|
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5330$929'.
|
|
Found and cleaned up 8 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5288$926'.
|
|
Found and cleaned up 90 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4977$823'.
|
|
Found and cleaned up 61 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4715$773'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4706$764'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4706$764'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4699$763'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4699$763'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4692$762'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4692$762'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4685$761'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4685$761'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4677$760'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4677$760'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4669$759'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4669$759'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4660$758'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4660$758'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4651$757'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4651$757'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4642$756'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4642$756'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$755'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$755'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4555$701'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4555$701'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4544$699'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4544$699'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$698'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$698'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4516$696'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4497$686'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4497$686'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4488$683'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4488$683'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$682'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$682'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4462$677'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4462$677'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4448$676'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4448$676'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4419$671'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4419$671'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4397$670'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4373$669'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4358$668'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4339$665'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4339$665'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4327$658'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4327$658'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4291$649'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4291$649'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4263$647'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4263$647'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4228$646'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4192$643'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4183$639'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4183$639'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$638'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$638'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4143$637'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4119$636'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4101$635'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4101$635'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4087$634'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4087$634'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$630'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$630'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4064$628'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4064$628'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4028$606'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4028$606'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4014$590'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4014$590'.
|
|
Found and cleaned up 16 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3967$585'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3967$585'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3954$583'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3954$583'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3943$582'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3943$582'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3933$579'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3933$579'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3918$573'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3918$573'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3904$572'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3904$572'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3884$571'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3855$568'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3837$565'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3837$565'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3821$563'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3821$563'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3806$562'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3806$562'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$552'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$552'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3772$543'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3772$543'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$531'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$531'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3716$525'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3716$525'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3690$507'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3690$507'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3672$501'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3672$501'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3663$499'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3663$499'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3656$498'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3656$498'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3648$496'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3648$496'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$492'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$492'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3630$490'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3630$490'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3623$489'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3623$489'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3607$488'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3607$488'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3597$487'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3597$487'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$486'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$486'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3579$484'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3579$484'.
|
|
Found and cleaned up 6 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3558$483'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3558$483'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3544$482'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3544$482'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3536$481'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3536$481'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3527$480'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3527$480'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3519$479'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3519$479'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3506$469'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3506$469'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3497$468'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3497$468'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3488$467'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3488$467'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3481$466'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3481$466'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3474$465'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3474$465'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$457'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$457'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3453$456'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3453$456'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3440$446'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3440$446'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3421$445'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3421$445'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3410$444'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3410$444'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3382$441'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3382$441'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3367$440'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3367$440'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3360$438'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3360$438'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3352$436'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3352$436'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3314$435'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3314$435'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3283$433'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3283$433'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3253$431'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3253$431'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2594$399'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2588$397'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2588$397'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2582$395'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2582$395'.
|
|
Removing empty process `BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1365$217'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
Removing empty process `BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Cleaned up 553 empty switches.
|
|
|
|
2.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module PipelinedMemoryBusArbiter_1_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter.
|
|
Deleting now unused module PipelinedMemoryBusDecoder_1_.
|
|
Deleting now unused module PipelinedMemoryBusDecoder.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s_1_.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s.
|
|
Deleting now unused module Apb3Router.
|
|
Deleting now unused module Apb3Decoder.
|
|
Deleting now unused module MyMem.
|
|
Deleting now unused module Apb3UartCtrl.
|
|
Deleting now unused module PipelinedMemoryBusToApbBridge.
|
|
Deleting now unused module SystemDebugger.
|
|
Deleting now unused module JtagBridge.
|
|
Deleting now unused module VexRiscv.
|
|
Deleting now unused module BufferCC_2_.
|
|
Deleting now unused module StreamFifoLowLatency_1_.
|
|
Deleting now unused module StreamFork.
|
|
Deleting now unused module StreamArbiter.
|
|
Deleting now unused module StreamFifo.
|
|
Deleting now unused module UartCtrl.
|
|
Deleting now unused module FlowCCByToggle.
|
|
Deleting now unused module StreamFifoLowLatency.
|
|
Deleting now unused module UartCtrlRx.
|
|
Deleting now unused module UartCtrlTx.
|
|
Deleting now unused module BufferCC_1_.
|
|
Deleting now unused module BufferCC.
|
|
<suppressed ~28 debug messages>
|
|
|
|
2.6. Executing TRIBUF pass.
|
|
|
|
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
2.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~452 debug messages>
|
|
|
|
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 293 unused cells and 2597 unused wires.
|
|
<suppressed ~380 debug messages>
|
|
|
|
2.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~435 debug messages>
|
|
Removed a total of 145 cells.
|
|
|
|
2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $flatten\systemDebugger_1_.$procmux$1880: \systemDebugger_1_.dispatcher_headerLoaded -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\systemDebugger_1_.$procmux$1878: \systemDebugger_1_.dispatcher_headerLoaded -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3380.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1726.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3505.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3514.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3517.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3517.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3517.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3517.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3526.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3526.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3526.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3526.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1735.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3536.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3538.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3544.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1744.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1753.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3603.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3605.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3612.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1762.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1773.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1792.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2541.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2543.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2552.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2580.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2582.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2591.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2609.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2635.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2638.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2644.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2657.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2659.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2665.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2675.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2677.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2683.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2701.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2714.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2716.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2722.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2732.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2734.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2740.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2758.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2939.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2972.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3002.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3014.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3023.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3038.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3070.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3095.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3105.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3107.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3113.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3123.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3125.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3131.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3143.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3149.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3158.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3168.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3170.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3176.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3186.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3188.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3194.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3206.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3212.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3221.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$1926.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$1935.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$1944.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$1848.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$1857.
|
|
Removed 79 multiplexer ports.
|
|
<suppressed ~408 debug messages>
|
|
|
|
2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3547: { $auto$opt_reduce.cc:134:opt_mux$3954 $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3414_CMP }
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3323:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2619: $auto$opt_reduce.cc:134:opt_mux$3956
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2627: { $flatten\core_cpu.$procmux$2630_CMP $auto$opt_reduce.cc:134:opt_mux$3958 }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2704: { }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2761: { }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2902: $auto$opt_reduce.cc:134:opt_mux$3960
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3226:
|
|
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402
|
|
New ports: A=1'0, B=1'1, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0]
|
|
New connections: $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [31:1] = { $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN[31:0]$402 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3323:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1634:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN[7:0]$1069 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1640:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN[7:0]$1072 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1646:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN[7:0]$1075 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1652:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN[7:0]$1078 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3270:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
New connections: $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [1] = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1602:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN[7:0]$1114 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1608:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN[7:0]$1117 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1614:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN[7:0]$1120 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1620:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN[7:0]$1123 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3270:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
New connections: $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [1] = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 19 changes.
|
|
|
|
2.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~81 debug messages>
|
|
Removed a total of 27 cells.
|
|
|
|
2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$3873 ($adff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$3756 ($dff) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$3946 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$3939 ($dffsr) from module PQVexRiscvUlx3s.
|
|
|
|
2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 267 unused wires.
|
|
<suppressed ~40 debug messages>
|
|
|
|
2.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~8 debug messages>
|
|
|
|
2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~392 debug messages>
|
|
|
|
2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3413: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3381_CMP $auto$opt_reduce.cc:134:opt_mux$3962 }
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3564: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3570_CMP $auto$opt_reduce.cc:134:opt_mux$3964 }
|
|
New ctrl vector for $pmux cell $flatten\jtagBridge_1_.$procmux$1954: { $flatten\jtagBridge_1_.$procmux$1968_CMP $auto$opt_reduce.cc:134:opt_mux$3970 $flatten\jtagBridge_1_.$procmux$1965_CMP $flatten\jtagBridge_1_.$procmux$1964_CMP $flatten\jtagBridge_1_.$procmux$1963_CMP $flatten\jtagBridge_1_.$procmux$1961_CMP $auto$opt_reduce.cc:134:opt_mux$3968 $flatten\jtagBridge_1_.$procmux$1958_CMP $flatten\jtagBridge_1_.$procmux$1957_CMP $flatten\jtagBridge_1_.$procmux$1956_CMP $auto$opt_reduce.cc:134:opt_mux$3966 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 3 changes.
|
|
|
|
2.11.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 4 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.11.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~392 debug messages>
|
|
|
|
2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.11.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.11.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2596$218_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_8_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_9_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state.
|
|
Not marking PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_code as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_targetPrivilege.
|
|
Not marking PQVexRiscvUlx3s.core_cpu._zz_125_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.jtagBridge_1_.jtag_tap_fsm_state as FSM state register:
|
|
Register has an initialization value.
|
|
|
|
2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$3924
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3414_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3381_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3423_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3435_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
found state code: 3'010
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
found state code: 3'001
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3435_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3423_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3414_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3381_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3381_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3414_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3423_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3435_CMP }
|
|
transition: 3'000 6'-0---- -> 3'000 7'0000001
|
|
transition: 3'000 6'-1---- -> 3'001 7'0010001
|
|
transition: 3'100 6'----0- -> 3'100 7'1000000
|
|
transition: 3'100 6'---01- -> 3'000 7'0000000
|
|
transition: 3'100 6'---110 -> 3'100 7'1000000
|
|
transition: 3'100 6'---111 -> 3'000 7'0000000
|
|
transition: 3'010 6'----0- -> 3'010 7'0101000
|
|
transition: 3'010 6'--0-1- -> 3'010 7'0101000
|
|
transition: 3'010 6'--1-1- -> 3'100 7'1001000
|
|
transition: 3'001 6'----0- -> 3'001 7'0010010
|
|
transition: 3'001 6'---01- -> 3'010 7'0100010
|
|
transition: 3'001 6'---11- -> 3'000 7'0000010
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procdff$3935
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3565_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3570_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3559_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3596_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
found state code: 3'001
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
found state code: 3'010
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3596_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3570_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3565_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3559_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3559_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3565_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3570_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3596_CMP }
|
|
transition: 3'000 5'---0- -> 3'000 7'0000001
|
|
transition: 3'000 5'---1- -> 3'001 7'0010001
|
|
transition: 3'100 5'--0-- -> 3'100 7'1000000
|
|
transition: 3'100 5'--1-0 -> 3'100 7'1000000
|
|
transition: 3'100 5'0-1-1 -> 3'000 7'0000000
|
|
transition: 3'100 5'1-1-1 -> 3'001 7'0010000
|
|
transition: 3'010 5'--0-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-01-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-11-- -> 3'100 7'1000010
|
|
transition: 3'001 5'--0-- -> 3'001 7'0011000
|
|
transition: 3'001 5'--1-- -> 3'010 7'0101000
|
|
Extracting FSM `\core_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\PQVexRiscvUlx3s'.
|
|
found $dff cell for state register: $flatten\core_cpu.$procdff$3763
|
|
root of input selection tree: $flatten\core_cpu.$0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
found ctrl input: \core_cpu.CsrPlugin_mstatus_MIE
|
|
found ctrl input: \core_cpu._zz_164_
|
|
found ctrl input: \core_cpu._zz_163_
|
|
found state code: 2'11
|
|
fsm extraction failed: at least two states are required.
|
|
|
|
2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977' from module `\PQVexRiscvUlx3s'.
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused input signal \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_.
|
|
|
|
2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 30 unused cells and 30 unused wires.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [2].
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3596_CMP.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [2].
|
|
|
|
2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
|
|
2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971 (\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
1: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3435_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3423_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3414_CMP
|
|
3: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3381_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'0---- -> 0 4'0001
|
|
1: 0 5'1---- -> 3 4'0001
|
|
2: 1 5'--111 -> 0 4'0000
|
|
3: 1 5'--01- -> 0 4'0000
|
|
4: 1 5'--110 -> 1 4'0000
|
|
5: 1 5'---0- -> 1 4'0000
|
|
6: 2 5'-1-1- -> 1 4'1000
|
|
7: 2 5'---0- -> 2 4'1000
|
|
8: 2 5'-0-1- -> 2 4'1000
|
|
9: 3 5'--11- -> 0 4'0010
|
|
10: 3 5'--01- -> 2 4'0010
|
|
11: 3 5'---0- -> 3 4'0010
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977 (\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 3
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3570_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3565_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3559_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'---0- -> 0 3'000
|
|
1: 0 5'---1- -> 3 3'000
|
|
2: 1 5'0-1-1 -> 0 3'000
|
|
3: 1 5'--1-0 -> 1 3'000
|
|
4: 1 5'--0-- -> 1 3'000
|
|
5: 1 5'1-1-1 -> 3 3'000
|
|
6: 2 5'-11-- -> 1 3'001
|
|
7: 2 5'--0-- -> 2 3'001
|
|
8: 2 5'-01-- -> 2 3'001
|
|
9: 3 5'--1-- -> 2 3'100
|
|
10: 3 5'--0-- -> 3 3'100
|
|
|
|
-------------------------------------
|
|
|
|
2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$3971' from module `\PQVexRiscvUlx3s'.
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$3977' from module `\PQVexRiscvUlx3s'.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~13 debug messages>
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3447.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3447.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3449.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3449.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3451.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3534.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3534.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3542.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3542.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3547.
|
|
dead port 1/4 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3619.
|
|
Removed 11 multiplexer ports.
|
|
<suppressed ~390 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$3661 ($dff) from module PQVexRiscvUlx3s (D = \asyncReset_buffercc.buffers_1, Q = \resetCtrl_systemClockReset, rval = 1'1).
|
|
Adding EN signal on $procdff$3660 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:7686$1244_Y, Q = \_zz_30_).
|
|
Adding EN signal on $procdff$3659 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_24_[0:0], Q = \_zz_24_).
|
|
Adding EN signal on $procdff$3658 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:7677$1243_Y, Q = \_zz_11_).
|
|
Adding EN signal on $procdff$3657 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_5_[0:0], Q = \_zz_5_).
|
|
Adding EN signal on $procdff$3656 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7714$1253_Y, Q = \_zz_34_).
|
|
Adding EN signal on $procdff$3655 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7713$1252_Y, Q = \_zz_33_).
|
|
Adding EN signal on $procdff$3654 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7712$1251_Y, Q = \_zz_32_).
|
|
Adding EN signal on $procdff$3653 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7711$1250_Y, Q = \_zz_31_).
|
|
Adding EN signal on $procdff$3652 ($dff) from module PQVexRiscvUlx3s (D = \_zz_21_, Q = \_zz_28_).
|
|
Adding EN signal on $procdff$3651 ($dff) from module PQVexRiscvUlx3s (D = \_zz_20_, Q = \_zz_27_).
|
|
Adding EN signal on $procdff$3650 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB, Q = \_zz_26_).
|
|
Adding EN signal on $procdff$3649 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \_zz_25_).
|
|
Adding EN signal on $procdff$3648 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7702$1249_Y, Q = \_zz_15_).
|
|
Adding EN signal on $procdff$3647 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7701$1248_Y, Q = \_zz_14_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4109 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_8_, Q = \_zz_14_, rval = 0).
|
|
Adding EN signal on $procdff$3646 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7700$1247_Y, Q = \_zz_13_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4111 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_7_ [1:0], Q = \_zz_13_ [1:0], rval = 2'00).
|
|
Adding EN signal on $procdff$3645 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:7699$1246_Y, Q = \_zz_12_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4113 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_6_, Q = \_zz_12_, rval = 1'0).
|
|
Adding EN signal on $procdff$3644 ($dff) from module PQVexRiscvUlx3s (D = 4'xxxx, Q = \_zz_9_).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4115 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4115 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4115 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4115 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3643 ($dff) from module PQVexRiscvUlx3s (D = 0, Q = \_zz_8_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4116 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3642 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, Q = \_zz_7_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4117 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4117 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3641 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \_zz_6_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4118 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3720 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$procmux$1874_Y, Q = \systemDebugger_1_.dispatcher_counter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3719 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_headerLoaded[0:0], Q = \systemDebugger_1_.dispatcher_headerLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3718 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_dataLoaded[0:0], Q = \systemDebugger_1_.dispatcher_dataLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3717 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_headerShifter [7:1] }, Q = \systemDebugger_1_.dispatcher_headerShifter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3716 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_dataShifter [66:1] }, Q = \systemDebugger_1_.dispatcher_dataShifter).
|
|
Adding SRST signal on $flatten\pipelinedMemoryBusToApbBridge_1_.$procdff$3713 ($dff) from module PQVexRiscvUlx3s (D = { \myMem_1_.myReg [31:29] \myMem_1_.myReg [23:21] \myMem_1_.myReg [14:10] }, Q = { \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [31:29] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [23:21] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [14:10] }, rval = 11'00000000000).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3705 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_.myReg).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$3888 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$3895 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$3894 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$3898 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$3897 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$3896 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3686 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6563$1110_DATA, Q = \memory_ramBlocks_1._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3685 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6562$1109_DATA, Q = \memory_ramBlocks_1._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3684 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6561$1108_DATA, Q = \memory_ramBlocks_1._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3683 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6560$1107_DATA, Q = \memory_ramBlocks_1._zz_5_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$3888 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$3895 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$3894 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$3898 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$3897 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$3896 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3703 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6495$1065_DATA, Q = \memory_ramBlocks_0._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3702 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6494$1064_DATA, Q = \memory_ramBlocks_0._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3701 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6493$1063_DATA, Q = \memory_ramBlocks_0._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3700 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6492$1062_DATA, Q = \memory_ramBlocks_0._zz_5_).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$3914 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tdi, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_fragment).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$3913 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tms, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_last).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$3912 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.\flowCCByToggle_1_.$logic_not$PQVexRiscvUlx3s.v:768$104_Y, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_target).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3730 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.DebugPlugin_busReadDataReg [31:5] \jtagBridge_1_.io_remote_rsp_payload_data [4:0] }, Q = \jtagBridge_1_.system_rsp_payload_data).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3729 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_payload_error).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4184 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3728 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$1918_Y, Q = \jtagBridge_1_.system_rsp_valid, rval = 1'1).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4185 ($sdff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_valid).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3727 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$1896_Y, Q = \jtagBridge_1_.jtag_readArea_shifter).
|
|
Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3726 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$1902_Y, Q = \jtagBridge_1_.jtag_idcodeArea_shifter, rval = 268443647).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4192 ($sdff) from module PQVexRiscvUlx3s (D = { \io_jtag_tdi \jtagBridge_1_.jtag_idcodeArea_shifter [31:1] }, Q = \jtagBridge_1_.jtag_idcodeArea_shifter).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3724 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$0\jtag_tap_instructionShift[3:0], Q = \jtagBridge_1_.jtag_tap_instructionShift).
|
|
Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3723 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$1910_Y, Q = \jtagBridge_1_.jtag_tap_instruction, rval = 4'0001).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4199 ($sdff) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_tap_instructionShift, Q = \jtagBridge_1_.jtag_tap_instruction).
|
|
Adding EN signal on $flatten\core_ibus_decoder.$procdff$3664 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_1, Q = \core_ibus_decoder.logic_rspHits_1).
|
|
Adding EN signal on $flatten\core_ibus_decoder.$procdff$3663 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_0, Q = \core_ibus_decoder.logic_rspHits_0).
|
|
Adding EN signal on $flatten\core_dbus_decoder.$procdff$3668 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_2, Q = \core_dbus_decoder.logic_rspHits_2).
|
|
Adding EN signal on $flatten\core_dbus_decoder.$procdff$3667 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_1, Q = \core_dbus_decoder.logic_rspHits_1).
|
|
Adding EN signal on $flatten\core_dbus_decoder.$procdff$3666 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_0, Q = \core_dbus_decoder.logic_rspHits_0).
|
|
Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$3916 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.pushing, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.risingOccupancy).
|
|
Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$3915 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_payload_inst 1'0 }, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c._zz_3_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4207 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3880 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_125_[2:0], Q = \core_cpu._zz_125_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3872 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3871 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_1).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3870 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3868 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mie_MSIE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3867 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [7], Q = \core_cpu.CsrPlugin_mie_MTIE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3866 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [11], Q = \core_cpu.CsrPlugin_mie_MEIE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3862 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [31:2], Q = \core_cpu.CsrPlugin_mtvec_base).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3861 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [1:0], Q = \core_cpu.CsrPlugin_mtvec_mode).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3852 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_59_[0:0], Q = \core_cpu._zz_59_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3851 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_57_[0:0], Q = \core_cpu._zz_57_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3850 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_55_[0:0], Q = \core_cpu._zz_55_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3849 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \core_cpu.IBusSimplePlugin_fetchPc_inc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3846 ($adff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \core_cpu.IBusSimplePlugin_fetchPc_pcReg).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4261 ($adffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4261 ($adffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3844 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_arbitration_isValid[0:0], Q = \core_cpu.memory_arbitration_isValid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3843 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\execute_arbitration_isValid[0:0], Q = \core_cpu.execute_arbitration_isValid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3842 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5279$925_Y, Q = \core_cpu.execute_CsrPlugin_csr_2946).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3841 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5276$923_Y, Q = \core_cpu.execute_CsrPlugin_csr_2818).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3840 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5273$921_Y, Q = \core_cpu.execute_CsrPlugin_csr_2944).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3839 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5270$919_Y, Q = \core_cpu.execute_CsrPlugin_csr_2816).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3838 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5267$917_Y, Q = \core_cpu.execute_CsrPlugin_csr_834).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3837 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5264$915_Y, Q = \core_cpu.execute_CsrPlugin_csr_773).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3836 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5261$913_Y, Q = \core_cpu.execute_CsrPlugin_csr_772).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3835 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5258$911_Y, Q = \core_cpu.execute_CsrPlugin_csr_836).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3834 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5255$909_Y, Q = \core_cpu.execute_CsrPlugin_csr_768).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3833 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_EXECUTE_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3832 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_27_, Q = \core_cpu.decode_to_execute_RS2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3831 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_2_ [1] \core_cpu._zz_384_ }, Q = \core_cpu.decode_to_execute_BRANCH_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3830 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_LESS_UNSIGNED, Q = \core_cpu.decode_to_execute_SRC_LESS_UNSIGNED).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3828 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC1, Q = \core_cpu.execute_to_memory_SRC1).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3827 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC1, Q = \core_cpu.decode_to_execute_SRC1).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3826 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_CSR, Q = \core_cpu.decode_to_execute_IS_CSR).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3824 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC2, Q = \core_cpu.execute_to_memory_SRC2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3823 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2, Q = \core_cpu.decode_to_execute_SRC2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3822 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LL, Q = \core_cpu.execute_to_memory_MUL_LL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3820 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_ENV_CTRL, Q = \core_cpu.execute_to_memory_ENV_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3819 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_9_, Q = \core_cpu.decode_to_execute_ENV_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3814 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LH, Q = \core_cpu.execute_to_memory_MUL_LH).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3812 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_VALID).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3811 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_REGFILE_WRITE_VALID, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s (D = \core_cpu._zz_191_, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3807 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.decode_to_execute_PC).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3806 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2_FORCE_ZERO, Q = \core_cpu.decode_to_execute_SRC2_FORCE_ZERO).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3805 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_304_ \core_cpu._zz_317_ }, Q = \core_cpu.decode_to_execute_ALU_BITWISE_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3804 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_BRANCH_DO, Q = \core_cpu.execute_to_memory_BRANCH_DO).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3803 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SHIFT_CTRL, Q = \core_cpu.execute_to_memory_SHIFT_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3802 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_319_ \core_cpu._zz_320_ }, Q = \core_cpu.decode_to_execute_SHIFT_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3801 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS2_SIGNED).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3799 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_MUL, Q = \core_cpu.execute_to_memory_IS_MUL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3798 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_MUL, Q = \core_cpu.decode_to_execute_IS_MUL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3797 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HL, Q = \core_cpu.execute_to_memory_MUL_HL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3795 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_ENABLE, Q = \core_cpu.execute_to_memory_MEMORY_ENABLE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3794 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_ENABLE, Q = \core_cpu.decode_to_execute_MEMORY_ENABLE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3793 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_373_ \core_cpu._zz_368_ }, Q = \core_cpu.decode_to_execute_ALU_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3792 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_INSTRUCTION, Q = \core_cpu.execute_to_memory_INSTRUCTION).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3791 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_62_, Q = \core_cpu.decode_to_execute_INSTRUCTION).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3790 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_DO_EBREAK, Q = \core_cpu.decode_to_execute_DO_EBREAK).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3788 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \core_cpu.execute_to_memory_MEMORY_STORE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3787 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_STORE, Q = \core_cpu.decode_to_execute_MEMORY_STORE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3785 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.execute_to_memory_BYPASSABLE_MEMORY_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3784 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3782 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB [1:0], Q = \core_cpu.execute_to_memory_MEMORY_ADDRESS_LOW).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3781 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_USE_SUB_LESS, Q = \core_cpu.decode_to_execute_SRC_USE_SUB_LESS).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3780 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS1_SIGNED).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3779 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_29_, Q = \core_cpu.decode_to_execute_RS1).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3778 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \core_cpu.execute_to_memory_BRANCH_CALC).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4317 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3777 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_DIV, Q = \core_cpu.execute_to_memory_IS_DIV).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3776 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_DIV, Q = \core_cpu.decode_to_execute_IS_DIV).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3775 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_183_ [31:0], Q = \core_cpu.execute_to_memory_SHIFT_RIGHT).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3774 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_43_, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_DATA).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3773 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HH, Q = \core_cpu.execute_to_memory_MUL_HH).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3772 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_CSR_WRITE_OPCODE, Q = \core_cpu.decode_to_execute_CSR_WRITE_OPCODE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3771 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_228_ [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_div_result).
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$3770 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2247_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_done, rval = 1'0).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4329 ($sdff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.memory_MulDivIterativePlugin_div_done).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3769 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$logic_and$PQVexRiscvUlx3s.v:5063$844_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_needRevert).
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$3768 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2093_Y, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0], rval = 0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3768 ($dff) from module PQVexRiscvUlx3s (D = 33'000000000000000000000000000000000, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [64:32]).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$4333 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4332 ($sdff) from module PQVexRiscvUlx3s (D = \core_cpu.memory_MulDivIterativePlugin_div_stage_0_outRemainder, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3767 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5062$835_Y, Q = \core_cpu.memory_MulDivIterativePlugin_rs2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3766 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832_Y [32], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [32]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3766 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0] [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3763 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2269_Y, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4352 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege, rval = 2'11).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4355 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4355 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3762 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2277_Y, Q = \core_cpu.CsrPlugin_interrupt_code).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4360 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2275_Y [3], Q = \core_cpu.CsrPlugin_interrupt_code [3], rval = 1'1).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4360 ($dffe) from module PQVexRiscvUlx3s (D = 3'xxx, Q = \core_cpu.CsrPlugin_interrupt_code [2:0], rval = 3'011).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4364 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4364 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4364 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3761 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5015$825_Y, Q = \core_cpu.CsrPlugin_minstret).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3759 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.CsrPlugin_interrupt_code, Q = \core_cpu.CsrPlugin_mcause_exceptionCode).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3758 ($dff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.CsrPlugin_mcause_interrupt).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4371 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$3757 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mip_MSIP, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3754 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.CsrPlugin_mepc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3751 ($dff) from module PQVexRiscvUlx3s (D = { $flatten\core_cpu.$0\_zz_62_[31:0] [31:25] $flatten\core_cpu.$0\_zz_62_[31:0] [14:0] }, Q = { \core_cpu._zz_62_ [31:25] \core_cpu._zz_62_ [14:0] }).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3749 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_58_, Q = \core_cpu._zz_60_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3748 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_fetchPc_pcReg, Q = \core_cpu._zz_58_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3745 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\DebugPlugin_busReadDataReg[31:0], Q = \core_cpu.DebugPlugin_busReadDataReg).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3744 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3743 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3742 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3738 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3737 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3736 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3733 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [36], Q = \core_cpu.DebugPlugin_stepIt).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3731 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2054_Y, Q = \core_cpu.DebugPlugin_resetIt).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$3902 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$3930 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\break_counter[6:0], Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.break_counter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$3927 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_2).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$3926 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.io_rxd_buffercc.buffers_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$3920 ($dff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$or$PQVexRiscvUlx3s.v:0$80_Y, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_shifter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$3902 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3710 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readOverflowError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readOverflowError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3709 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3708 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_readIntEnable).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3707 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_writeIntEnable).
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 208 unused cells and 236 unused wires.
|
|
<suppressed ~213 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~258 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~39 debug messages>
|
|
Removed a total of 13 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4382 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4382 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4368 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4368 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4368 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4114 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4112 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4112 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:702:run$4110 ($sdffce) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 21 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.13.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~259 debug messages>
|
|
|
|
2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4381 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4381 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4108 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4108 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4108 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4108 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~259 debug messages>
|
|
|
|
2.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4377 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4377 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4293 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4293 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~259 debug messages>
|
|
|
|
2.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4385 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2064_Y [1:0], Q = \core_cpu.DebugPlugin_busReadDataReg [1:0], rval = 2'00).
|
|
|
|
2.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.37. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~260 debug messages>
|
|
|
|
2.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.40. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.41. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.43. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.44. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 18 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol0$PQVexRiscvUlx3s.v:0$1092 (memory_ramBlocks_0.ram_symbol0).
|
|
Removed top 18 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol1$PQVexRiscvUlx3s.v:0$1093 (memory_ramBlocks_0.ram_symbol1).
|
|
Removed top 18 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol2$PQVexRiscvUlx3s.v:0$1094 (memory_ramBlocks_0.ram_symbol2).
|
|
Removed top 18 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol3$PQVexRiscvUlx3s.v:0$1095 (memory_ramBlocks_0.ram_symbol3).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1539 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1545 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4344 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4250 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4044 ($eq).
|
|
Removed top 31 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$3883 ($dff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$3879 ($adff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$auto$opt_dff.cc:764:run$4306 ($dffe).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3230 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3228 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3094_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2892_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2885_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2782_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2778_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2773_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2769_CMP0 ($eq).
|
|
Removed top 12 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2623 ($pmux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2617_CMP0 ($eq).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2542_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2475 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2471 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2455 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2447 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2443 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2349 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2347 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2343 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2341 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2337 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2328 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2327_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2326_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2325_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2323 ($mux).
|
|
Removed top 7 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2299 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2275 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2255 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2253 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2064 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2052 ($mux).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$1988_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$1980_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$1973_CMP0 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5267$917 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5264$915 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5261$913 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5258$911 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5255$909 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5062$835 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832 ($add).
|
|
Removed top 1 bits (of 33) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:5061$831 ($mux).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5061$830 ($not).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5061$830 ($not).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5015$825 ($add).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5013$824 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4845$796 ($sub).
|
|
Removed top 20 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4713$766 ($or).
|
|
Removed top 19 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4713$765 ($or).
|
|
Removed top 20 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4713$765 ($or).
|
|
Removed top 19 bits (of 32) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4713$765 ($or).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4510$688 ($sub).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4501$687 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4447$675 ($add).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4447$675 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4330$660 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4227$644 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4045$626 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4045$625 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4045$623 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4044$620 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4044$619 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4043$618 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4043$617 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4041$614 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4041$613 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4040$612 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4040$611 ($and).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3760$532 ($sub).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:3225$423 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2579$394 ($and).
|
|
Removed top 28 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2577$393 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2574$392 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2572$390 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2572$389 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2570$388 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2569$387 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2569$386 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2569$385 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2568$383 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2567$381 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2567$380 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2563$375 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2560$374 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2559$372 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2559$371 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2557$369 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2549$363 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2548$361 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2548$360 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2546$359 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2544$358 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2534$355 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2533$354 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2530$349 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2530$348 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2529$347 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2529$346 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2525$344 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2517$339 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2516$338 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2516$337 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2515$336 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2515$335 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2514$334 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2514$333 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2513$332 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2513$331 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2507$327 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2507$326 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2506$325 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2506$324 ($and).
|
|
Removed top 11 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2504$323 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2502$322 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2499$321 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2497$320 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2493$316 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2491$315 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2489$314 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2489$313 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2487$312 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2486$311 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2486$310 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2485$309 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2485$308 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2483$307 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2481$306 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2479$305 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2471$301 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2469$300 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2467$299 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2465$298 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2464$297 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2463$296 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2462$295 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2462$294 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2460$293 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2457$289 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2455$288 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2455$287 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2454$286 ($eq).
|
|
Removed top 3 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2451$285 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2449$284 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2445$280 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2442$278 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2442$277 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2439$276 ($and).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2411$271 ($add).
|
|
Removed top 31 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:2402$266 ($mux).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2398$262 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2386$259 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258 ($sub).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2382$257 ($and).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2382$257 ($and).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2382$257 ($and).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2382$256 ($not).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2382$256 ($not).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sshr$PQVexRiscvUlx3s.v:2373$253 ($sshr).
|
|
Removed top 15 bits (of 48) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2368$252 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1969_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1968_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1965_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1964_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1963_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1909_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1908_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$1894 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5650$959 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5635$956 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5634$955 ($eq).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5602$953 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5596$951 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5593$950 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5590$949 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5584$947 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5572$943 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5563$940 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5560$939 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$1890 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$1888 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$1884 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$1872 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5755$975 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4211 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4169 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4153 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4070 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3325 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3327 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$3905 ($dff).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3325 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3327 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$3905 ($dff).
|
|
Removed top 19 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4026 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4022 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3461 ($mux).
|
|
Removed top 7 bits (of 8) from port A of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$shl$PQVexRiscvUlx3s.v:0$77 ($shl).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
Removed top 6 bits (of 7) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
Removed top 2 bits (of 5) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1717_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1710 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1708 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1704 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1702 ($mux).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1684_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6365$1050 ($eq).
|
|
Removed top 3 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6364$1047 ($eq).
|
|
Removed top 3 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\apb3Router_1_.$procmux$1670 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3699 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3696 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3693 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3690 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1656 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1654 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1650 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1648 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1644 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1642 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1638 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1636 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3682 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3679 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3676 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3673 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1624 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1622 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1618 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1616 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1612 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1610 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1606 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1604 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$procmux$1600_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6732$1182 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6656$1141 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:6854$1219 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:6794$1185 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3272 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3274 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$3893 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3276 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3280 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1108$165 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procmux$3294 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3272 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3274 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$3893 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3276 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3280 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1108$165 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procmux$3294 ($mux).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258 ($sub).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258 ($sub).
|
|
Removed top 3 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1686 ($mux).
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0].
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832_Y.
|
|
Removed top 1 bits (of 2) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2382$256_Y.
|
|
Removed top 19 bits (of 32) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4713$765_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5560$939_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5563$940_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5572$943_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5584$947_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5590$949_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5593$950_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5596$951_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5602$953_Y.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3Router_1__io_input_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3UartCtrl_1__io_apb_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.io_apb_decoder_io_input_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.myMem_1__io_bus_PRDATA.
|
|
|
|
2.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 77 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.17. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.21. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.3. Continuing TECHMAP pass.
|
|
Using template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\_80_mul for cells of type $mul.
|
|
Using template $paramod\$__MUL18X18\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=32\A_SIGNED=0\B_SIGNED=0 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~98 debug messages>
|
|
|
|
2.22. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module PQVexRiscvUlx3s:
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5976$991 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2368$252 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2386$259 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2398$262 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2399$263 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2409$267 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2410$269 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2411$271 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4434$672 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4447$675 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4501$687 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5013$824 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5015$825 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5062$835 ($add).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3760$532 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4510$688 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4845$796 ($sub).
|
|
creating $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6656$1141 ($add).
|
|
creating $macc model for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6732$1182 ($sub).
|
|
creating $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:6794$1185 ($add).
|
|
creating $macc model for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:6854$1219 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
creating $macc model for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5755$975 ($add).
|
|
merging $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:6794$1185 into $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:6854$1219.
|
|
merging $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6656$1141 into $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6732$1182.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2386$259 into $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3760$532.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2410$269 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2409$267.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2411$271 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2409$267.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2399$263 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2398$262.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4447$675 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2368$252.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4845$796.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4510$688.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5062$835.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5015$825.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5013$824.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4501$687.
|
|
creating $alu model for $macc $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5755$975.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4434$672.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5976$991.
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2398$262: $auto$alumacc.cc:365:replace_macc$4467
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2409$267: $auto$alumacc.cc:365:replace_macc$4468
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2368$252: $auto$alumacc.cc:365:replace_macc$4469
|
|
creating $macc cell for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6732$1182: $auto$alumacc.cc:365:replace_macc$4470
|
|
creating $macc cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3760$532: $auto$alumacc.cc:365:replace_macc$4471
|
|
creating $macc cell for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:6854$1219: $auto$alumacc.cc:365:replace_macc$4472
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5976$991: $auto$alumacc.cc:485:replace_alu$4473
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4476
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4479
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146: $auto$alumacc.cc:485:replace_alu$4482
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112: $auto$alumacc.cc:485:replace_alu$4485
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56: $auto$alumacc.cc:485:replace_alu$4488
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66: $auto$alumacc.cc:485:replace_alu$4491
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65: $auto$alumacc.cc:485:replace_alu$4494
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10: $auto$alumacc.cc:485:replace_alu$4497
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24: $auto$alumacc.cc:485:replace_alu$4500
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4503
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4506
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4509
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200: $auto$alumacc.cc:485:replace_alu$4514
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200: $auto$alumacc.cc:485:replace_alu$4517
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156: $auto$alumacc.cc:485:replace_alu$4520
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194: $auto$alumacc.cc:485:replace_alu$4523
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2420$275: $auto$alumacc.cc:485:replace_alu$4526
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500: $auto$alumacc.cc:485:replace_alu$4529
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4434$672: $auto$alumacc.cc:485:replace_alu$4532
|
|
creating $alu cell for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5755$975: $auto$alumacc.cc:485:replace_alu$4535
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4501$687: $auto$alumacc.cc:485:replace_alu$4538
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5013$824: $auto$alumacc.cc:485:replace_alu$4541
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5015$825: $auto$alumacc.cc:485:replace_alu$4544
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5061$832: $auto$alumacc.cc:485:replace_alu$4547
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5062$835: $auto$alumacc.cc:485:replace_alu$4550
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2383$258: $auto$alumacc.cc:485:replace_alu$4553
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4510$688: $auto$alumacc.cc:485:replace_alu$4556
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4845$796: $auto$alumacc.cc:485:replace_alu$4559
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194: $auto$alumacc.cc:485:replace_alu$4562
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156: $auto$alumacc.cc:485:replace_alu$4565
|
|
created 31 $alu and 6 $macc cells.
|
|
|
|
2.23. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.23.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~24 debug messages>
|
|
Removed a total of 8 cells.
|
|
|
|
2.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~230 debug messages>
|
|
|
|
2.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.23.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3681 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6578$1104_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3678 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6575$1103_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3675 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6572$1102_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3672 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6569$1101_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3698 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6510$1059_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3695 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6507$1058_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3692 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6504$1057_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3689 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6501$1056_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4191 ($dffe) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_readArea_shifter [2], Q = \jtagBridge_1_.jtag_readArea_shifter [1], rval = 1'0).
|
|
|
|
2.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 9 unused cells and 74 unused wires.
|
|
<suppressed ~38 debug messages>
|
|
|
|
2.23.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~224 debug messages>
|
|
|
|
2.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.23.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.23.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.24. Executing MEMORY pass.
|
|
|
|
2.24.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.24.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:0$932' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1096' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1097' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1098' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1099' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$216' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1137' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1138' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1139' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1140' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$216' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2584$396' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2590$398' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6492$1062' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6493$1063' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6494$1064' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6495$1065' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1248$183' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6560$1107' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6561$1108' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6562$1109' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6563$1110' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1248$183' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
|
|
2.24.3. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 43 unused cells and 55 unused wires.
|
|
<suppressed ~44 debug messages>
|
|
|
|
2.24.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.24.6. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.25. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol0:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol0.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol1:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol1.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol2:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol2.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol3:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol3.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol0:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol0.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol1:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol1.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol2:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol2.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol3:
|
|
Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=100, cells=8, acells=2
|
|
Efficiency for rule 4.3: efficiency=100, cells=8, acells=4
|
|
Efficiency for rule 4.2: efficiency=88, cells=8, acells=8
|
|
Efficiency for rule 4.1: efficiency=44, cells=16, acells=16
|
|
Efficiency for rule 1.1: efficiency=22, cells=32, acells=32
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol3.7.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
|
|
2.27. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
|
|
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.27.2. Continuing TECHMAP pass.
|
|
Using template $paramod$38262e435a9f54db3b5bdc33b5e39b1fffa1b883\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$7bb2aa69d4fd7c6f9b4e5ff3b44b082f58457620\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$daa0f7328f1363afdd5c4a368994724043bb0143\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$d43eda8c7a9c0d8553340d69fdb90e3c23ae045b\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$402989f39058136e1c91563ca89ef77be3f22258\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$e972dec2c8e9d87dedcc7b8d6657a79929dfce90\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$c6e799b2419a2b3136828b67a5ba7b66be011cc7\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$b17af36c1cdb6b53ef0f4193fe4ca39cdda767c6\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$c8bb721bb514a4ce9108391f2b0356fba9ce1d15\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$1d007a3dc583a38431ecce96fa16dfe75f4886d8\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$6ade60ead834999d733df6b5d654ec29de8a7818\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$e6fbec2b698a856728a232050c4a183f62766acf\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$2fc6b69a16fac37efa83894c85587859abf36901\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$d9fc12e415d63b55cf16cab0b232fd766ef253e4\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$35a1a7c9d44970daf86e55fceadb5153a443a8aa\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$cbf5006e5db5f183b9479603f15e1e68b7c120d9\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$6d9f85c9db9c26b70d60c144294001c5156d7654\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$1af9d294c152f2c6f76a1157c1d315bbecf48af4\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$400fe83e0c146be115598976e9f786ad9b2f8b2b\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$e3a74bca3e03aac4fec86c742c6b024b52b65e30\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$827e4d31772d231df1b8b6ba8f158ef8c61c9924\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$98ee0b40fd9ad77dc8426aa78c6915300fd20a60\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$f7a51628e100907e1b8f50a114c49335454242da\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$4d4b8aa4d103d30f62122a1b56ee1ff8e41fdea9\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$7543939f955f4038d5120bb2b6b34d6288a11bea\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$2050c2d1847ac18632980336cbc6f622ece35fbd\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$6c1504325225c90073a350bdc60de5471d14255a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$81088628bfba82ee3afb0f1ad367423cda75bbcd\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$282e38012fe59acea2bb00a960f24d02bc47005b\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$0c3fb6ac3b3e837a4bba8cf2bcb9352c280ef28c\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$8ec4356189e3b42c282d8d01c7d6b7210a42839c\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$bb255839cf5f7987a052681950c69f11d6c361a1\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
No more expansions possible.
|
|
<suppressed ~802 debug messages>
|
|
|
|
2.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.2.
|
|
Updated properties: dups=2 waste=0 efficiency=50
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: core_cpu.RegFilePlugin_regFile.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: core_cpu.RegFilePlugin_regFile.0.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: core_cpu.RegFilePlugin_regFile.0.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: core_cpu.RegFilePlugin_regFile.0.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: core_cpu.RegFilePlugin_regFile.1.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: core_cpu.RegFilePlugin_regFile.1.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: core_cpu.RegFilePlugin_regFile.1.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: core_cpu.RegFilePlugin_regFile.1.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: core_cpu.RegFilePlugin_regFile.2.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: core_cpu.RegFilePlugin_regFile.2.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: core_cpu.RegFilePlugin_regFile.2.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: core_cpu.RegFilePlugin_regFile.2.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: core_cpu.RegFilePlugin_regFile.3.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: core_cpu.RegFilePlugin_regFile.3.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: core_cpu.RegFilePlugin_regFile.3.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: core_cpu.RegFilePlugin_regFile.3.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: core_cpu.RegFilePlugin_regFile.4.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: core_cpu.RegFilePlugin_regFile.4.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: core_cpu.RegFilePlugin_regFile.4.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: core_cpu.RegFilePlugin_regFile.4.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: core_cpu.RegFilePlugin_regFile.5.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: core_cpu.RegFilePlugin_regFile.5.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: core_cpu.RegFilePlugin_regFile.5.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: core_cpu.RegFilePlugin_regFile.5.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: core_cpu.RegFilePlugin_regFile.6.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: core_cpu.RegFilePlugin_regFile.6.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: core_cpu.RegFilePlugin_regFile.6.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: core_cpu.RegFilePlugin_regFile.6.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: core_cpu.RegFilePlugin_regFile.7.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: core_cpu.RegFilePlugin_regFile.7.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: core_cpu.RegFilePlugin_regFile.7.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: core_cpu.RegFilePlugin_regFile.7.1.1
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
|
|
2.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.29.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~52 debug messages>
|
|
|
|
2.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~711 debug messages>
|
|
|
|
2.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~273 debug messages>
|
|
Removed a total of 91 cells.
|
|
|
|
2.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 3 unused cells and 1237 unused wires.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.30.5. Finished fast OPT passes.
|
|
|
|
2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
2.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~293 debug messages>
|
|
|
|
2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2492:
|
|
Old ports: A=4'0000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 3'011 }, Y=\core_cpu._zz_130_ [3:0]
|
|
New ports: A=2'00, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 1'1 }, Y={ \core_cpu._zz_130_ [3] \core_cpu._zz_130_ [0] }
|
|
New connections: \core_cpu._zz_130_ [2:1] = { 1'0 \core_cpu._zz_130_ [0] }
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2623:
|
|
Old ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [30:25] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [30:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31:20] }, Y=\core_cpu.execute_BranchPlugin_branch_src2 [19:0]
|
|
New ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [24:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [24:20] }, Y={ \core_cpu.execute_BranchPlugin_branch_src2 [19:11] \core_cpu.execute_BranchPlugin_branch_src2 [4:0] }
|
|
New connections: \core_cpu.execute_BranchPlugin_branch_src2 [10:5] = \core_cpu.decode_to_execute_INSTRUCTION [30:25]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2874:
|
|
Old ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_69_ [7:0] \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated
|
|
New ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated [31:8]
|
|
New connections: \core_cpu.writeBack_DBusSimplePlugin_rspFormated [7:0] = \core_cpu._zz_69_ [7:0]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2891:
|
|
Old ports: A=\core_cpu.decode_to_execute_RS2, B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:0] }, Y=\_zz_20_
|
|
New ports: A=\core_cpu.decode_to_execute_RS2 [31:8], B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:8] }, Y=\_zz_20_ [31:8]
|
|
New connections: \_zz_20_ [7:0] = \core_cpu.decode_to_execute_RS2 [7:0]
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2945:
|
|
Old ports: A=0, B={ \core_cpu.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=30'000000000000000000000000000000, B=\core_cpu.CsrPlugin_mtvec_base, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5557$938:
|
|
Old ports: A=4'0001, B=4'1001, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5557$938_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5557$938_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5557$938_Y [2:0] = 3'001
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5560$939:
|
|
Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$4447 [1:0]
|
|
New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$4447 [0]
|
|
New connections: $auto$wreduce.cc:454:run$4447 [1] = $auto$wreduce.cc:454:run$4447 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942:
|
|
Old ports: A=4'0110, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y [3] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y [1] }
|
|
New connections: { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y [2] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y [0] } = { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5569$942_Y [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5575$944:
|
|
Old ports: A=4'0100, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5575$944_Y
|
|
New ports: A=2'01, B=2'10, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5575$944_Y [3:2]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5575$944_Y [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5581$946:
|
|
Old ports: A=4'1010, B=4'0010, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5581$946_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5581$946_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5581$946_Y [2:0] = 3'010
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5584$947:
|
|
Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$4450 [2:0]
|
|
New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$4450 [2] $auto$wreduce.cc:454:run$4450 [0] }
|
|
New connections: $auto$wreduce.cc:454:run$4450 [1] = $auto$wreduce.cc:454:run$4450 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5590$949:
|
|
Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:454:run$4451 [1:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4451 [1]
|
|
New connections: $auto$wreduce.cc:454:run$4451 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5596$951:
|
|
Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:454:run$4453 [2:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4453 [2]
|
|
New connections: $auto$wreduce.cc:454:run$4453 [1:0] = 2'11
|
|
Consolidated identical input bits for $pmux cell $procmux$1552:
|
|
Old ports: A=4'1111, B=8'00010011, Y=\_zz_22_
|
|
New ports: A=2'11, B=4'0001, Y=\_zz_22_ [2:1]
|
|
New connections: { \_zz_22_ [3] \_zz_22_ [0] } = { \_zz_22_ [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $ternary$PQVexRiscvUlx3s.v:7700$1247:
|
|
Old ports: A={ \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \_zz_7_ [31:2] 2'00 }, Y=$ternary$PQVexRiscvUlx3s.v:7700$1247_Y
|
|
New ports: A=\core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2], B=\_zz_7_ [31:2], Y=$ternary$PQVexRiscvUlx3s.v:7700$1247_Y [31:2]
|
|
New connections: $ternary$PQVexRiscvUlx3s.v:7700$1247_Y [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2937:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B={ \core_cpu.CsrPlugin_mepc [31:2] 2'00 }, Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=\core_cpu.CsrPlugin_mepc [31:2], Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2942:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0], Y=\core_cpu.CsrPlugin_jumpInterface_payload
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\core_cpu.CsrPlugin_jumpInterface_payload [31:2]
|
|
New connections: \core_cpu.CsrPlugin_jumpInterface_payload [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:3647$495:
|
|
Old ports: A={ \core_cpu.execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\core_cpu.CsrPlugin_jumpInterface_payload, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload
|
|
New ports: A=\core_cpu.execute_to_memory_BRANCH_CALC [31:1], B={ \core_cpu.CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1]
|
|
New connections: \core_cpu.IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2918:
|
|
Old ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500_Y [31:2] 2'00 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload, Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] }
|
|
New ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3664$500_Y [31:2] 1'0 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1] }
|
|
New connections: $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 19 changes.
|
|
|
|
2.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
2.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 7 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~5 debug messages>
|
|
|
|
2.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~293 debug messages>
|
|
|
|
2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~293 debug messages>
|
|
|
|
2.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ecp5_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Using extmapper simplemap for cells of type $adff.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $adffe.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc.
|
|
add \core_ibus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_valid (1 bits, unsigned)
|
|
add bits \core_ibus_decoder._zz_5_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
|
|
add { \core_cpu.execute_to_memory_MUL_HH \core_cpu.execute_to_memory_MUL_LL [31:16] } (48 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_LH (32 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_HL (32 bits, unsigned)
|
|
add \core_cpu.memory_to_writeBack_MUL [63:32] (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2411$270_Y (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2410$268_Y (32 bits, unsigned)
|
|
add 2 (32 bits, unsigned)
|
|
packed 2 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=33\B_WIDTH=32\Y_WIDTH=33 for cells of type $alu.
|
|
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
|
|
add \core_dbus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.dBus_rsp_ready (1 bits, unsigned)
|
|
add bits \core_dbus_decoder._zz_6_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=11 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=1\Y_WIDTH=20 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
|
|
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.75. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~2327 debug messages>
|
|
|
|
2.33.76. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~35 debug messages>
|
|
Removed 0 unused cells and 8 unused wires.
|
|
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
|
|
add \core_cpu.decode_to_execute_SRC1 (32 bits, signed)
|
|
add { 1'0 \core_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
|
|
add \core_cpu._zz_211_ (32 bits, signed)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
add \core_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned)
|
|
add bits \core_cpu.IBusSimplePlugin_pending_inc (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=2 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa.
|
|
Using template $paramod\_90_fa\WIDTH=48 for cells of type $fa.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=3 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~2691 debug messages>
|
|
|
|
2.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~3147 debug messages>
|
|
|
|
2.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~1887 debug messages>
|
|
Removed a total of 629 cells.
|
|
|
|
2.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1257 unused cells and 3833 unused wires.
|
|
<suppressed ~1263 debug messages>
|
|
|
|
2.34.5. Finished fast OPT passes.
|
|
|
|
2.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
2.37. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.37.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
|
|
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
|
|
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
|
|
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
|
|
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
|
|
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
|
|
Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_.
|
|
Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_.
|
|
Using template \$_DFFE_PP1N_ for cells of type $_DFFE_PP1N_.
|
|
No more expansions possible.
|
|
<suppressed ~2290 debug messages>
|
|
|
|
2.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~94 debug messages>
|
|
|
|
2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.40. Executing ECP5_GSR pass (implement FF init values).
|
|
Handling GSR in PQVexRiscvUlx3s.
|
|
|
|
2.41. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
2.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 10511 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.44. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.44.1. Extracting gate netlist of module `\PQVexRiscvUlx3s' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 6102 gates and 8242 wires to a netlist network with 2138 inputs and 1509 outputs.
|
|
|
|
2.44.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + dress
|
|
ABC: Total number of equiv classes = 2025.
|
|
ABC: Participating nodes from both networks = 4376.
|
|
ABC: Participating nodes from the first network = 2100. ( 80.00 % of nodes)
|
|
ABC: Participating nodes from the second network = 2276. ( 86.70 % of nodes)
|
|
ABC: Node pairs (any polarity) = 2100. ( 80.00 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 1662. ( 63.31 % of names can be moved)
|
|
ABC: Total runtime = 0.21 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.44.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 2623
|
|
ABC RESULTS: internal signals: 4595
|
|
ABC RESULTS: input signals: 2138
|
|
ABC RESULTS: output signals: 1509
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 4810 unused wires.
|
|
|
|
2.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.45.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10110000000010110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429409791 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663244 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11100000000000001111000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001010001001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=15091 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65536 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$746424d0983081829316163db34337ccf8ceb1ee\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2147450880 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111110100000000000000 for cells of type $lut.
|
|
Using template $paramod$58f333b1684fbb0b09cad2f8a7d278f749397c26\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod$ac6f7ebcdc72793173744ada7c7ce801bc233a4d\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=721420288 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000111011100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065336832 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2004287600 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000011101111111111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1090519040 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100010001001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16777216 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073709056 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=20479 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011100000 for cells of type $lut.
|
|
Using template $paramod$d6a97cece58353cd8de5b6e824f1d055bdb32a45\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2139029631 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111100000000000000000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000100 for cells of type $lut.
|
|
Using template $paramod$ef003d70d3febf7a5568510cba4a0111646430ac\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429470991 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100110011 for cells of type $lut.
|
|
Using template $paramod$8c4a05941f55bb06326bc324da9ead3ccfa4bfc8\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101000110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001111101011110000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
|
|
Using template $paramod$43b35b87196cad0a06a38d61f4fde3235e5ee137\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=11141183 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110001 for cells of type $lut.
|
|
Using template $paramod$6e8e9a95aa7012438678197fd66a79121b4bccb4\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=251723656 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268435456 for cells of type $lut.
|
|
Using template $paramod$4f86f7450df106cfc0b46ec818faf56ccaad25ac\$lut for cells of type $lut.
|
|
Using template $paramod$f340a7e85fbe3e11c384ecf1cd11a7f6ad674e2c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod$b1bd2a921ec0f1ea0cc7578a2bcf32d761c7f62f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2139095040 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000010010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1090519105 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=47883 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549387 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10110000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=218103821 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65423 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252641501 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010111110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010101010011001100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=24383 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073741824 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100010001000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
|
|
Using template $paramod$dd6948ac36bee735182831345cfd009aa50d8601\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001110101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001011010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=8355711 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100100010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1303511040 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100010011110100010001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110101110001 for cells of type $lut.
|
|
Using template $paramod$57fff8aec24b6f871ae10cc88359a481bbdd3e2d\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101011011100001111000011100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10001101111011110011110000010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=262851599 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1142743210 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101011100110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100111111110000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2035471 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268398592 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=15990784 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=5177344 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663091 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110001010101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100111110101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001000110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011111000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1580370602 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011001111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=125239296 for cells of type $lut.
|
|
Using template $paramod$f681f3bc2f183cf0b7ca5bce4be86a556250e16c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100110011001111000010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut.
|
|
Using template $paramod$76666f44bff191e671564a6be8ce47db7409d0b8\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010111100001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001000100011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16639 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1431683900 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001111111101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001100101010101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001100111111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100011100001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110111011101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000101010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010101010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000100010000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429467376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252654421 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=866840816 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=720896 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011011101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=48911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10110000111111111111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196148992 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111101001111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000000001111010011110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101111010000001100110011001100 for cells of type $lut.
|
|
Using template $paramod$b1d156d74856176edf19ed75f67a0cd91d5a9036\$lut for cells of type $lut.
|
|
Using template $paramod$81ee01f40718b5930dae8e3ff79bda1d7bc9c621\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
|
|
Using template $paramod$6305bea2049314474329c24b6615ab2d9739e87a\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111001110001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1425080319 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
|
|
Using template $paramod$9abd567e56fa5e5fe88aefab580dea7b3d3324a7\$lut for cells of type $lut.
|
|
Using template $paramod$c6d51bbba2974d40075f64507965a1fed88c7c87\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101001010110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110111000010001110111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~5958 debug messages>
|
|
|
|
2.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in PQVexRiscvUlx3s.
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26045.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26239.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26235.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26243.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26229.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26247.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26233.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26237.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26241.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26245.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26249.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26261.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26343.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26355.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26355.lut2 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26355.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut4 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut5 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut6 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut7 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26379.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26366.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26367.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26370.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26371.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26376.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26382.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26386.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26404.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26515.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26515.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26517.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26517.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26517.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26815.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26034.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26048.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26040.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26019.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26044.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26027.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25857.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25861.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25837.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26020.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26023.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26031.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26024.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26036.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26025.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26037.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25369.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25425.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25534.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25517.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25498.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25499.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25478.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25483.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25387.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26041.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26403.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26368.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26364.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26352.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26043.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26039.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26035.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26030.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26026.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26021.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26017.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25943.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25944.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25931.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25932.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25479.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25923.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25409.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25373.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25905.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25901.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25893.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25960.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25963.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25573.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25976.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25972.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25555.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25556.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25556.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut2 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut3 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25390.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25391.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25750.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25729.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25991.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26003.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25691.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25354.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25332.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25312.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25208.lut3 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut6 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24604.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24604.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24598.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24598.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24598.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut5 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut7 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut7 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut7 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25613.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut3 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut5 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut7 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut3 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24472.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24365.lut3 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut2 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut3 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut4 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut5 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut6 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut7 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24335.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25292.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24356.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24364.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24362.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24365.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24377.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25294.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24392.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24333.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24338.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24409.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24412.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24416.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24447.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24452.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24456.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24469.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24469.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24470.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24371.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24481.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24481.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24482.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24483.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24468.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24486.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24488.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24496.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24501.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24519.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24522.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24523.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24524.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24526.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24530.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24531.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24529.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24531.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24543.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24547.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24569.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24580.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24580.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24587.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24601.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24602.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24604.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24605.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24609.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24611.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24642.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24664.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24694.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24706.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24727.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24739.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24746.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24744.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24744.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25897.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24365.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24765.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24768.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26011.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25553.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26028.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25690.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25983.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26004.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25821.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26000.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24987.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25987.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25432.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25443.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25070.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25984.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25067.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25072.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25077.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25086.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25099.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25533.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25102.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25783.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25980.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25159.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25158.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25157.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$24638.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25186.lut1 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26033.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25187.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25188.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25208.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25208.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25407.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25245.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25245.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25254.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25257.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25262.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25257.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25267.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25267.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25268.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25271.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25275.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25275.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25278.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25283.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25271.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25292.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25293.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25294.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25293.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25297.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25297.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25299.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25304.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25305.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25309.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25311.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25312.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25313.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25316.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25316.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25318.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25313.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25311.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25328.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25330.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25330.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25331.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25332.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25335.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25335.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25337.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25331.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25350.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25352.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25353.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25354.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25357.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25357.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25359.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25353.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25352.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25424.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25369.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25371.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25371.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25372.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25373.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25376.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25376.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25378.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25372.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25387.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25389.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25390.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25391.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25394.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25394.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25396.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25389.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25405.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25407.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25408.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25409.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25412.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25412.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25414.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25408.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25418.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25424.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25425.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25921.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25432.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25434.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25443.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25445.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25449.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25449.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25451.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25446.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25445.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25460.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25462.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25463.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25466.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25468.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25466.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25462.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25477.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25478.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25479.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25460.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25927.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25483.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25485.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25498.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25499.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25504.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25501.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25504.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25506.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25516.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25517.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25522.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25519.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25522.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25524.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25533.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25535.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25964.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25939.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25540.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25540.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25535.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25543.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25516.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25553.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25405.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25555.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25556.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25561.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25561.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25563.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25573.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25575.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25583.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25952.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25592.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25594.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25594.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25595.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25572.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25601.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25956.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25611.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25613.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25614.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25620.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25630.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25632.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25632.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25641.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25652.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25654.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25655.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25661.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25968.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25671.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25673.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25674.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25680.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25673.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25691.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25693.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25700.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25709.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25711.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25711.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25712.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25718.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25728.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25729.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25730.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25733.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25733.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25735.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25745.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25746.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25747.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25750.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25752.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25746.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25762.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25764.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25764.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25995.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25771.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25781.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25783.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25790.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25800.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25802.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25809.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25999.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25820.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25821.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25822.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26018.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25825.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25827.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25825.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25838.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25992.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25847.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26008.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25856.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25857.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25858.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25861.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25863.lut0 (4 -> 2)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26012.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25870.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25872.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25877.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25878.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25654.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25881.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25877.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25892.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25892.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25893.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25896.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25896.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25897.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25900.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25900.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25901.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25904.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25904.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25905.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25907.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25907.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25909.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25909.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25911.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25911.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25913.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25913.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25915.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25915.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25917.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25917.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25919.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25919.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25427.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25921.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25838.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25923.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25925.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25925.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25927.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25929.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25929.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25931.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25932.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25934.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25936.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25936.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25996.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25934.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25939.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25941.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25941.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25942.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25943.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25944.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25947.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25949.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25949.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25951.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25951.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25952.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25955.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25955.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25956.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26022.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25959.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25959.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25960.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25962.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25963.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25964.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25967.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25967.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25968.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25971.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25972.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25975.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25976.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25971.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25979.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25979.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25980.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25982.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25983.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25984.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25975.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25986.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25987.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25988.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25947.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25991.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25992.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25765.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25995.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25996.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25784.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25998.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25999.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26000.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26002.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26003.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26004.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25988.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26007.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26007.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26008.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$25840.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26010.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26011.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26012.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26015.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26016.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26017.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26018.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26019.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26020.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26021.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26022.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26023.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26024.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26025.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26026.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26027.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26028.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26029.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26030.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26031.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26032.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26033.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26034.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26035.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26036.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26037.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26038.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26039.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26040.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26041.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26042.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26043.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26044.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26045.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26046.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26047.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26048.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26047.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26065.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26066.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26067.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26068.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26069.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26070.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26071.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26072.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26069.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26046.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26065.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26066.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26067.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26068.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26070.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26071.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26072.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26179.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26182.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26042.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26226.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26222.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26231.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26219.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26222.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26224.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26226.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26219.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26229.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26231.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26224.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26233.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26235.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26251.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26237.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26239.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26255.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26241.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26243.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26259.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26245.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26247.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26263.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26249.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26251.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26253.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26253.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26255.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26257.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26257.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26259.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26269.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26261.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26263.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26265.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26265.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26267.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26269.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26273.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26271.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26267.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26273.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26277.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26275.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26271.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26277.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26279.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26275.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26279.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26330.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26342.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26342.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26343.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26361.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26365.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26352.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26350.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26369.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26355.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26358.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26362.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26361.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26362.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26363.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26364.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26365.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26366.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26367.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26368.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26369.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26370.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26371.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26372.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26373.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26363.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26385.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26376.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26373.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26379.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26372.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26399.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26382.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26385.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26386.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26390.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26400.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26393.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26390.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26405.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26396.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26393.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26399.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26400.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26402.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26403.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26404.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26405.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26406.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26407.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26408.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26396.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26402.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26408.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26407.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26406.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26474.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26515.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26517.lut0 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26516.lut1 (4 -> 0)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26032.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26029.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26038.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26680.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26679.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26680.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26741.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26826.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26709.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26709.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26743.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26714.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26714.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26767.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26741.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26743.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26767.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26835.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26781.lut1 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26781.lut0 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26810.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26798.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26804.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26804.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26798.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26810.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26815.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26833.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26821.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26823.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26821.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26826.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26829.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26829.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26823.lut1 (4 -> 1)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26831.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26833.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26835.lut0 (4 -> 3)
|
|
Optimizing lut $abc$24323$auto$blifparse.cc:498:parse_blif$26831.lut1 (4 -> 1)
|
|
Removed 0 unused cells and 5536 unused wires.
|
|
|
|
2.47. Executing AUTONAME pass.
|
|
Renamed 101231 objects in module PQVexRiscvUlx3s (93 iterations).
|
|
<suppressed ~8828 debug messages>
|
|
|
|
2.48. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.48.1. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
|
|
2.48.2. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Removed 0 unused modules.
|
|
|
|
2.49. Printing statistics.
|
|
|
|
=== PQVexRiscvUlx3s ===
|
|
|
|
Number of wires: 4066
|
|
Number of wire bits: 21890
|
|
Number of public wires: 4066
|
|
Number of public wire bits: 21890
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 6313
|
|
CCU2C 236
|
|
DP16KD 64
|
|
L6MUX21 90
|
|
LUT4 3175
|
|
MULT18X18D 4
|
|
PFUMX 547
|
|
TRELLIS_DPR16X4 38
|
|
TRELLIS_FF 2159
|
|
|
|
2.50. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.51. Executing JSON backend.
|
|
|
|
Warnings: 1 unique messages, 2 total
|
|
End of script. Logfile hash: 47f720c82e, CPU: user 27.24s system 1.20s, MEM: 2224.63 MB peak
|
|
Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
|
|
Time spent: 35% 8x techmap (10 sec), 16% 29x opt_clean (4 sec), ...
|