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8488 lines
686 KiB
8488 lines
686 KiB
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
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-- Parsing `PQVexRiscvUlx3s.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend: PQVexRiscvUlx3s.v
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Parsing Verilog input from `PQVexRiscvUlx3s.v' to AST representation.
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Generating RTLIL representation for module `\BufferCC'.
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Generating RTLIL representation for module `\BufferCC_1_'.
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Generating RTLIL representation for module `\UartCtrlTx'.
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Generating RTLIL representation for module `\UartCtrlRx'.
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Generating RTLIL representation for module `\StreamFifoLowLatency'.
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Generating RTLIL representation for module `\FlowCCByToggle'.
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Generating RTLIL representation for module `\UartCtrl'.
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Generating RTLIL representation for module `\StreamFifo'.
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Generating RTLIL representation for module `\StreamArbiter'.
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Generating RTLIL representation for module `\StreamFork'.
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Generating RTLIL representation for module `\StreamFifoLowLatency_1_'.
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Generating RTLIL representation for module `\StreamArbiter_1_'.
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Generating RTLIL representation for module `\StreamFork_1_'.
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Generating RTLIL representation for module `\BufferCC_2_'.
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Generating RTLIL representation for module `\VexRiscv'.
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Generating RTLIL representation for module `\JtagBridge'.
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Generating RTLIL representation for module `\SystemDebugger'.
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Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'.
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Generating RTLIL representation for module `\Apb3UartCtrl'.
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Generating RTLIL representation for module `\MyMem'.
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Generating RTLIL representation for module `\Apb3Decoder'.
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Generating RTLIL representation for module `\Apb3Router'.
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Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s'.
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Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_2_'.
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Generating RTLIL representation for module `\PQVexRiscvUlx3s'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -top PQVexRiscvUlx3s -json PQVexRiscvUlx3s.json' --
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2. Executing SYNTH_ECP5 pass.
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2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_SLICE'.
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Generating RTLIL representation for module `\DP16KD'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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2.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\DCUA'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Successfully finished Verilog frontend.
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2.3. Executing HIERARCHY pass (managing design hierarchy).
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2.3.1. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_2_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork_1_
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Used module: \StreamArbiter_1_
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s_1_
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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2.3.2. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_2_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork_1_
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Used module: \StreamArbiter_1_
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s_1_
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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Removed 0 unused modules.
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2.4. Executing PROC pass (convert processes to netlists).
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2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1435'.
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Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:0$1129'.
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Cleaned up 1 empty switch.
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2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1516 in module TRELLIS_FF.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8122$1288 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8063$1275 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8013$1268 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7991$1263 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7434$1256 in module PipelinedMemoryBusArbiter_2_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7427$1255 in module PipelinedMemoryBusArbiter_2_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7281$1252 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7274$1251 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7098$1247 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7086$1229 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7073$1225 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7060$1221 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7048$1218 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6976$1210 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6964$1189 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6951$1185 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6938$1181 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6925$1177 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6910$1174 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6835$1162 in module PipelinedMemoryBusRamUlx3s_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6767$1117 in module PipelinedMemoryBusRamUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6668$1083 in module Apb3Router.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6624$1082 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6616$1081 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6486$1056 in module MyMem.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6361$1047 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6341$1046 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6324$1045 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6307$1044 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6290$1043 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6273$1042 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6253$1037 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6245$1036 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6238$1035 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6218$1034 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6182$1019 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5992$1014 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5982$1011 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5968$1009 in module PipelinedMemoryBusToApbBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5913$1005 in module SystemDebugger.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5887$1001 in module SystemDebugger.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5776$984 in module JtagBridge.
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Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5748$981 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5694$964 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5470$956 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4855$800 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4846$791 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4839$790 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4832$789 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4825$788 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4817$787 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4809$786 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4800$785 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4791$784 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4782$783 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4763$782 in module VexRiscv.
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Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4695$728 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4684$726 in module VexRiscv.
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Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4661$725 in module VexRiscv.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4637$713 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4628$710 in module VexRiscv.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4619$709 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4602$704 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4588$703 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4559$698 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4479$692 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4467$685 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4431$676 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4403$674 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4323$666 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4306$665 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4241$662 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4227$661 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4213$657 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4204$655 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4168$633 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4154$617 in module VexRiscv.
|
|
Marked 16 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4107$612 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4094$610 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4083$609 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4073$606 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4058$600 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4044$599 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3977$592 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3961$590 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3946$589 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3936$579 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3912$570 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3877$558 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3856$552 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3830$534 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3812$528 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3803$526 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3796$525 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3788$523 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3777$519 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3770$517 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3763$516 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3747$515 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3737$514 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3730$513 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3719$511 in module VexRiscv.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3698$510 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3684$509 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3676$508 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3667$507 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3659$506 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3646$496 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3637$495 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3628$494 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3621$493 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3614$492 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3602$484 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3593$483 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3580$473 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3561$472 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3550$471 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3522$468 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3507$467 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3500$465 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3492$463 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3454$462 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3423$460 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3393$458 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1474$241 in module StreamFork_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1454$234 in module StreamFork_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1406$231 in module StreamArbiter_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1333$214 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1325$210 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1305$199 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1296$196 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1289$195 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1278$193 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1269$190 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1262$189 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1255$188 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1182$178 in module StreamFork.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1162$171 in module StreamFork.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1114$168 in module StreamArbiter.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1038$150 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1020$132 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1011$129 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1004$128 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:997$126 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:988$123 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:981$122 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:974$121 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:899$111 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:884$110 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:877$109 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:780$106 in module FlowCCByToggle.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:706$99 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:697$97 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:689$96 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:680$95 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:665$87 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:658$86 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:649$84 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:642$83 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:635$82 in module StreamFifoLowLatency.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:553$61 in module UartCtrlRx.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:474$43 in module UartCtrlRx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:461$41 in module UartCtrlRx.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:431$39 in module UartCtrlRx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:260$14 in module UartCtrlTx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:238$13 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:219$11 in module UartCtrlTx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:208$9 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:198$6 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:97$1 in module BufferCC.
|
|
Removed a total of 0 dead cases.
|
|
|
|
2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 30 redundant assignments.
|
|
Promoted 407 assignments to connections.
|
|
|
|
2.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1520'.
|
|
Set init value: \Q = 1'0
|
|
Found init rule in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5582$996'.
|
|
Set init value: \jtag_tap_fsm_state = 4'0000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2167$961'.
|
|
Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2166$960'.
|
|
Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Set init value: \inputArea_target = 1'0
|
|
|
|
2.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
Found async reset \resetCtrl_mainClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8122$1288'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7098$1247'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6976$1210'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6835$1162'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6767$1117'.
|
|
Found async reset \resetCtrl_systemClockReset in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
Found async reset \resetCtrl_mainClockReset in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
Found async reset \resetCtrl_mainClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
Found async reset \resetCtrl_systemClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1406$231'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found async reset \resetCtrl_mainClockReset in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found async reset \resetCtrl_systemClockReset in `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
|
|
2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1520'.
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1516'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1513'.
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
1/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_EN[3:0]$1495
|
|
2/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_DATA[3:0]$1494
|
|
3/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_ADDR[3:0]$1493
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1458'.
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
1/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_EN[3:0]$1439
|
|
2/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_DATA[3:0]$1438
|
|
3/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_ADDR[3:0]$1437
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1435'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8122$1288'.
|
|
1/1: $0\_zz_35_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8118$1287'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
1/16: $0\_zz_34_[3:0]
|
|
2/16: $0\_zz_33_[31:0]
|
|
3/16: $0\_zz_32_[31:0]
|
|
4/16: $0\_zz_31_[0:0]
|
|
5/16: $0\_zz_28_[3:0]
|
|
6/16: $0\_zz_27_[31:0]
|
|
7/16: $0\_zz_26_[31:0]
|
|
8/16: $0\_zz_25_[0:0]
|
|
9/16: $0\_zz_15_[3:0]
|
|
10/16: $0\_zz_14_[31:0]
|
|
11/16: $0\_zz_13_[31:0]
|
|
12/16: $0\_zz_12_[0:0]
|
|
13/16: $0\_zz_9_[3:0]
|
|
14/16: $0\_zz_8_[31:0]
|
|
15/16: $0\_zz_7_[31:0]
|
|
16/16: $0\_zz_6_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
1/4: $0\_zz_30_[0:0]
|
|
2/4: $0\_zz_24_[0:0]
|
|
3/4: $0\_zz_11_[0:0]
|
|
4/4: $0\_zz_5_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8055$1274'.
|
|
1/1: $0\resetCtrl_systemClockReset[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8013$1268'.
|
|
1/1: $1\_zz_22_[3:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7991$1263'.
|
|
1/1: $1\core_externalInterrupt[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7434$1256'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7427$1255'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7281$1252'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7274$1251'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7106$1249'.
|
|
1/2: $0\logic_rspHits_1[0:0]
|
|
2/2: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7098$1247'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7086$1229'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7073$1225'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7060$1221'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7048$1218'.
|
|
1/1: $1\_zz_3_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
1/3: $0\logic_rspHits_2[0:0]
|
|
2/3: $0\logic_rspHits_1[0:0]
|
|
3/3: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6976$1210'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6964$1189'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6951$1185'.
|
|
1/1: $1\io_outputs_2_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6938$1181'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6925$1177'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6910$1174'.
|
|
1/1: $1\_zz_4_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6835$1162'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_DATA[7:0]$1142
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_ADDR[14:0]$1141
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_DATA[7:0]$1145
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_ADDR[14:0]$1144
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_DATA[7:0]$1148
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_ADDR[14:0]$1147
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_DATA[7:0]$1151
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_ADDR[14:0]$1150
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6803$1134'.
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6767$1117'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_DATA[7:0]$1097
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_ADDR[15:0]$1096
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_DATA[7:0]$1100
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_ADDR[15:0]$1099
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_DATA[7:0]$1103
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_ADDR[15:0]$1102
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_DATA[7:0]$1106
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_ADDR[15:0]$1105
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6735$1089'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6697$1084'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
|
|
1/3: $1\_zz_4_[0:0]
|
|
2/3: $1\_zz_3_[31:0]
|
|
3/3: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6624$1082'.
|
|
1/1: $1\io_input_PSLVERROR[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6616$1081'.
|
|
1/1: $1\io_input_PREADY[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6611$1074'.
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
1/9: $0\_zz_2_[127:0] [127:96]
|
|
2/9: $0\_zz_2_[127:0] [95:64]
|
|
3/9: $0\_zz_2_[127:0] [63:32]
|
|
4/9: $0\_zz_2_[127:0] [31:0]
|
|
5/9: $0\_zz_1_[127:0] [95:64]
|
|
6/9: $0\_zz_1_[127:0] [63:32]
|
|
7/9: $0\_zz_1_[127:0] [31:0]
|
|
8/9: $0\_zz_3_[31:0]
|
|
9/9: $0\_zz_1_[127:0] [127:96]
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6486$1056'.
|
|
1/1: $1\io_bus_PRDATA[31:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1053'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6421$1052'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
1/6: $0\bridge_misc_doBreak[0:0]
|
|
2/6: $0\bridge_misc_breakDetected[0:0]
|
|
3/6: $0\bridge_misc_readOverflowError[0:0]
|
|
4/6: $0\bridge_misc_readError[0:0]
|
|
5/6: $0\bridge_interruptCtrl_readIntEnable[0:0]
|
|
6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6341$1046'.
|
|
1/2: $2\_zz_6_[0:0]
|
|
2/2: $1\_zz_6_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6324$1045'.
|
|
1/2: $2\_zz_5_[0:0]
|
|
2/2: $1\_zz_5_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6307$1044'.
|
|
1/2: $2\_zz_4_[0:0]
|
|
2/2: $1\_zz_4_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6290$1043'.
|
|
1/2: $2\_zz_3_[0:0]
|
|
2/2: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6273$1042'.
|
|
1/2: $2\_zz_2_[0:0]
|
|
2/2: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6253$1037'.
|
|
1/2: $2\bridge_read_streamBreaked_ready[0:0]
|
|
2/2: $1\bridge_read_streamBreaked_ready[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6245$1036'.
|
|
1/1: $1\_zz_8_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6238$1035'.
|
|
1/1: $1\bridge_read_streamBreaked_valid[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6218$1034'.
|
|
1/2: $2\_zz_1_[0:0]
|
|
2/2: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6214$1033'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6182$1019'.
|
|
1/9: $2\io_apb_PRDATA[20:15] [5:2]
|
|
2/9: $1\io_apb_PRDATA[9:0] [7:2]
|
|
3/9: $2\io_apb_PRDATA[20:15] [1]
|
|
4/9: $1\io_apb_PRDATA[9:0] [8]
|
|
5/9: $2\io_apb_PRDATA[20:15] [0]
|
|
6/9: $1\io_apb_PRDATA[9:0] [1]
|
|
7/9: $3\io_apb_PRDATA[28:24]
|
|
8/9: $1\io_apb_PRDATA[9:0] [9]
|
|
9/9: $1\io_apb_PRDATA[9:0] [0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:6008$1015'.
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
1/2: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0]
|
|
2/2: $0\state[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5982$1011'.
|
|
1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5968$1009'.
|
|
1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5913$1005'.
|
|
1/2: $0\dispatcher_headerShifter[7:0]
|
|
2/2: $0\dispatcher_dataShifter[66:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
1/3: $0\dispatcher_counter[2:0]
|
|
2/3: $0\dispatcher_headerLoaded[0:0]
|
|
3/3: $0\dispatcher_dataLoaded[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5582$996'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5837$995'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
1/4: $0\jtag_readArea_shifter[33:0]
|
|
2/4: $0\jtag_idcodeArea_shifter[31:0]
|
|
3/4: $0\jtag_tap_instructionShift[3:0]
|
|
4/4: $0\jtag_tap_instruction[3:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
1/3: $0\system_rsp_payload_data[31:0]
|
|
2/3: $0\system_rsp_payload_error[0:0]
|
|
3/3: $0\system_rsp_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5776$984'.
|
|
1/2: $2\jtag_writeArea_source_valid[0:0]
|
|
2/2: $1\jtag_writeArea_source_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5748$981'.
|
|
1/5: $5\jtag_tap_tdoUnbufferd[0:0]
|
|
2/5: $4\jtag_tap_tdoUnbufferd[0:0]
|
|
3/5: $3\jtag_tap_tdoUnbufferd[0:0]
|
|
4/5: $2\jtag_tap_tdoUnbufferd[0:0]
|
|
5/5: $1\jtag_tap_tdoUnbufferd[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5694$964'.
|
|
1/1: $1\_zz_1_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2167$961'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2166$960'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
1/8: $0\DebugPlugin_hardwareBreakpoints_2_valid[0:0]
|
|
2/8: $0\DebugPlugin_hardwareBreakpoints_1_valid[0:0]
|
|
3/8: $0\DebugPlugin_hardwareBreakpoints_0_valid[0:0]
|
|
4/8: $0\DebugPlugin_haltedByBreak[0:0]
|
|
5/8: $0\DebugPlugin_godmode[0:0]
|
|
6/8: $0\DebugPlugin_stepIt[0:0]
|
|
7/8: $0\DebugPlugin_haltIt[0:0]
|
|
8/8: $0\DebugPlugin_resetIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
1/5: $0\DebugPlugin_firstCycle[0:0]
|
|
2/5: $0\DebugPlugin_busReadDataReg[31:0]
|
|
3/5: $0\DebugPlugin_hardwareBreakpoints_2_pc[30:0]
|
|
4/5: $0\DebugPlugin_hardwareBreakpoints_1_pc[30:0]
|
|
5/5: $0\DebugPlugin_hardwareBreakpoints_0_pc[30:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
1/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [32]
|
|
2/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [31:0]
|
|
3/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [64:32]
|
|
4/92: $0\execute_CsrPlugin_csr_2946[0:0]
|
|
5/92: $0\execute_CsrPlugin_csr_2818[0:0]
|
|
6/92: $0\execute_CsrPlugin_csr_2944[0:0]
|
|
7/92: $0\execute_CsrPlugin_csr_2816[0:0]
|
|
8/92: $0\execute_CsrPlugin_csr_834[0:0]
|
|
9/92: $0\execute_CsrPlugin_csr_773[0:0]
|
|
10/92: $0\execute_CsrPlugin_csr_772[0:0]
|
|
11/92: $0\execute_CsrPlugin_csr_836[0:0]
|
|
12/92: $0\execute_CsrPlugin_csr_768[0:0]
|
|
13/92: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
|
|
14/92: $0\decode_to_execute_RS2[31:0]
|
|
15/92: $0\decode_to_execute_BRANCH_CTRL[1:0]
|
|
16/92: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
|
|
17/92: $0\memory_to_writeBack_SRC1[31:0]
|
|
18/92: $0\execute_to_memory_SRC1[31:0]
|
|
19/92: $0\decode_to_execute_SRC1[31:0]
|
|
20/92: $0\decode_to_execute_IS_CSR[0:0]
|
|
21/92: $0\memory_to_writeBack_SRC2[31:0]
|
|
22/92: $0\execute_to_memory_SRC2[31:0]
|
|
23/92: $0\decode_to_execute_SRC2[31:0]
|
|
24/92: $0\execute_to_memory_MUL_LL[31:0]
|
|
25/92: $0\memory_to_writeBack_ENV_CTRL[0:0]
|
|
26/92: $0\execute_to_memory_ENV_CTRL[0:0]
|
|
27/92: $0\decode_to_execute_ENV_CTRL[0:0]
|
|
28/92: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
|
|
29/92: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
|
|
30/92: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
|
|
31/92: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
|
|
32/92: $0\execute_to_memory_MUL_LH[31:0]
|
|
33/92: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
|
|
34/92: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
|
|
35/92: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
|
|
36/92: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
|
|
37/92: $0\memory_to_writeBack_PC[31:0]
|
|
38/92: $0\execute_to_memory_PC[31:0]
|
|
39/92: $0\decode_to_execute_PC[31:0]
|
|
40/92: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
|
|
41/92: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
|
|
42/92: $0\execute_to_memory_BRANCH_DO[0:0]
|
|
43/92: $0\execute_to_memory_SHIFT_CTRL[1:0]
|
|
44/92: $0\decode_to_execute_SHIFT_CTRL[1:0]
|
|
45/92: $0\decode_to_execute_IS_RS2_SIGNED[0:0]
|
|
46/92: $0\memory_to_writeBack_IS_MUL[0:0]
|
|
47/92: $0\execute_to_memory_IS_MUL[0:0]
|
|
48/92: $0\decode_to_execute_IS_MUL[0:0]
|
|
49/92: $0\execute_to_memory_MUL_HL[31:0]
|
|
50/92: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
|
|
51/92: $0\execute_to_memory_MEMORY_ENABLE[0:0]
|
|
52/92: $0\decode_to_execute_MEMORY_ENABLE[0:0]
|
|
53/92: $0\decode_to_execute_ALU_CTRL[1:0]
|
|
54/92: $0\execute_to_memory_INSTRUCTION[31:0]
|
|
55/92: $0\decode_to_execute_INSTRUCTION[31:0]
|
|
56/92: $0\decode_to_execute_DO_EBREAK[0:0]
|
|
57/92: $0\memory_to_writeBack_MEMORY_STORE[0:0]
|
|
58/92: $0\execute_to_memory_MEMORY_STORE[0:0]
|
|
59/92: $0\decode_to_execute_MEMORY_STORE[0:0]
|
|
60/92: $0\memory_to_writeBack_MUL[63:0]
|
|
61/92: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
62/92: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
63/92: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
|
|
64/92: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
|
|
65/92: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
|
|
66/92: $0\decode_to_execute_IS_RS1_SIGNED[0:0]
|
|
67/92: $0\decode_to_execute_RS1[31:0]
|
|
68/92: $0\execute_to_memory_BRANCH_CALC[31:0]
|
|
69/92: $0\execute_to_memory_IS_DIV[0:0]
|
|
70/92: $0\decode_to_execute_IS_DIV[0:0]
|
|
71/92: $0\execute_to_memory_SHIFT_RIGHT[31:0]
|
|
72/92: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
|
|
73/92: $0\execute_to_memory_MUL_HH[31:0]
|
|
74/92: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
|
|
75/92: $0\memory_MulDivIterativePlugin_div_result[31:0]
|
|
76/92: $0\memory_MulDivIterativePlugin_div_done[0:0]
|
|
77/92: $0\memory_MulDivIterativePlugin_div_needRevert[0:0]
|
|
78/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [31:0]
|
|
79/92: $0\memory_MulDivIterativePlugin_rs2[31:0]
|
|
80/92: $0\CsrPlugin_mip_MSIP[0:0]
|
|
81/92: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
82/92: $0\CsrPlugin_interrupt_code[3:0]
|
|
83/92: $0\CsrPlugin_minstret[63:0]
|
|
84/92: $0\CsrPlugin_mcause_exceptionCode[3:0]
|
|
85/92: $0\CsrPlugin_mcause_interrupt[0:0]
|
|
86/92: $0\CsrPlugin_mepc[31:0]
|
|
87/92: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0]
|
|
88/92: $0\_zz_63_[0:0]
|
|
89/92: $0\_zz_62_[31:0]
|
|
90/92: $0\_zz_61_[0:0]
|
|
91/92: $0\_zz_60_[31:0]
|
|
92/92: $0\_zz_58_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
1/38: $0\memory_MulDivIterativePlugin_div_counter_value[5:0]
|
|
2/38: $0\_zz_100_[0:0]
|
|
3/38: $0\_zz_88_[0:0]
|
|
4/38: $0\execute_CsrPlugin_wfiWake[0:0]
|
|
5/38: $0\CsrPlugin_hadException[0:0]
|
|
6/38: $0\CsrPlugin_interrupt_valid[0:0]
|
|
7/38: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0]
|
|
8/38: $0\IBusSimplePlugin_pending_value[2:0]
|
|
9/38: $0\IBusSimplePlugin_fetchPc_booted[0:0]
|
|
10/38: $0\_zz_125_[2:0]
|
|
11/38: $0\memory_to_writeBack_INSTRUCTION[31:0]
|
|
12/38: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
|
|
13/38: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
|
|
14/38: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
|
|
15/38: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
|
|
16/38: $0\CsrPlugin_mie_MSIE[0:0]
|
|
17/38: $0\CsrPlugin_mie_MTIE[0:0]
|
|
18/38: $0\CsrPlugin_mie_MEIE[0:0]
|
|
19/38: $0\CsrPlugin_mstatus_MPP[1:0]
|
|
20/38: $0\CsrPlugin_mstatus_MPIE[0:0]
|
|
21/38: $0\CsrPlugin_mstatus_MIE[0:0]
|
|
22/38: $0\CsrPlugin_mtvec_base[29:0]
|
|
23/38: $0\CsrPlugin_mtvec_mode[1:0]
|
|
24/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0]
|
|
25/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0]
|
|
26/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0]
|
|
27/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0]
|
|
28/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0]
|
|
29/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0]
|
|
30/38: $0\_zz_59_[0:0]
|
|
31/38: $0\_zz_57_[0:0]
|
|
32/38: $0\_zz_55_[0:0]
|
|
33/38: $0\IBusSimplePlugin_fetchPc_inc[0:0]
|
|
34/38: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0]
|
|
35/38: $0\IBusSimplePlugin_fetchPc_pcReg[31:0]
|
|
36/38: $0\writeBack_arbitration_isValid[0:0]
|
|
37/38: $0\memory_arbitration_isValid[0:0]
|
|
38/38: $0\execute_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4846$791'.
|
|
1/1: $1\_zz_134_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4839$790'.
|
|
1/1: $1\_zz_133_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4832$789'.
|
|
1/1: $1\_zz_132_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4825$788'.
|
|
1/1: $1\_zz_131_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$787'.
|
|
1/2: $1\_zz_130_[3:0]
|
|
2/2: $2\_zz_130_[31:31]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4809$786'.
|
|
1/2: $1\_zz_129_[31:0] [31:2]
|
|
2/2: $1\_zz_129_[31:0] [1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4800$785'.
|
|
1/3: $1\_zz_128_[3:3]
|
|
2/3: $2\_zz_128_[7:7]
|
|
3/3: $3\_zz_128_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4791$784'.
|
|
1/3: $1\_zz_127_[3:3]
|
|
2/3: $2\_zz_127_[7:7]
|
|
3/3: $3\_zz_127_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4782$783'.
|
|
1/3: $1\_zz_126_[3:3]
|
|
2/3: $2\_zz_126_[7:7]
|
|
3/3: $3\_zz_126_[12:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4763$782'.
|
|
1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4695$728'.
|
|
1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4684$726'.
|
|
1/5: $1\debug_bus_rsp_data[4:0] [4]
|
|
2/5: $1\debug_bus_rsp_data[4:0] [2]
|
|
3/5: $1\debug_bus_rsp_data[4:0] [1]
|
|
4/5: $1\debug_bus_rsp_data[4:0] [0]
|
|
5/5: $1\debug_bus_rsp_data[4:0] [3]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4661$725'.
|
|
1/3: $3\debug_bus_cmd_ready[0:0]
|
|
2/3: $2\debug_bus_cmd_ready[0:0]
|
|
3/3: $1\debug_bus_cmd_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4656$723'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4637$713'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4628$710'.
|
|
1/1: $1\memory_MulDivIterativePlugin_div_counter_willClear[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4619$709'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4602$704'.
|
|
1/1: $1\writeBack_Mul16Plugin_bSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4588$703'.
|
|
1/1: $1\writeBack_Mul16Plugin_aSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4559$698'.
|
|
1/1: $1\_zz_118_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4537$697'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4513$696'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4498$695'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$692'.
|
|
1/1: $1\_zz_111_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4467$685'.
|
|
1/3: $3\_zz_110_[0:0]
|
|
2/3: $2\_zz_110_[0:0]
|
|
3/3: $1\_zz_110_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4431$676'.
|
|
1/10: $10\_zz_99_[0:0]
|
|
2/10: $9\_zz_99_[0:0]
|
|
3/10: $8\_zz_99_[0:0]
|
|
4/10: $7\_zz_99_[0:0]
|
|
5/10: $6\_zz_99_[0:0]
|
|
6/10: $5\_zz_99_[0:0]
|
|
7/10: $4\_zz_99_[0:0]
|
|
8/10: $3\_zz_99_[0:0]
|
|
9/10: $2\_zz_99_[0:0]
|
|
10/10: $1\_zz_99_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4403$674'.
|
|
1/10: $10\_zz_98_[0:0]
|
|
2/10: $9\_zz_98_[0:0]
|
|
3/10: $8\_zz_98_[0:0]
|
|
4/10: $7\_zz_98_[0:0]
|
|
5/10: $6\_zz_98_[0:0]
|
|
6/10: $5\_zz_98_[0:0]
|
|
7/10: $4\_zz_98_[0:0]
|
|
8/10: $3\_zz_98_[0:0]
|
|
9/10: $2\_zz_98_[0:0]
|
|
10/10: $1\_zz_98_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4368$673'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4332$670'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4323$666'.
|
|
1/1: $1\execute_SrcPlugin_addSub[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4306$665'.
|
|
1/1: $1\_zz_95_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4283$664'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4259$663'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4241$662'.
|
|
1/1: $1\_zz_90_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4227$661'.
|
|
1/1: $1\_zz_89_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4213$657'.
|
|
1/1: $1\execute_IntAluPlugin_bitwise[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4204$655'.
|
|
1/1: $1\lastStageRegFileWrite_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4168$633'.
|
|
1/1: $1\execute_CsrPlugin_writeData[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4154$617'.
|
|
1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
|
|
2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4107$612'.
|
|
1/16: $16\execute_CsrPlugin_illegalAccess[0:0]
|
|
2/16: $15\execute_CsrPlugin_illegalAccess[0:0]
|
|
3/16: $14\execute_CsrPlugin_illegalAccess[0:0]
|
|
4/16: $13\execute_CsrPlugin_illegalAccess[0:0]
|
|
5/16: $12\execute_CsrPlugin_illegalAccess[0:0]
|
|
6/16: $11\execute_CsrPlugin_illegalAccess[0:0]
|
|
7/16: $10\execute_CsrPlugin_illegalAccess[0:0]
|
|
8/16: $9\execute_CsrPlugin_illegalAccess[0:0]
|
|
9/16: $8\execute_CsrPlugin_illegalAccess[0:0]
|
|
10/16: $7\execute_CsrPlugin_illegalAccess[0:0]
|
|
11/16: $6\execute_CsrPlugin_illegalAccess[0:0]
|
|
12/16: $5\execute_CsrPlugin_illegalAccess[0:0]
|
|
13/16: $4\execute_CsrPlugin_illegalAccess[0:0]
|
|
14/16: $3\execute_CsrPlugin_illegalAccess[0:0]
|
|
15/16: $2\execute_CsrPlugin_illegalAccess[0:0]
|
|
16/16: $1\execute_CsrPlugin_illegalAccess[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4094$610'.
|
|
1/1: $1\CsrPlugin_xtvec_base[29:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4083$609'.
|
|
1/1: $1\CsrPlugin_xtvec_mode[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$606'.
|
|
1/1: $1\CsrPlugin_pipelineLiberator_done[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4058$600'.
|
|
1/1: $1\CsrPlugin_privilege[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4044$599'.
|
|
1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4024$598'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3995$595'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3977$592'.
|
|
1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
|
|
2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3961$590'.
|
|
1/1: $1\_zz_67_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3946$589'.
|
|
1/1: $1\_zz_66_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3936$579'.
|
|
1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3912$570'.
|
|
1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3877$558'.
|
|
1/1: $1\decode_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3856$552'.
|
|
1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3830$534'.
|
|
1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3812$528'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3803$526'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$525'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3788$523'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3777$519'.
|
|
1/1: $1\CsrPlugin_allowException[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3770$517'.
|
|
1/1: $1\CsrPlugin_allowInterrupts[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3763$516'.
|
|
1/1: $1\CsrPlugin_forceMachineWire[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3747$515'.
|
|
1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
|
|
2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
|
|
3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$514'.
|
|
1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
|
|
2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3730$513'.
|
|
1/1: $1\CsrPlugin_thirdPartyWake[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3719$511'.
|
|
1/2: $2\IBusSimplePlugin_incomingInstruction[0:0]
|
|
2/2: $1\IBusSimplePlugin_incomingInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3698$510'.
|
|
1/6: $6\IBusSimplePlugin_fetcherHalt[0:0]
|
|
2/6: $5\IBusSimplePlugin_fetcherHalt[0:0]
|
|
3/6: $4\IBusSimplePlugin_fetcherHalt[0:0]
|
|
4/6: $3\IBusSimplePlugin_fetcherHalt[0:0]
|
|
5/6: $2\IBusSimplePlugin_fetcherHalt[0:0]
|
|
6/6: $1\IBusSimplePlugin_fetcherHalt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3684$509'.
|
|
1/2: $2\writeBack_arbitration_flushNext[0:0]
|
|
2/2: $1\writeBack_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3676$508'.
|
|
1/1: $1\writeBack_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3667$507'.
|
|
1/1: $1\memory_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3659$506'.
|
|
1/1: $1\memory_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$496'.
|
|
1/3: $3\memory_arbitration_haltItself[0:0]
|
|
2/3: $2\memory_arbitration_haltItself[0:0]
|
|
3/3: $1\memory_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$495'.
|
|
1/2: $2\execute_arbitration_flushNext[0:0]
|
|
2/2: $1\execute_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3628$494'.
|
|
1/2: $2\execute_arbitration_flushIt[0:0]
|
|
2/2: $1\execute_arbitration_flushIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$493'.
|
|
1/1: $1\execute_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3614$492'.
|
|
1/1: $1\execute_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3602$484'.
|
|
1/3: $3\execute_arbitration_haltItself[0:0]
|
|
2/3: $2\execute_arbitration_haltItself[0:0]
|
|
3/3: $1\execute_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3593$483'.
|
|
1/1: $1\decode_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3580$473'.
|
|
1/3: $3\decode_arbitration_haltByOther[0:0]
|
|
2/3: $2\decode_arbitration_haltByOther[0:0]
|
|
3/3: $1\decode_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3561$472'.
|
|
1/1: $1\decode_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3550$471'.
|
|
1/1: $1\_zz_48_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3522$468'.
|
|
1/3: $3\_zz_47_[31:0]
|
|
2/3: $2\_zz_47_[31:0]
|
|
3/3: $1\_zz_47_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3507$467'.
|
|
1/1: $1\_zz_43_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3500$465'.
|
|
1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3492$463'.
|
|
1/1: $1\_zz_35_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$462'.
|
|
1/3: $3\_zz_23_[31:0]
|
|
2/3: $2\_zz_23_[31:0]
|
|
3/3: $1\_zz_23_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3423$460'.
|
|
1/11: $11\decode_RS1[31:0]
|
|
2/11: $10\decode_RS1[31:0]
|
|
3/11: $9\decode_RS1[31:0]
|
|
4/11: $8\decode_RS1[31:0]
|
|
5/11: $7\decode_RS1[31:0]
|
|
6/11: $6\decode_RS1[31:0]
|
|
7/11: $5\decode_RS1[31:0]
|
|
8/11: $4\decode_RS1[31:0]
|
|
9/11: $3\decode_RS1[31:0]
|
|
10/11: $2\decode_RS1[31:0]
|
|
11/11: $1\decode_RS1[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3393$458'.
|
|
1/11: $11\decode_RS2[31:0]
|
|
2/11: $10\decode_RS2[31:0]
|
|
3/11: $9\decode_RS2[31:0]
|
|
4/11: $8\decode_RS2[31:0]
|
|
5/11: $7\decode_RS2[31:0]
|
|
6/11: $6\decode_RS2[31:0]
|
|
7/11: $5\decode_RS2[31:0]
|
|
8/11: $4\decode_RS2[31:0]
|
|
9/11: $3\decode_RS2[31:0]
|
|
10/11: $2\decode_RS2[31:0]
|
|
11/11: $1\decode_RS2[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
1/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429
|
|
2/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_DATA[31:0]$428
|
|
3/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_ADDR[4:0]$427
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2728$424'.
|
|
1/1: $0\_zz_138_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2722$422'.
|
|
1/1: $0\_zz_137_[31:0]
|
|
Creating decoders for process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1505$244'.
|
|
Creating decoders for process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1454$234'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1419$233'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1406$231'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
1/3: $0\popPtr_value[2:0]
|
|
2/3: $0\pushPtr_value[2:0]
|
|
3/3: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
1/1: $1\io_occupancy[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
1/2: $2\popPtr_valueNext[2:0]
|
|
2/2: $1\popPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
1/2: $2\pushPtr_valueNext[2:0]
|
|
2/2: $1\pushPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
1/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
2/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_DATA[1:0]$186
|
|
3/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_ADDR[2:0]$185
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
1/4: $0\_zz_2_[0:0]
|
|
2/4: $0\logic_popPtr_value[3:0]
|
|
3/4: $0\logic_pushPtr_value[3:0]
|
|
4/4: $0\logic_risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
1/1: $1\logic_popPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
1/1: $1\logic_popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
1/1: $1\logic_popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
1/1: $1\logic_pushPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
1/1: $1\logic_pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
1/1: $1\logic_pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
1/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
2/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA[7:0]$119
|
|
3/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR[3:0]$118
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
1/1: $0\_zz_3_[7:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
1/1: $0\clockDivider_counter[19:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
1/1: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
1/1: $1\io_write_thrown_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
1/1: $0\outputArea_flow_regNext_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
1/3: $0\inputArea_data_fragment[0:0]
|
|
2/3: $0\inputArea_data_last[0:0]
|
|
3/3: $0\inputArea_target[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
1/1: $0\_zz_3_[32:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
1/1: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
1/1: $1\io_pop_payload_inst[31:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
1/1: $1\io_pop_payload_error[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
1/1: $1\io_pop_valid[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
1/9: $2$lookahead\stateMachine_shifter$60[7:0]$74
|
|
2/9: $2$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$73
|
|
3/9: $2$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$72
|
|
4/9: $1$lookahead\stateMachine_shifter$60[7:0]$70
|
|
5/9: $1$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$69
|
|
6/9: $1$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$68
|
|
7/9: $0\bitCounter_value[2:0]
|
|
8/9: $0\bitTimer_counter[2:0]
|
|
9/9: $0\stateMachine_parity[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
1/8: $0\stateMachine_validReg[0:0]
|
|
2/8: $0\sampler_tick[0:0]
|
|
3/8: $0\sampler_value[0:0]
|
|
4/8: $0\_zz_1_[0:0]
|
|
5/8: $0\break_counter[6:0]
|
|
6/8: $0\sampler_samples_2[0:0]
|
|
7/8: $0\sampler_samples_1[0:0]
|
|
8/8: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
1/2: $2\bitTimer_tick[0:0]
|
|
2/2: $1\bitTimer_tick[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
1/5: $5\io_error[0:0]
|
|
2/5: $4\io_error[0:0]
|
|
3/5: $3\io_error[0:0]
|
|
4/5: $2\io_error[0:0]
|
|
5/5: $1\io_error[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
1/2: $0\stateMachine_parity[0:0]
|
|
2/2: $0\tickCounter_value[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
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1/3: $0\_zz_1_[0:0]
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2/3: $0\clockDivider_counter_value[2:0]
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3/3: $0\stateMachine_state[2:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
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1/3: $3\io_write_ready[0:0]
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2/3: $2\io_write_ready[0:0]
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3/3: $1\io_write_ready[0:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
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1/1: $1\stateMachine_txd[0:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
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1/2: $2\clockDivider_counter_valueNext[2:0]
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2/2: $1\clockDivider_counter_valueNext[2:0]
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Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
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1/1: $1\clockDivider_counter_willIncrement[0:0]
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Creating decoders for process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
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Creating decoders for process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
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1/2: $0\buffers_1[0:0]
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2/2: $0\buffers_0[0:0]
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2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
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No latch inferred for signal `\PQVexRiscvUlx3s.\_zz_22_' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8013$1268'.
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No latch inferred for signal `\PQVexRiscvUlx3s.\core_externalInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7991$1263'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_2_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7434$1256'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_2_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7427$1255'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7281$1252'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7274$1251'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7086$1229'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7073$1225'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7060$1221'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\_zz_3_' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7048$1218'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6964$1189'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_2_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6951$1185'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6938$1181'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6925$1177'.
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|
No latch inferred for signal `\PipelinedMemoryBusDecoder.\_zz_4_' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6910$1174'.
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|
No latch inferred for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6803$1134'.
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No latch inferred for signal `\PipelinedMemoryBusRamUlx3s.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6735$1089'.
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No latch inferred for signal `\Apb3Router.\_zz_2_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
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No latch inferred for signal `\Apb3Router.\_zz_3_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
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No latch inferred for signal `\Apb3Router.\_zz_4_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
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No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6624$1082'.
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No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6616$1081'.
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No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6611$1074'.
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|
No latch inferred for signal `\MyMem.\io_bus_PRDATA' from process `\MyMem.$proc$PQVexRiscvUlx3s.v:6486$1056'.
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|
No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6213$1016$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1053'.
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No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6213$1017$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1053'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_6_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6341$1046'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_5_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6324$1045'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_4_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6307$1044'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_3_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6290$1043'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_2_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6273$1042'.
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|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6253$1037'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_8_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6245$1036'.
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|
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6238$1035'.
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|
No latch inferred for signal `\Apb3UartCtrl.\_zz_1_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6218$1034'.
|
|
No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6214$1033'.
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|
No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6182$1019'.
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|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5982$1011'.
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|
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5968$1009'.
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|
No latch inferred for signal `\JtagBridge.\jtag_writeArea_source_valid' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5776$984'.
|
|
No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5748$981'.
|
|
No latch inferred for signal `\JtagBridge.\_zz_1_' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5694$964'.
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|
No latch inferred for signal `\VexRiscv.\_zz_134_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4846$791'.
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|
No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4839$790'.
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|
No latch inferred for signal `\VexRiscv.\_zz_132_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4832$789'.
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|
No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4825$788'.
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|
No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$787'.
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|
No latch inferred for signal `\VexRiscv.\_zz_129_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4809$786'.
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|
No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4800$785'.
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|
No latch inferred for signal `\VexRiscv.\_zz_127_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4791$784'.
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|
No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4782$783'.
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|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4763$782'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4695$728'.
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|
No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4684$726'.
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No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4661$725'.
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No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4656$723'.
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|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_valueNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4637$713'.
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|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willClear' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4628$710'.
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|
No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4619$709'.
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|
No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_bSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4602$704'.
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No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_aSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4588$703'.
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|
No latch inferred for signal `\VexRiscv.\_zz_118_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4559$698'.
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|
No latch inferred for signal `\VexRiscv.\_zz_117_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4537$697'.
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|
No latch inferred for signal `\VexRiscv.\_zz_115_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4513$696'.
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|
No latch inferred for signal `\VexRiscv.\_zz_113_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4498$695'.
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|
No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$692'.
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|
No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4467$685'.
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|
No latch inferred for signal `\VexRiscv.\_zz_99_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4431$676'.
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|
No latch inferred for signal `\VexRiscv.\_zz_98_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4403$674'.
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|
No latch inferred for signal `\VexRiscv.\_zz_97_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4368$673'.
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|
No latch inferred for signal `\VexRiscv.\_zz_96_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4332$670'.
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|
No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4323$666'.
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|
No latch inferred for signal `\VexRiscv.\_zz_95_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4306$665'.
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|
No latch inferred for signal `\VexRiscv.\_zz_94_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4283$664'.
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|
No latch inferred for signal `\VexRiscv.\_zz_92_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4259$663'.
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|
No latch inferred for signal `\VexRiscv.\_zz_90_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4241$662'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_89_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4227$661'.
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|
No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4213$657'.
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|
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4204$655'.
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|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4168$633'.
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|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4154$617'.
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|
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4107$612'.
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|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4094$610'.
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|
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4083$609'.
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|
No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$606'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4058$600'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4044$599'.
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No latch inferred for signal `\VexRiscv.\_zz_71_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4024$598'.
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|
No latch inferred for signal `\VexRiscv.\_zz_69_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3995$595'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3977$592'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_67_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3961$590'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_66_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3946$589'.
|
|
No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3936$579'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3912$570'.
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|
No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3877$558'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3856$552'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3830$534'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3812$528'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3803$526'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$525'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3788$523'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3777$519'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3770$517'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3763$516'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3747$515'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$514'.
|
|
No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3730$513'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3719$511'.
|
|
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3698$510'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3684$509'.
|
|
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3676$508'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3667$507'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3659$506'.
|
|
No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$496'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$495'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3628$494'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$493'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3614$492'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3602$484'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3593$483'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3580$473'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3561$472'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_48_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3550$471'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_47_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3522$468'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_43_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3507$467'.
|
|
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3500$465'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_35_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3492$463'.
|
|
No latch inferred for signal `\VexRiscv.\_zz_23_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$462'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3423$460'.
|
|
No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3393$458'.
|
|
No latch inferred for signal `\StreamFork_1_.\io_input_ready' from process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1454$234'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\io_occupancy' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\_zz_1_' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
No latch inferred for signal `\StreamFork.\io_input_ready' from process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
No latch inferred for signal `\StreamFifo.\_zz_1_' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\_zz_1_' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
|
|
2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1516'.
|
|
created $dff cell `$procdff$3779' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1513'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
created $dff cell `$procdff$3780' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
created $dff cell `$procdff$3781' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1491_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
created $dff cell `$procdff$3782' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1458'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
created $dff cell `$procdff$3783' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
created $dff cell `$procdff$3784' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1434_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
created $dff cell `$procdff$3785' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1435'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_35_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8122$1288'.
|
|
created $adff cell `$procdff$3786' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\core_cpu_debug_resetOut_regNext' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8118$1287'.
|
|
created $dff cell `$procdff$3787' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_6_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3788' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_7_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3789' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_8_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3790' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_9_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3791' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_12_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3792' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_13_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3793' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_14_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3794' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_15_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3795' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_25_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3796' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_26_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3797' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_27_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3798' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_28_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3799' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_31_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3800' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_32_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3801' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_33_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3802' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_34_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
created $dff cell `$procdff$3803' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_5_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
created $adff cell `$procdff$3804' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_11_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
created $adff cell `$procdff$3805' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_24_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
created $adff cell `$procdff$3806' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_30_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
created $adff cell `$procdff$3807' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_systemClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8055$1274'.
|
|
created $dff cell `$procdff$3808' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_mainClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8055$1274'.
|
|
created $dff cell `$procdff$3809' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7106$1249'.
|
|
created $dff cell `$procdff$3810' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7106$1249'.
|
|
created $dff cell `$procdff$3811' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7098$1247'.
|
|
created $adff cell `$procdff$3812' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
created $dff cell `$procdff$3813' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
created $dff cell `$procdff$3814' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_2' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
created $dff cell `$procdff$3815' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6976$1210'.
|
|
created $adff cell `$procdff$3816' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6835$1162'.
|
|
created $adff cell `$procdff$3817' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3818' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3819' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3820' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3821' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3822' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3823' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3824' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3825' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3826' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3827' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3828' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
created $dff cell `$procdff$3829' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
created $dff cell `$procdff$3830' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
created $dff cell `$procdff$3831' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
created $dff cell `$procdff$3832' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
created $dff cell `$procdff$3833' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6767$1117'.
|
|
created $adff cell `$procdff$3834' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3835' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3836' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3837' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3838' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3839' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3840' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3841' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3842' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3843' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3844' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3845' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
created $dff cell `$procdff$3846' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
created $dff cell `$procdff$3847' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
created $dff cell `$procdff$3848' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
created $dff cell `$procdff$3849' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
created $dff cell `$procdff$3850' with positive edge clock.
|
|
Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6697$1084'.
|
|
created $dff cell `$procdff$3851' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_2_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
created $dff cell `$procdff$3852' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_3_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
created $dff cell `$procdff$3853' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_1_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
created $dff cell `$procdff$3854' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\uartCtrl_1__io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6421$1052'.
|
|
created $dff cell `$procdff$3855' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3856' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3857' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3858' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3859' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3860' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
created $adff cell `$procdff$3861' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:6008$1015'.
|
|
created $dff cell `$procdff$3862' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
created $adff cell `$procdff$3863' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
created $adff cell `$procdff$3864' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5913$1005'.
|
|
created $dff cell `$procdff$3865' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5913$1005'.
|
|
created $dff cell `$procdff$3866' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
created $adff cell `$procdff$3867' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
created $adff cell `$procdff$3868' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
created $adff cell `$procdff$3869' with positive edge clock and positive level reset.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5837$995'.
|
|
created $dff cell `$procdff$3870' with negative edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3871' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3872' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3873' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3874' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3875' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_readArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
created $dff cell `$procdff$3876' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
created $dff cell `$procdff$3877' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
created $dff cell `$procdff$3878' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
created $dff cell `$procdff$3879' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3880' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3881' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3882' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3883' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3884' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3885' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3886' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
created $adff cell `$procdff$3887' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3888' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3889' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3890' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3891' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3892' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3893' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3894' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_124_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3895' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
created $dff cell `$procdff$3896' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_58_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3897' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_60_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3898' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_61_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3899' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_62_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3900' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_63_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3901' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3902' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3903' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3904' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3905' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3906' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3907' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3908' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3909' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3910' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3911' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3912' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3913' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_102_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3914' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3915' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3916' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_accumulator' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3917' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_needRevert' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3918' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_done' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3919' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_result' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3920' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3921' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3922' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3923' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3924' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3925' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3926' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3927' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3928' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3929' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3930' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3931' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3932' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3933' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3934' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3935' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3936' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3937' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3938' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3939' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3940' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3941' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3942' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3943' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3944' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3945' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3946' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3947' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3948' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3949' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3950' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3951' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3952' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3953' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3954' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3955' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3956' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3957' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3958' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3959' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3960' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3961' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3962' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3963' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3964' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3965' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3966' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3967' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3968' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3969' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3970' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3971' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3972' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3973' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3974' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3975' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3976' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3977' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3978' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3979' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3980' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3981' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3982' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3983' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3984' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3985' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3986' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3987' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2816' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3988' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2944' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3989' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2818' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3990' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2946' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
created $dff cell `$procdff$3991' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3992' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3993' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3994' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3995' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3996' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3997' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3998' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_55_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$3999' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_57_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4000' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_59_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4001' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4002' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4003' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4004' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4005' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4006' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4007' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4008' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4009' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4010' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4011' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4012' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4013' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4014' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4015' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4016' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4017' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4018' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4019' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4020' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4021' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4022' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4023' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_88_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4024' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_100_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4025' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4026' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4027' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4028' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_125_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
created $adff cell `$procdff$4029' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_ADDR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
created $dff cell `$procdff$4030' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
created $dff cell `$procdff$4031' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
created $dff cell `$procdff$4032' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_138_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2728$424'.
|
|
created $dff cell `$procdff$4033' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_137_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2722$422'.
|
|
created $dff cell `$procdff$4034' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_0' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1505$244'.
|
|
created $dff cell `$procdff$4035' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_1' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1505$244'.
|
|
created $dff cell `$procdff$4036' with positive edge clock.
|
|
Creating register for signal `\StreamFork_1_.\_zz_2_' using process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
created $adff cell `$procdff$4037' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork_1_.\_zz_1_' using process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
created $adff cell `$procdff$4038' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter_1_.\maskLocked_0' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1419$233'.
|
|
created $dff cell `$procdff$4039' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter_1_.\maskLocked_1' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1419$233'.
|
|
created $dff cell `$procdff$4040' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter_1_.\locked' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1406$231'.
|
|
created $adff cell `$procdff$4041' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\risingOccupancy' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$4042' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\pushPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$4043' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\popPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
created $adff cell `$procdff$4044' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_ADDR' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$4045' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_DATA' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$4046' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
created $dff cell `$procdff$4047' with positive edge clock.
|
|
Creating register for signal `\StreamFork.\_zz_2_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
created $adff cell `$procdff$4048' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork.\_zz_1_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
created $adff cell `$procdff$4049' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_0' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
created $dff cell `$procdff$4050' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_1' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
created $dff cell `$procdff$4051' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\locked' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
created $adff cell `$procdff$4052' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\_zz_2_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4053' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4054' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4055' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
created $adff cell `$procdff$4056' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4057' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4058' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
created $dff cell `$procdff$4059' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.\_zz_3_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
created $dff cell `$procdff$4060' with positive edge clock.
|
|
Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
created $adff cell `$procdff$4061' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_valid' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
created $adff cell `$procdff$4062' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4063' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4064' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
created $dff cell `$procdff$4065' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4066' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4067' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
created $dff cell `$procdff$4068' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\_zz_3_' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
created $dff cell `$procdff$4069' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
created $adff cell `$procdff$4070' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4071' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4072' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4073' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4074' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4075' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$data$PQVexRiscvUlx3s.v:580$28' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4076' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$60' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
created $dff cell `$procdff$4077' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4078' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\_zz_1_' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4079' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4080' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4081' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4082' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4083' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4084' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
created $adff cell `$procdff$4085' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$4086' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
created $dff cell `$procdff$4087' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4088' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4089' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\_zz_1_' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
created $adff cell `$procdff$4090' with positive edge clock and positive level reset.
|
|
Creating register for signal `\BufferCC_1_.\buffers_0' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$4091' with positive edge clock.
|
|
Creating register for signal `\BufferCC_1_.\buffers_1' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
created $dff cell `$procdff$4092' with positive edge clock.
|
|
Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$4093' with positive edge clock and positive level non-const reset.
|
|
Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$4100' with positive edge clock and positive level non-const reset.
|
|
|
|
2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1520'.
|
|
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1516'.
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1516'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1513'.
|
|
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1492'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1458'.
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1436'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1435'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8122$1288'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8118$1287'.
|
|
Found and cleaned up 4 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8091$1278'.
|
|
Found and cleaned up 6 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8063$1275'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8055$1274'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8055$1274'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8013$1268'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8013$1268'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7991$1263'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:7991$1263'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7434$1256'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7434$1256'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7427$1255'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:7427$1255'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7281$1252'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7281$1252'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7274$1251'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7274$1251'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7106$1249'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7106$1249'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7098$1247'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7086$1229'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7086$1229'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7073$1225'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7073$1225'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7060$1221'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7060$1221'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7048$1218'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7048$1218'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6984$1212'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6976$1210'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6964$1189'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6964$1189'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6951$1185'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6951$1185'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6938$1181'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6938$1181'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6925$1177'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6925$1177'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6910$1174'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:6910$1174'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6835$1162'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6815$1140'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6806$1135'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:6803$1134'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6767$1117'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6747$1095'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6738$1090'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:6735$1089'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6697$1084'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6668$1083'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6624$1082'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6624$1082'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6616$1081'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6616$1081'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6611$1074'.
|
|
Found and cleaned up 11 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6527$1069'.
|
|
Found and cleaned up 1 empty switch in `\MyMem.$proc$PQVexRiscvUlx3s.v:6486$1056'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6486$1056'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1053'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6421$1052'.
|
|
Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6361$1047'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6341$1046'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6341$1046'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6324$1045'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6324$1045'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6307$1044'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6307$1044'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6290$1043'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6290$1043'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6273$1042'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6273$1042'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6253$1037'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6253$1037'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6245$1036'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6245$1036'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6238$1035'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6238$1035'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6218$1034'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6218$1034'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6214$1033'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6182$1019'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6182$1019'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:6008$1015'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5992$1014'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5982$1011'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5982$1011'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5968$1009'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5968$1009'.
|
|
Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5913$1005'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5913$1005'.
|
|
Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5887$1001'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5582$996'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5837$995'.
|
|
Found and cleaned up 7 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5802$989'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5791$987'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5776$984'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5776$984'.
|
|
Found and cleaned up 5 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5748$981'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5748$981'.
|
|
Found and cleaned up 1 empty switch in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5694$964'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5694$964'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2167$961'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2166$960'.
|
|
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5470$956'.
|
|
Found and cleaned up 8 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5428$953'.
|
|
Found and cleaned up 90 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5117$850'.
|
|
Found and cleaned up 61 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4855$800'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4846$791'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4846$791'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4839$790'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4839$790'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4832$789'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4832$789'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4825$788'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4825$788'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$787'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$787'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4809$786'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4809$786'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4800$785'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4800$785'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4791$784'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4791$784'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4782$783'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4782$783'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4763$782'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4763$782'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4695$728'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4695$728'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4684$726'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4684$726'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4661$725'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4661$725'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4656$723'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4637$713'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4637$713'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4628$710'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4628$710'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4619$709'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4619$709'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4602$704'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4602$704'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4588$703'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4588$703'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4559$698'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4559$698'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4537$697'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4513$696'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4498$695'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$692'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4479$692'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4467$685'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4467$685'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4431$676'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4431$676'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4403$674'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4403$674'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4368$673'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4332$670'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4323$666'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4323$666'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4306$665'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4306$665'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4283$664'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4259$663'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4241$662'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4241$662'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4227$661'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4227$661'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4213$657'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4213$657'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4204$655'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4204$655'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4168$633'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4168$633'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4154$617'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4154$617'.
|
|
Found and cleaned up 16 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4107$612'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4107$612'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4094$610'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4094$610'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4083$609'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4083$609'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$606'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4073$606'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4058$600'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4058$600'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4044$599'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4044$599'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4024$598'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3995$595'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3977$592'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3977$592'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3961$590'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3961$590'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3946$589'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3946$589'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3936$579'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3936$579'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3912$570'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3912$570'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3877$558'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3877$558'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3856$552'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3856$552'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3830$534'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3830$534'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3812$528'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3812$528'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3803$526'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3803$526'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$525'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3796$525'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3788$523'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3788$523'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3777$519'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3777$519'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3770$517'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3770$517'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3763$516'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3763$516'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3747$515'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3747$515'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$514'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3737$514'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3730$513'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3730$513'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3719$511'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3719$511'.
|
|
Found and cleaned up 6 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3698$510'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3698$510'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3684$509'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3684$509'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3676$508'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3676$508'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3667$507'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3667$507'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3659$506'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3659$506'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$496'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$496'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$495'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3637$495'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3628$494'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3628$494'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$493'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$493'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3614$492'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3614$492'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3602$484'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3602$484'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3593$483'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3593$483'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3580$473'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3580$473'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3561$472'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3561$472'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3550$471'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3550$471'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3522$468'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3522$468'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3507$467'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3507$467'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3500$465'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3500$465'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3492$463'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3492$463'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$462'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$462'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3423$460'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3423$460'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3393$458'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3393$458'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2734$426'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2728$424'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2728$424'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2722$422'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2722$422'.
|
|
Removing empty process `BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1505$244'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
Removing empty process `StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1474$241'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1454$234'.
|
|
Removing empty process `StreamFork_1_.$proc$PQVexRiscvUlx3s.v:1454$234'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1419$233'.
|
|
Removing empty process `StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1419$233'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1406$231'.
|
|
Removing empty process `StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:1406$231'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1333$214'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1325$210'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1305$199'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1296$196'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1289$195'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1278$193'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1269$190'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1262$189'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1255$188'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1249$184'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1182$178'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1162$171'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1127$170'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1114$168'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'.
|
|
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'.
|
|
Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'.
|
|
Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'.
|
|
Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'.
|
|
Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'.
|
|
Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'.
|
|
Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'.
|
|
Removing empty process `BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'.
|
|
Removing empty process `BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'.
|
|
Cleaned up 572 empty switches.
|
|
|
|
2.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module PipelinedMemoryBusArbiter_2_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter_1_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter.
|
|
Deleting now unused module PipelinedMemoryBusDecoder_1_.
|
|
Deleting now unused module PipelinedMemoryBusDecoder.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s_1_.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s.
|
|
Deleting now unused module Apb3Router.
|
|
Deleting now unused module Apb3Decoder.
|
|
Deleting now unused module MyMem.
|
|
Deleting now unused module Apb3UartCtrl.
|
|
Deleting now unused module PipelinedMemoryBusToApbBridge.
|
|
Deleting now unused module SystemDebugger.
|
|
Deleting now unused module JtagBridge.
|
|
Deleting now unused module VexRiscv.
|
|
Deleting now unused module BufferCC_2_.
|
|
Deleting now unused module StreamFork_1_.
|
|
Deleting now unused module StreamArbiter_1_.
|
|
Deleting now unused module StreamFifoLowLatency_1_.
|
|
Deleting now unused module StreamFork.
|
|
Deleting now unused module StreamArbiter.
|
|
Deleting now unused module StreamFifo.
|
|
Deleting now unused module UartCtrl.
|
|
Deleting now unused module FlowCCByToggle.
|
|
Deleting now unused module StreamFifoLowLatency.
|
|
Deleting now unused module UartCtrlRx.
|
|
Deleting now unused module UartCtrlTx.
|
|
Deleting now unused module BufferCC_1_.
|
|
Deleting now unused module BufferCC.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.6. Executing TRIBUF pass.
|
|
|
|
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
2.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~452 debug messages>
|
|
|
|
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 293 unused cells and 2618 unused wires.
|
|
<suppressed ~380 debug messages>
|
|
|
|
2.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~453 debug messages>
|
|
Removed a total of 151 cells.
|
|
|
|
2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $flatten\systemDebugger_1_.$procmux$2005: \systemDebugger_1_.dispatcher_headerLoaded -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\systemDebugger_1_.$procmux$2003: \systemDebugger_1_.dispatcher_headerLoaded -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3527.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1851.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3652.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3661.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3664.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3664.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3664.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3664.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3673.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3673.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3673.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3673.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1860.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3683.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3685.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3691.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1869.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1878.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3752.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3759.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1887.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1898.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1917.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2666.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2668.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2677.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2705.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2707.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2716.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2734.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2760.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2763.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2769.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2782.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2784.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2790.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2800.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2802.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2808.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2826.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2839.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2841.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2847.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$2857.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2859.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2865.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$2883.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3064.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3097.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3127.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3139.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3148.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3163.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3195.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3220.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3230.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3232.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3238.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3248.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3250.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3256.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3268.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3274.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3283.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3293.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3295.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3301.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3311.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3313.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3319.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3331.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3337.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3346.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2051.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2060.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2069.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$1973.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$1982.
|
|
Removed 79 multiplexer ports.
|
|
<suppressed ~421 debug messages>
|
|
|
|
2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3694: { $auto$opt_reduce.cc:134:opt_mux$4108 $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP }
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3470:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2744: $auto$opt_reduce.cc:134:opt_mux$4110
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2752: { $flatten\core_cpu.$procmux$2755_CMP $auto$opt_reduce.cc:134:opt_mux$4112 }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2829: { }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2886: { }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3027: $auto$opt_reduce.cc:134:opt_mux$4114
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3351:
|
|
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429
|
|
New ports: A=1'0, B=1'1, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0]
|
|
New connections: $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [31:1] = { $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN[31:0]$429 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3470:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1673:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN[7:0]$1098 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1679:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN[7:0]$1101 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1685:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN[7:0]$1104 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1691:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0]
|
|
New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN[7:0]$1107 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3417:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
New connections: $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [1] = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1641:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN[7:0]$1143 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1647:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN[7:0]$1146 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1653:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN[7:0]$1149 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1659:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0]
|
|
New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN[7:0]$1152 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3417:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187
|
|
New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
New connections: $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [1] = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN[1:0]$187 [0]
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 19 changes.
|
|
|
|
2.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~81 debug messages>
|
|
Removed a total of 27 cells.
|
|
|
|
2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$4022 ($adff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$3905 ($dff) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4100 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4093 ($dffsr) from module PQVexRiscvUlx3s.
|
|
|
|
2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 273 unused wires.
|
|
<suppressed ~40 debug messages>
|
|
|
|
2.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~8 debug messages>
|
|
|
|
2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~405 debug messages>
|
|
|
|
2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3560: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3528_CMP $auto$opt_reduce.cc:134:opt_mux$4116 }
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3711: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3717_CMP $auto$opt_reduce.cc:134:opt_mux$4118 }
|
|
New ctrl vector for $pmux cell $flatten\jtagBridge_1_.$procmux$2079: { $flatten\jtagBridge_1_.$procmux$2093_CMP $auto$opt_reduce.cc:134:opt_mux$4124 $flatten\jtagBridge_1_.$procmux$2090_CMP $flatten\jtagBridge_1_.$procmux$2089_CMP $flatten\jtagBridge_1_.$procmux$2088_CMP $flatten\jtagBridge_1_.$procmux$2086_CMP $auto$opt_reduce.cc:134:opt_mux$4122 $flatten\jtagBridge_1_.$procmux$2083_CMP $flatten\jtagBridge_1_.$procmux$2082_CMP $flatten\jtagBridge_1_.$procmux$2081_CMP $auto$opt_reduce.cc:134:opt_mux$4120 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 3 changes.
|
|
|
|
2.11.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 4 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.11.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~405 debug messages>
|
|
|
|
2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.11.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.11.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2736$245_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1251$181_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_8_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_9_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state.
|
|
Not marking PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_code as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_targetPrivilege.
|
|
Not marking PQVexRiscvUlx3s.core_cpu._zz_125_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.jtagBridge_1_.jtag_tap_fsm_state as FSM state register:
|
|
Register has an initialization value.
|
|
|
|
2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4078
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3528_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3570_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3582_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
found state code: 3'010
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
found state code: 3'001
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3582_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3570_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3528_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3528_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3570_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3582_CMP }
|
|
transition: 3'000 6'-0---- -> 3'000 7'0000001
|
|
transition: 3'000 6'-1---- -> 3'001 7'0010001
|
|
transition: 3'100 6'----0- -> 3'100 7'1000000
|
|
transition: 3'100 6'---01- -> 3'000 7'0000000
|
|
transition: 3'100 6'---110 -> 3'100 7'1000000
|
|
transition: 3'100 6'---111 -> 3'000 7'0000000
|
|
transition: 3'010 6'----0- -> 3'010 7'0101000
|
|
transition: 3'010 6'--0-1- -> 3'010 7'0101000
|
|
transition: 3'010 6'--1-1- -> 3'100 7'1001000
|
|
transition: 3'001 6'----0- -> 3'001 7'0010010
|
|
transition: 3'001 6'---01- -> 3'010 7'0100010
|
|
transition: 3'001 6'---11- -> 3'000 7'0000010
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procdff$4089
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3712_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3717_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3706_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3743_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
found state code: 3'001
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
found state code: 3'010
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3743_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3717_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3712_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3706_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3706_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3712_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3717_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3743_CMP }
|
|
transition: 3'000 5'---0- -> 3'000 7'0000001
|
|
transition: 3'000 5'---1- -> 3'001 7'0010001
|
|
transition: 3'100 5'--0-- -> 3'100 7'1000000
|
|
transition: 3'100 5'--1-0 -> 3'100 7'1000000
|
|
transition: 3'100 5'0-1-1 -> 3'000 7'0000000
|
|
transition: 3'100 5'1-1-1 -> 3'001 7'0010000
|
|
transition: 3'010 5'--0-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-01-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-11-- -> 3'100 7'1000010
|
|
transition: 3'001 5'--0-- -> 3'001 7'0011000
|
|
transition: 3'001 5'--1-- -> 3'010 7'0101000
|
|
Extracting FSM `\core_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\PQVexRiscvUlx3s'.
|
|
found $dff cell for state register: $flatten\core_cpu.$procdff$3912
|
|
root of input selection tree: $flatten\core_cpu.$0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
found ctrl input: \core_cpu.CsrPlugin_mstatus_MIE
|
|
found ctrl input: \core_cpu._zz_164_
|
|
found ctrl input: \core_cpu._zz_163_
|
|
found state code: 2'11
|
|
fsm extraction failed: at least two states are required.
|
|
|
|
2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131' from module `\PQVexRiscvUlx3s'.
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused input signal \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_.
|
|
|
|
2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 30 unused cells and 30 unused wires.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [2].
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3743_CMP.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [2].
|
|
|
|
2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
|
|
2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125 (\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y
|
|
1: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3582_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3570_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP
|
|
3: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3528_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'0---- -> 0 4'0001
|
|
1: 0 5'1---- -> 3 4'0001
|
|
2: 1 5'--111 -> 0 4'0000
|
|
3: 1 5'--01- -> 0 4'0000
|
|
4: 1 5'--110 -> 1 4'0000
|
|
5: 1 5'---0- -> 1 4'0000
|
|
6: 2 5'-1-1- -> 1 4'1000
|
|
7: 2 5'---0- -> 2 4'1000
|
|
8: 2 5'-0-1- -> 2 4'1000
|
|
9: 3 5'--11- -> 0 4'0010
|
|
10: 3 5'--01- -> 2 4'0010
|
|
11: 3 5'---0- -> 3 4'0010
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131 (\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 3
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3717_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3712_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3706_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'---0- -> 0 3'000
|
|
1: 0 5'---1- -> 3 3'000
|
|
2: 1 5'0-1-1 -> 0 3'000
|
|
3: 1 5'--1-0 -> 1 3'000
|
|
4: 1 5'--0-- -> 1 3'000
|
|
5: 1 5'1-1-1 -> 3 3'000
|
|
6: 2 5'-11-- -> 1 3'001
|
|
7: 2 5'--0-- -> 2 3'001
|
|
8: 2 5'-01-- -> 2 3'001
|
|
9: 3 5'--1-- -> 2 3'100
|
|
10: 3 5'--0-- -> 3 3'100
|
|
|
|
-------------------------------------
|
|
|
|
2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4125' from module `\PQVexRiscvUlx3s'.
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4131' from module `\PQVexRiscvUlx3s'.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~13 debug messages>
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3596.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3596.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3598.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3681.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3681.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3689.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3689.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3694.
|
|
dead port 1/4 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3766.
|
|
Removed 11 multiplexer ports.
|
|
<suppressed ~403 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$3808 ($dff) from module PQVexRiscvUlx3s (D = \asyncReset_buffercc.buffers_1, Q = \resetCtrl_systemClockReset, rval = 1'1).
|
|
Adding EN signal on $procdff$3807 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8086$1277_Y, Q = \_zz_30_).
|
|
Adding EN signal on $procdff$3806 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_24_[0:0], Q = \_zz_24_).
|
|
Adding EN signal on $procdff$3805 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8077$1276_Y, Q = \_zz_11_).
|
|
Adding EN signal on $procdff$3804 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_5_[0:0], Q = \_zz_5_).
|
|
Adding EN signal on $procdff$3803 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8114$1286_Y, Q = \_zz_34_).
|
|
Adding EN signal on $procdff$3802 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8113$1285_Y, Q = \_zz_33_).
|
|
Adding EN signal on $procdff$3801 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8112$1284_Y, Q = \_zz_32_).
|
|
Adding EN signal on $procdff$3800 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8111$1283_Y, Q = \_zz_31_).
|
|
Adding EN signal on $procdff$3799 ($dff) from module PQVexRiscvUlx3s (D = \_zz_21_, Q = \_zz_28_).
|
|
Adding EN signal on $procdff$3798 ($dff) from module PQVexRiscvUlx3s (D = \_zz_20_, Q = \_zz_27_).
|
|
Adding EN signal on $procdff$3797 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB, Q = \_zz_26_).
|
|
Adding EN signal on $procdff$3796 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \_zz_25_).
|
|
Adding EN signal on $procdff$3795 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8102$1282_Y, Q = \_zz_15_).
|
|
Adding EN signal on $procdff$3794 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8101$1281_Y, Q = \_zz_14_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4263 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_8_, Q = \_zz_14_, rval = 0).
|
|
Adding EN signal on $procdff$3793 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8100$1280_Y, Q = \_zz_13_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4265 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_7_ [1:0], Q = \_zz_13_ [1:0], rval = 2'00).
|
|
Adding EN signal on $procdff$3792 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8099$1279_Y, Q = \_zz_12_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4267 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_6_, Q = \_zz_12_, rval = 1'0).
|
|
Adding EN signal on $procdff$3791 ($dff) from module PQVexRiscvUlx3s (D = 4'xxxx, Q = \_zz_9_).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4269 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4269 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4269 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4269 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3790 ($dff) from module PQVexRiscvUlx3s (D = 0, Q = \_zz_8_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4270 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3789 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, Q = \_zz_7_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4271 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4271 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$3788 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \_zz_6_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4272 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3869 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$procmux$1999_Y, Q = \systemDebugger_1_.dispatcher_counter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3868 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_headerLoaded[0:0], Q = \systemDebugger_1_.dispatcher_headerLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3867 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_dataLoaded[0:0], Q = \systemDebugger_1_.dispatcher_dataLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3866 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_headerShifter [7:1] }, Q = \systemDebugger_1_.dispatcher_headerShifter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$3865 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_dataShifter [66:1] }, Q = \systemDebugger_1_.dispatcher_dataShifter).
|
|
Adding SRST signal on $flatten\pipelinedMemoryBusToApbBridge_1_.$procdff$3862 ($dff) from module PQVexRiscvUlx3s (D = { \apb3Router_1_.io_outputs_1_PRDATA [31:29] \apb3Router_1_.io_outputs_1_PRDATA [23:21] \apb3Router_1_.io_outputs_1_PRDATA [14:10] }, Q = { \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [31:29] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [23:21] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [14:10] }, rval = 11'00000000000).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [31:0]).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [63:32]).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [95:64]).
|
|
Adding EN signal on $flatten\myMem_1_.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [127:96]).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4042 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4038 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4037 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4041 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4040 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4039 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3833 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6811$1139_DATA, Q = \memory_ramBlocks_1._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3832 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6810$1138_DATA, Q = \memory_ramBlocks_1._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3831 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6809$1137_DATA, Q = \memory_ramBlocks_1._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3830 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6808$1136_DATA, Q = \memory_ramBlocks_1._zz_5_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4042 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4049 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_1_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4048 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_2_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4052 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.locked).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4051 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_1).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4050 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_0).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3850 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6743$1094_DATA, Q = \memory_ramBlocks_0._zz_8_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3849 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6742$1093_DATA, Q = \memory_ramBlocks_0._zz_7_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3848 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6741$1092_DATA, Q = \memory_ramBlocks_0._zz_6_).
|
|
Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3847 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6740$1091_DATA, Q = \memory_ramBlocks_0._zz_5_).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4068 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tdi, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_fragment).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4067 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tms, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_last).
|
|
Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4066 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.\flowCCByToggle_1_.$logic_not$PQVexRiscvUlx3s.v:768$104_Y, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_target).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3879 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.DebugPlugin_busReadDataReg [31:5] \jtagBridge_1_.io_remote_rsp_payload_data [4:0] }, Q = \jtagBridge_1_.system_rsp_payload_data).
|
|
Adding EN signal on $flatten\jtagBridge_1_.$procdff$3878 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_payload_error).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4345 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3877 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2043_Y, Q = \jtagBridge_1_.system_rsp_valid, rval = 1'1).
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Adding EN signal on $auto$opt_dff.cc:702:run$4346 ($sdff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_valid).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3876 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2021_Y, Q = \jtagBridge_1_.jtag_readArea_shifter).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3875 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2027_Y, Q = \jtagBridge_1_.jtag_idcodeArea_shifter, rval = 268443647).
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Adding EN signal on $auto$opt_dff.cc:702:run$4353 ($sdff) from module PQVexRiscvUlx3s (D = { \io_jtag_tdi \jtagBridge_1_.jtag_idcodeArea_shifter [31:1] }, Q = \jtagBridge_1_.jtag_idcodeArea_shifter).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$3873 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$0\jtag_tap_instructionShift[3:0], Q = \jtagBridge_1_.jtag_tap_instructionShift).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3872 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2035_Y, Q = \jtagBridge_1_.jtag_tap_instruction, rval = 4'0001).
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Adding EN signal on $auto$opt_dff.cc:702:run$4360 ($sdff) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_tap_instructionShift, Q = \jtagBridge_1_.jtag_tap_instruction).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$3811 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_1, Q = \core_ibus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$3810 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_0, Q = \core_ibus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3815 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_2, Q = \core_dbus_decoder.logic_rspHits_2).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3814 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_1, Q = \core_dbus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$3813 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_0, Q = \core_dbus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4070 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.pushing, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.risingOccupancy).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4069 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_payload_inst 1'0 }, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c._zz_3_).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4368 ($dffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$4029 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_125_[2:0], Q = \core_cpu._zz_125_).
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Adding EN signal on $flatten\core_cpu.$procdff$4021 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_2).
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Adding EN signal on $flatten\core_cpu.$procdff$4020 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_1).
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Adding EN signal on $flatten\core_cpu.$procdff$4019 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_0).
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Adding EN signal on $flatten\core_cpu.$procdff$4017 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mie_MSIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4016 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [7], Q = \core_cpu.CsrPlugin_mie_MTIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4015 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [11], Q = \core_cpu.CsrPlugin_mie_MEIE).
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Adding EN signal on $flatten\core_cpu.$procdff$4011 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [31:2], Q = \core_cpu.CsrPlugin_mtvec_base).
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Adding EN signal on $flatten\core_cpu.$procdff$4010 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [1:0], Q = \core_cpu.CsrPlugin_mtvec_mode).
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Adding EN signal on $flatten\core_cpu.$procdff$4001 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_59_[0:0], Q = \core_cpu._zz_59_).
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Adding EN signal on $flatten\core_cpu.$procdff$4000 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_57_[0:0], Q = \core_cpu._zz_57_).
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Adding EN signal on $flatten\core_cpu.$procdff$3999 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_55_[0:0], Q = \core_cpu._zz_55_).
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Adding EN signal on $flatten\core_cpu.$procdff$3998 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \core_cpu.IBusSimplePlugin_fetchPc_inc).
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Adding EN signal on $flatten\core_cpu.$procdff$3995 ($adff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \core_cpu.IBusSimplePlugin_fetchPc_pcReg).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4422 ($adffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4422 ($adffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$3993 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_arbitration_isValid[0:0], Q = \core_cpu.memory_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$3992 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\execute_arbitration_isValid[0:0], Q = \core_cpu.execute_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$3991 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5419$952_Y, Q = \core_cpu.execute_CsrPlugin_csr_2946).
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Adding EN signal on $flatten\core_cpu.$procdff$3990 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5416$950_Y, Q = \core_cpu.execute_CsrPlugin_csr_2818).
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Adding EN signal on $flatten\core_cpu.$procdff$3989 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5413$948_Y, Q = \core_cpu.execute_CsrPlugin_csr_2944).
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Adding EN signal on $flatten\core_cpu.$procdff$3988 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5410$946_Y, Q = \core_cpu.execute_CsrPlugin_csr_2816).
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Adding EN signal on $flatten\core_cpu.$procdff$3987 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5407$944_Y, Q = \core_cpu.execute_CsrPlugin_csr_834).
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Adding EN signal on $flatten\core_cpu.$procdff$3986 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5404$942_Y, Q = \core_cpu.execute_CsrPlugin_csr_773).
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Adding EN signal on $flatten\core_cpu.$procdff$3985 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5401$940_Y, Q = \core_cpu.execute_CsrPlugin_csr_772).
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Adding EN signal on $flatten\core_cpu.$procdff$3984 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5398$938_Y, Q = \core_cpu.execute_CsrPlugin_csr_836).
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Adding EN signal on $flatten\core_cpu.$procdff$3983 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5395$936_Y, Q = \core_cpu.execute_CsrPlugin_csr_768).
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Adding EN signal on $flatten\core_cpu.$procdff$3982 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_EXECUTE_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3981 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_27_, Q = \core_cpu.decode_to_execute_RS2).
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Adding EN signal on $flatten\core_cpu.$procdff$3980 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_2_ [1] \core_cpu._zz_384_ }, Q = \core_cpu.decode_to_execute_BRANCH_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3979 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_LESS_UNSIGNED, Q = \core_cpu.decode_to_execute_SRC_LESS_UNSIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3977 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC1, Q = \core_cpu.execute_to_memory_SRC1).
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Adding EN signal on $flatten\core_cpu.$procdff$3976 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC1, Q = \core_cpu.decode_to_execute_SRC1).
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Adding EN signal on $flatten\core_cpu.$procdff$3975 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_CSR, Q = \core_cpu.decode_to_execute_IS_CSR).
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Adding EN signal on $flatten\core_cpu.$procdff$3973 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC2, Q = \core_cpu.execute_to_memory_SRC2).
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Adding EN signal on $flatten\core_cpu.$procdff$3972 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2, Q = \core_cpu.decode_to_execute_SRC2).
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Adding EN signal on $flatten\core_cpu.$procdff$3971 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LL, Q = \core_cpu.execute_to_memory_MUL_LL).
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Adding EN signal on $flatten\core_cpu.$procdff$3969 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_ENV_CTRL, Q = \core_cpu.execute_to_memory_ENV_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3968 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_9_, Q = \core_cpu.decode_to_execute_ENV_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3963 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LH, Q = \core_cpu.execute_to_memory_MUL_LH).
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Adding EN signal on $flatten\core_cpu.$procdff$3961 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_VALID).
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Adding EN signal on $flatten\core_cpu.$procdff$3960 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_REGFILE_WRITE_VALID, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID).
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Adding SRST signal on $auto$opt_dff.cc:764:run$4452 ($dffe) from module PQVexRiscvUlx3s (D = \core_cpu._zz_191_, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
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Adding EN signal on $flatten\core_cpu.$procdff$3956 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.decode_to_execute_PC).
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Adding EN signal on $flatten\core_cpu.$procdff$3955 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2_FORCE_ZERO, Q = \core_cpu.decode_to_execute_SRC2_FORCE_ZERO).
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Adding EN signal on $flatten\core_cpu.$procdff$3954 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_304_ \core_cpu._zz_317_ }, Q = \core_cpu.decode_to_execute_ALU_BITWISE_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3953 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_BRANCH_DO, Q = \core_cpu.execute_to_memory_BRANCH_DO).
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Adding EN signal on $flatten\core_cpu.$procdff$3952 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SHIFT_CTRL, Q = \core_cpu.execute_to_memory_SHIFT_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3951 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_319_ \core_cpu._zz_320_ }, Q = \core_cpu.decode_to_execute_SHIFT_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3950 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS2_SIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3948 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_MUL, Q = \core_cpu.execute_to_memory_IS_MUL).
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Adding EN signal on $flatten\core_cpu.$procdff$3947 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_MUL, Q = \core_cpu.decode_to_execute_IS_MUL).
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Adding EN signal on $flatten\core_cpu.$procdff$3946 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HL, Q = \core_cpu.execute_to_memory_MUL_HL).
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Adding EN signal on $flatten\core_cpu.$procdff$3944 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_ENABLE, Q = \core_cpu.execute_to_memory_MEMORY_ENABLE).
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Adding EN signal on $flatten\core_cpu.$procdff$3943 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_ENABLE, Q = \core_cpu.decode_to_execute_MEMORY_ENABLE).
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Adding EN signal on $flatten\core_cpu.$procdff$3942 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_373_ \core_cpu._zz_368_ }, Q = \core_cpu.decode_to_execute_ALU_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$3941 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_INSTRUCTION, Q = \core_cpu.execute_to_memory_INSTRUCTION).
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Adding EN signal on $flatten\core_cpu.$procdff$3940 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_62_, Q = \core_cpu.decode_to_execute_INSTRUCTION).
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Adding EN signal on $flatten\core_cpu.$procdff$3939 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_DO_EBREAK, Q = \core_cpu.decode_to_execute_DO_EBREAK).
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Adding EN signal on $flatten\core_cpu.$procdff$3937 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \core_cpu.execute_to_memory_MEMORY_STORE).
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Adding EN signal on $flatten\core_cpu.$procdff$3936 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_STORE, Q = \core_cpu.decode_to_execute_MEMORY_STORE).
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Adding EN signal on $flatten\core_cpu.$procdff$3934 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.execute_to_memory_BYPASSABLE_MEMORY_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3933 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE).
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Adding EN signal on $flatten\core_cpu.$procdff$3931 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB [1:0], Q = \core_cpu.execute_to_memory_MEMORY_ADDRESS_LOW).
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Adding EN signal on $flatten\core_cpu.$procdff$3930 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_USE_SUB_LESS, Q = \core_cpu.decode_to_execute_SRC_USE_SUB_LESS).
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Adding EN signal on $flatten\core_cpu.$procdff$3929 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS1_SIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$3928 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_29_, Q = \core_cpu.decode_to_execute_RS1).
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Adding EN signal on $flatten\core_cpu.$procdff$3927 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \core_cpu.execute_to_memory_BRANCH_CALC).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4478 ($dffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$3926 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_DIV, Q = \core_cpu.execute_to_memory_IS_DIV).
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Adding EN signal on $flatten\core_cpu.$procdff$3925 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_DIV, Q = \core_cpu.decode_to_execute_IS_DIV).
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Adding EN signal on $flatten\core_cpu.$procdff$3924 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_183_ [31:0], Q = \core_cpu.execute_to_memory_SHIFT_RIGHT).
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Adding EN signal on $flatten\core_cpu.$procdff$3923 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_43_, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_DATA).
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Adding EN signal on $flatten\core_cpu.$procdff$3922 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HH, Q = \core_cpu.execute_to_memory_MUL_HH).
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Adding EN signal on $flatten\core_cpu.$procdff$3921 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_CSR_WRITE_OPCODE, Q = \core_cpu.decode_to_execute_CSR_WRITE_OPCODE).
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Adding EN signal on $flatten\core_cpu.$procdff$3920 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_228_ [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_div_result).
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Adding SRST signal on $flatten\core_cpu.$procdff$3919 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2372_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_done, rval = 1'0).
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Adding EN signal on $auto$opt_dff.cc:702:run$4490 ($sdff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.memory_MulDivIterativePlugin_div_done).
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Adding EN signal on $flatten\core_cpu.$procdff$3918 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$logic_and$PQVexRiscvUlx3s.v:5203$871_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_needRevert).
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Adding SRST signal on $flatten\core_cpu.$procdff$3917 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2218_Y, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0], rval = 0).
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Adding EN signal on $flatten\core_cpu.$procdff$3917 ($dff) from module PQVexRiscvUlx3s (D = 33'000000000000000000000000000000000, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [64:32]).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$4494 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$4493 ($sdff) from module PQVexRiscvUlx3s (D = \core_cpu.memory_MulDivIterativePlugin_div_stage_0_outRemainder, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3916 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5202$862_Y, Q = \core_cpu.memory_MulDivIterativePlugin_rs2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3915 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859_Y [32], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [32]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3915 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0] [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [31:0]).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3912 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2394_Y, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4513 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege, rval = 2'11).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4516 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4516 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3911 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2402_Y, Q = \core_cpu.CsrPlugin_interrupt_code).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4521 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2400_Y [3], Q = \core_cpu.CsrPlugin_interrupt_code [3], rval = 1'1).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4521 ($dffe) from module PQVexRiscvUlx3s (D = 3'xxx, Q = \core_cpu.CsrPlugin_interrupt_code [2:0], rval = 3'011).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4525 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4525 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4525 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3910 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5155$852_Y, Q = \core_cpu.CsrPlugin_minstret).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3908 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.CsrPlugin_interrupt_code, Q = \core_cpu.CsrPlugin_mcause_exceptionCode).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3907 ($dff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.CsrPlugin_mcause_interrupt).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4532 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$3906 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mip_MSIP, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3903 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.CsrPlugin_mepc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3900 ($dff) from module PQVexRiscvUlx3s (D = { $flatten\core_cpu.$0\_zz_62_[31:0] [31:25] $flatten\core_cpu.$0\_zz_62_[31:0] [14:0] }, Q = { \core_cpu._zz_62_ [31:25] \core_cpu._zz_62_ [14:0] }).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3898 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_58_, Q = \core_cpu._zz_60_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3897 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_fetchPc_pcReg, Q = \core_cpu._zz_58_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3894 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\DebugPlugin_busReadDataReg[31:0], Q = \core_cpu.DebugPlugin_busReadDataReg).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3893 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3892 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3891 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3887 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3886 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3885 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3882 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [36], Q = \core_cpu.DebugPlugin_stepIt).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$3880 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2179_Y, Q = \core_cpu.DebugPlugin_resetIt).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4056 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4084 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\break_counter[6:0], Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.break_counter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4081 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_2).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4080 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.io_rxd_buffercc.buffers_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4074 ($dff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$or$PQVexRiscvUlx3s.v:0$80_Y, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_shifter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4056 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3859 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readOverflowError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readOverflowError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3858 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3857 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_readIntEnable).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3856 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_writeIntEnable).
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 214 unused cells and 239 unused wires.
|
|
<suppressed ~219 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~269 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~39 debug messages>
|
|
Removed a total of 13 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4543 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4543 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4529 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4529 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4529 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4268 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4266 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4266 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:702:run$4264 ($sdffce) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 21 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.13.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~270 debug messages>
|
|
|
|
2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4542 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4542 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4262 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4262 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4262 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4262 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~270 debug messages>
|
|
|
|
2.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4538 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4538 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4454 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4454 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~270 debug messages>
|
|
|
|
2.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4546 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2189_Y [1:0], Q = \core_cpu.DebugPlugin_busReadDataReg [1:0], rval = 2'00).
|
|
|
|
2.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.37. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~271 debug messages>
|
|
|
|
2.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.40. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.41. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.43. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.44. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 16 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol0$PQVexRiscvUlx3s.v:0$1121 (memory_ramBlocks_0.ram_symbol0).
|
|
Removed top 16 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol1$PQVexRiscvUlx3s.v:0$1122 (memory_ramBlocks_0.ram_symbol1).
|
|
Removed top 16 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol2$PQVexRiscvUlx3s.v:0$1123 (memory_ramBlocks_0.ram_symbol2).
|
|
Removed top 16 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$meminit$\ram_symbol3$PQVexRiscvUlx3s.v:0$1124 (memory_ramBlocks_0.ram_symbol3).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1572 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$1578 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4505 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4411 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4198 ($eq).
|
|
Removed top 31 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4032 ($dff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4028 ($adff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$auto$opt_dff.cc:764:run$4467 ($dffe).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3355 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3353 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3219_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3017_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3010_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2907_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2903_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2898_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2894_CMP0 ($eq).
|
|
Removed top 12 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2748 ($pmux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2742_CMP0 ($eq).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2667_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2600 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2596 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2580 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2572 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2568 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2474 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2472 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2468 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2466 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2462 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2453 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2452_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2451_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2450_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2448 ($mux).
|
|
Removed top 7 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2424 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2400 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2380 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2378 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2189 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2177 ($mux).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2113_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2105_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2098_CMP0 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5407$944 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5404$942 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5401$940 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5398$938 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5395$936 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5202$862 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859 ($add).
|
|
Removed top 1 bits (of 33) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:5201$858 ($mux).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5201$857 ($not).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5201$857 ($not).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5155$852 ($add).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5153$851 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4985$823 ($sub).
|
|
Removed top 20 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4853$793 ($or).
|
|
Removed top 19 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4853$792 ($or).
|
|
Removed top 20 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4853$792 ($or).
|
|
Removed top 19 bits (of 32) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4853$792 ($or).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4650$715 ($sub).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4641$714 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4587$702 ($add).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4587$702 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4470$687 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4367$671 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4185$653 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4185$652 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4185$650 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4184$647 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4184$646 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4183$645 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4183$644 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4181$641 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4181$640 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4180$639 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4180$638 ($and).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3900$559 ($sub).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:3365$450 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2719$421 ($and).
|
|
Removed top 28 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2717$420 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2714$419 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2712$417 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2712$416 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2710$415 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2709$414 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2709$413 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2709$412 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2708$410 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2707$408 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2707$407 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2703$402 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2700$401 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2699$399 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2699$398 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2697$396 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2689$390 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2688$388 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2688$387 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2686$386 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2684$385 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2674$382 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2673$381 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2670$376 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2670$375 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2669$374 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2669$373 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2665$371 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2657$366 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2656$365 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2656$364 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2655$363 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2655$362 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2654$361 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2654$360 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2653$359 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2653$358 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2647$354 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2647$353 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2646$352 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2646$351 ($and).
|
|
Removed top 11 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2644$350 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2642$349 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2639$348 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2637$347 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2633$343 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2631$342 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2629$341 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2629$340 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2627$339 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2626$338 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2626$337 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2625$336 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2625$335 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2623$334 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2621$333 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2619$332 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2611$328 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2609$327 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2607$326 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2605$325 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2604$324 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2603$323 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2602$322 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2602$321 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2600$320 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2597$316 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2595$315 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2595$314 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2594$313 ($eq).
|
|
Removed top 3 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2591$312 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2589$311 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2585$307 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2582$305 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2582$304 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2579$303 ($and).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2551$298 ($add).
|
|
Removed top 31 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:2542$293 ($mux).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2538$289 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2526$286 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285 ($sub).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2522$284 ($and).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2522$284 ($and).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2522$284 ($and).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2522$283 ($not).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2522$283 ($not).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sshr$PQVexRiscvUlx3s.v:2513$280 ($sshr).
|
|
Removed top 15 bits (of 48) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2508$279 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2094_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2093_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2090_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2089_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2088_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2034_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2033_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2019 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5790$986 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5775$983 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5774$982 ($eq).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5742$980 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5736$978 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5733$977 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5730$976 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5724$974 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5712$970 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5703$967 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5700$966 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2015 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2013 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2009 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$1997 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5895$1002 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4372 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4330 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4314 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4224 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3472 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3474 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4059 ($dff).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3472 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3474 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4059 ($dff).
|
|
Removed top 19 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4180 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4176 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3608 ($mux).
|
|
Removed top 7 bits (of 8) from port A of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$shl$PQVexRiscvUlx3s.v:0$77 ($shl).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
Removed top 6 bits (of 7) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
Removed top 2 bits (of 5) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1842_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1835 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1833 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1829 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1827 ($mux).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1801_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1790_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1784_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1770_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1757_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1745_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1737_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1730_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1724_CMP0 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$eq$PQVexRiscvUlx3s.v:6528$1070 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6613$1079 ($eq).
|
|
Removed top 3 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6612$1076 ($eq).
|
|
Removed top 3 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\apb3Router_1_.$procmux$1709 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3846 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3843 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3840 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3837 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1695 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1693 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1689 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1687 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1683 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1681 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1677 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1675 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3829 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3826 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3823 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3820 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1663 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1661 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1657 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1655 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1651 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1649 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1645 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1643 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$procmux$1639_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6980$1211 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6904$1170 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7102$1248 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7042$1214 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3419 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3421 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4047 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3423 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3427 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1108$165 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procmux$3441 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3419 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3421 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4047 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3361 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3365 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1390$219 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1400$228 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procmux$3379 ($mux).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285 ($sub).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285 ($sub).
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0].
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859_Y.
|
|
Removed top 1 bits (of 2) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2522$283_Y.
|
|
Removed top 19 bits (of 32) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4853$792_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5700$966_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5703$967_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5712$970_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5724$974_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5730$976_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5733$977_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5736$978_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5742$980_Y.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3Router_1__io_input_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3UartCtrl_1__io_apb_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.io_apb_decoder_io_input_PRDATA.
|
|
|
|
2.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 76 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.17. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.21. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.3. Continuing TECHMAP pass.
|
|
Using template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\_80_mul for cells of type $mul.
|
|
Using template $paramod\$__MUL18X18\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=32\A_SIGNED=0\B_SIGNED=0 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~98 debug messages>
|
|
|
|
2.22. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module PQVexRiscvUlx3s:
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6116$1018 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2508$279 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2526$286 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2538$289 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2539$290 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2549$294 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2550$296 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2551$298 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4574$699 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4587$702 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4641$714 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5153$851 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5155$852 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5202$862 ($add).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3900$559 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4650$715 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4985$823 ($sub).
|
|
creating $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6904$1170 ($add).
|
|
creating $macc model for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6980$1211 ($sub).
|
|
creating $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7042$1214 ($add).
|
|
creating $macc model for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7102$1248 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1390$219 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200 ($add).
|
|
creating $macc model for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5895$1002 ($add).
|
|
merging $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7042$1214 into $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7102$1248.
|
|
merging $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:6904$1170 into $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6980$1211.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2526$286 into $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3900$559.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2550$296 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2549$294.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2551$298 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2549$294.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2539$290 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2538$289.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4587$702 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2508$279.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4985$823.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4650$715.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5202$862.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5155$852.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5153$851.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4641$714.
|
|
creating $alu model for $macc $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5895$1002.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4574$699.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1390$219.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6116$1018.
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2538$289: $auto$alumacc.cc:365:replace_macc$4627
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2549$294: $auto$alumacc.cc:365:replace_macc$4628
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2508$279: $auto$alumacc.cc:365:replace_macc$4629
|
|
creating $macc cell for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:6980$1211: $auto$alumacc.cc:365:replace_macc$4630
|
|
creating $macc cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3900$559: $auto$alumacc.cc:365:replace_macc$4631
|
|
creating $macc cell for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7102$1248: $auto$alumacc.cc:365:replace_macc$4632
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146.
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6116$1018: $auto$alumacc.cc:485:replace_alu$4633
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4636
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4639
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4642
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112: $auto$alumacc.cc:485:replace_alu$4647
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56: $auto$alumacc.cc:485:replace_alu$4650
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66: $auto$alumacc.cc:485:replace_alu$4653
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65: $auto$alumacc.cc:485:replace_alu$4656
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10: $auto$alumacc.cc:485:replace_alu$4659
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24: $auto$alumacc.cc:485:replace_alu$4662
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4665
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4668
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146: $auto$alumacc.cc:485:replace_alu$4671
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200: $auto$alumacc.cc:485:replace_alu$4674
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1309$200: $auto$alumacc.cc:485:replace_alu$4677
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1390$219: $auto$alumacc.cc:485:replace_alu$4680
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194: $auto$alumacc.cc:485:replace_alu$4683
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2560$302: $auto$alumacc.cc:485:replace_alu$4686
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527: $auto$alumacc.cc:485:replace_alu$4689
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4574$699: $auto$alumacc.cc:485:replace_alu$4692
|
|
creating $alu cell for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5895$1002: $auto$alumacc.cc:485:replace_alu$4695
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4641$714: $auto$alumacc.cc:485:replace_alu$4698
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5153$851: $auto$alumacc.cc:485:replace_alu$4701
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5155$852: $auto$alumacc.cc:485:replace_alu$4704
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5201$859: $auto$alumacc.cc:485:replace_alu$4707
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5202$862: $auto$alumacc.cc:485:replace_alu$4710
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2523$285: $auto$alumacc.cc:485:replace_alu$4713
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4650$715: $auto$alumacc.cc:485:replace_alu$4716
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4985$823: $auto$alumacc.cc:485:replace_alu$4719
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1282$194: $auto$alumacc.cc:485:replace_alu$4722
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1098$156: $auto$alumacc.cc:485:replace_alu$4725
|
|
created 31 $alu and 6 $macc cells.
|
|
|
|
2.23. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.23.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~24 debug messages>
|
|
Removed a total of 8 cells.
|
|
|
|
2.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~241 debug messages>
|
|
|
|
2.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.23.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3828 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6826$1133_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3825 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6823$1132_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3822 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6820$1131_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3819 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6817$1130_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3845 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:6758$1088_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3842 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:6755$1087_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3839 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:6752$1086_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3836 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:6749$1085_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$4352 ($dffe) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_readArea_shifter [2], Q = \jtagBridge_1_.jtag_readArea_shifter [1], rval = 1'0).
|
|
|
|
2.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 9 unused cells and 74 unused wires.
|
|
<suppressed ~38 debug messages>
|
|
|
|
2.23.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~235 debug messages>
|
|
|
|
2.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.23.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.23.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.24. Executing MEMORY pass.
|
|
|
|
2.24.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.24.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:0$959' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1125' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1126' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1127' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1128' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$216' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1166' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1167' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1168' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1169' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$216' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2724$423' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2730$425' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6740$1091' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6741$1092' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6742$1093' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6743$1094' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1248$183' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:6808$1136' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:6809$1137' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:6810$1138' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:6811$1139' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1248$183' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
|
|
2.24.3. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 43 unused cells and 55 unused wires.
|
|
<suppressed ~44 debug messages>
|
|
|
|
2.24.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.24.6. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.25. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol0:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol0.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol0.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol0.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol0.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol0.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol0.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol0.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol0.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol0.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol0.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol0.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol0.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol0.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol0.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol0.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol0.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol0.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol0.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol0.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol0.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol0.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol0.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol0.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol0.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol0.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol1:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol1.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol1.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol1.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol1.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol1.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol1.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol1.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol1.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol1.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol1.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol1.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol1.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol1.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol1.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol1.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol1.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol1.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol1.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol1.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol1.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol1.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol1.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol1.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol1.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol1.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol2:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol2.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol2.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol2.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol2.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol2.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol2.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol2.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol2.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol2.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol2.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol2.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol2.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol2.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol2.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol2.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol2.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol2.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol2.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol2.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol2.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol2.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol2.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol2.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol2.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol2.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol3:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol3.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol3.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol3.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol3.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol3.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol3.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol3.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol3.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol3.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol3.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol3.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol3.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol3.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol3.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol3.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol3.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol3.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol3.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol3.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol3.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol3.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol3.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol3.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol3.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol3.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol0:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol0.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol0.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol0.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol0.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol0.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol0.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol0.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol0.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol0.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol1:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol1.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol1.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol1.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol1.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol1.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol1.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol1.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol1.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol1.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol2:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol2.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol2.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol2.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol2.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol2.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol2.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol2.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol2.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol2.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol3:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol3.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol3.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol3.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol3.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol3.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol3.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol3.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol3.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol3.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
|
|
2.27. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
|
|
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.27.2. Continuing TECHMAP pass.
|
|
Using template $paramod$53d5203639c6bc1e4ede1d2a7482ee7adee11192\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$d9618481cfed4a8c49e61e1c1a6d73bb9dab92f3\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$672854668c3d28fa297cd425741228a4ad1839bd\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$38262e435a9f54db3b5bdc33b5e39b1fffa1b883\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$f630d87ca5e01700531afe07992bd3c8c221c9b8\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$0d4f984ef2648ac40679adb5f4d2fbdf250b204a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$9438ba363c0feada674254e23ebb327cc03eb4e1\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$665daa24e5c8b21cd7d1a87514f418930c87d619\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$f2e8301827648c8cb606c5517bdbc03aaf93e34d\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$d03f3b27c4d9e1e2380cab7963f05cfac84ad0d4\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$93fa4555310d13c440c6bb0d429ea9db08fc2638\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$da4df3005025319c86d6fe059648ba38330ef40c\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$c8d676c916d764bbfca4e06433df20dc20854f8a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$5649139d4907fedf0ed75c810f732ab1742bf673\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$8915003442e9d549081976b0a0ca6a290f27ab2a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$bd57d9fb8cadb449860c089c2c7d7d67b7789f81\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$7da2c443ddfe8283bba4c7d521dc32ed8016b94a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$c6274c3809a23cf325b51185f5e66ed15fede3e7\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$d6c0753584a9581fee12d1cbffb3a6f827ececb1\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$e53b3aec4901cd92e9144d56fac349c1c86a3115\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$2171f7039c77ca2c63bbe74e30747aa93971b70f\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$8db68796e552d7dab21f182c5cb6b233f87dd366\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$ef14e2a0672d373e548e6f56e1ff4a6bd945fe4c\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$1b093e0d5aae8819457f2bfcd9dc07de37042818\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$6ca0d5a125b3930afd2e18854b5d038dd842cb17\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$9d362e4cd098fc254ed41dddde34d93929a12faa\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$5cd02c60b4baa877c9a29d16f479c7848a9fac4f\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$be39805a11c7c665638a00b2412b7de0bdd12440\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$11f3a3c8cd24f3fb18f3155743862263910055dc\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$9cb946a9fafefb4d001fde41b1d58bff93fd457c\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$76d31f416200b4310e45831bff68a9a6849d8349\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$866237ac1548c1baa5d51ab0e4cb2dc4b68d8100\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$28c3888cd49a97ecd3d81388bbc3b8dfa83694ea\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
No more expansions possible.
|
|
<suppressed ~953 debug messages>
|
|
|
|
2.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.2.
|
|
Updated properties: dups=2 waste=0 efficiency=50
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: core_cpu.RegFilePlugin_regFile.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: core_cpu.RegFilePlugin_regFile.0.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: core_cpu.RegFilePlugin_regFile.0.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: core_cpu.RegFilePlugin_regFile.0.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: core_cpu.RegFilePlugin_regFile.1.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: core_cpu.RegFilePlugin_regFile.1.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: core_cpu.RegFilePlugin_regFile.1.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: core_cpu.RegFilePlugin_regFile.1.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: core_cpu.RegFilePlugin_regFile.2.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: core_cpu.RegFilePlugin_regFile.2.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: core_cpu.RegFilePlugin_regFile.2.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: core_cpu.RegFilePlugin_regFile.2.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: core_cpu.RegFilePlugin_regFile.3.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: core_cpu.RegFilePlugin_regFile.3.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: core_cpu.RegFilePlugin_regFile.3.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: core_cpu.RegFilePlugin_regFile.3.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: core_cpu.RegFilePlugin_regFile.4.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: core_cpu.RegFilePlugin_regFile.4.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: core_cpu.RegFilePlugin_regFile.4.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: core_cpu.RegFilePlugin_regFile.4.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: core_cpu.RegFilePlugin_regFile.5.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: core_cpu.RegFilePlugin_regFile.5.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: core_cpu.RegFilePlugin_regFile.5.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: core_cpu.RegFilePlugin_regFile.5.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: core_cpu.RegFilePlugin_regFile.6.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: core_cpu.RegFilePlugin_regFile.6.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: core_cpu.RegFilePlugin_regFile.6.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: core_cpu.RegFilePlugin_regFile.6.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: core_cpu.RegFilePlugin_regFile.7.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: core_cpu.RegFilePlugin_regFile.7.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: core_cpu.RegFilePlugin_regFile.7.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: core_cpu.RegFilePlugin_regFile.7.1.1
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
|
|
2.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.29.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~52 debug messages>
|
|
|
|
2.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~1171 debug messages>
|
|
|
|
2.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~2280 debug messages>
|
|
Removed a total of 760 cells.
|
|
|
|
2.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6512 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6505, Q = $auto$memory_bram.cc:1009:replace_memory$6509).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7298 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7291, Q = $auto$memory_bram.cc:1009:replace_memory$7295).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6525 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6518, Q = $auto$memory_bram.cc:1009:replace_memory$6522).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6075 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6068, Q = $auto$memory_bram.cc:1009:replace_memory$6072).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6931 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6924, Q = $auto$memory_bram.cc:1009:replace_memory$6928).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6538 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6531, Q = $auto$memory_bram.cc:1009:replace_memory$6535).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4889 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4882, Q = $auto$memory_bram.cc:1009:replace_memory$4886).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4902 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4895, Q = $auto$memory_bram.cc:1009:replace_memory$4899).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6088 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6081, Q = $auto$memory_bram.cc:1009:replace_memory$6085).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4915 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4908, Q = $auto$memory_bram.cc:1009:replace_memory$4912).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4928 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4921, Q = $auto$memory_bram.cc:1009:replace_memory$4925).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6551 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6544, Q = $auto$memory_bram.cc:1009:replace_memory$6548).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7030 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7023, Q = $auto$memory_bram.cc:1009:replace_memory$7027).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4941 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4934, Q = $auto$memory_bram.cc:1009:replace_memory$4938).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6101 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6094, Q = $auto$memory_bram.cc:1009:replace_memory$6098).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4954 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4947, Q = $auto$memory_bram.cc:1009:replace_memory$4951).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6564 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6557, Q = $auto$memory_bram.cc:1009:replace_memory$6561).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6499 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6492, Q = $auto$memory_bram.cc:1009:replace_memory$6496).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4967 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4960, Q = $auto$memory_bram.cc:1009:replace_memory$4964).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6114 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6107, Q = $auto$memory_bram.cc:1009:replace_memory$6111).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4980 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4973, Q = $auto$memory_bram.cc:1009:replace_memory$4977).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$4993 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4986, Q = $auto$memory_bram.cc:1009:replace_memory$4990).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6944 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6937, Q = $auto$memory_bram.cc:1009:replace_memory$6941).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5006 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$4999, Q = $auto$memory_bram.cc:1009:replace_memory$5003).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5019 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5012, Q = $auto$memory_bram.cc:1009:replace_memory$5016).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7069 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7062, Q = $auto$memory_bram.cc:1009:replace_memory$7066).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6127 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6120, Q = $auto$memory_bram.cc:1009:replace_memory$6124).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5032 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5025, Q = $auto$memory_bram.cc:1009:replace_memory$5029).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6585 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6578, Q = $auto$memory_bram.cc:1009:replace_memory$6582).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7246 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7239, Q = $auto$memory_bram.cc:1009:replace_memory$7243).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5045 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5038, Q = $auto$memory_bram.cc:1009:replace_memory$5042).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6421 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6414, Q = $auto$memory_bram.cc:1009:replace_memory$6418).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5058 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5051, Q = $auto$memory_bram.cc:1009:replace_memory$5055).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7311 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7304, Q = $auto$memory_bram.cc:1009:replace_memory$7308).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6140 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6133, Q = $auto$memory_bram.cc:1009:replace_memory$6137).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5071 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5064, Q = $auto$memory_bram.cc:1009:replace_memory$5068).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6598 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6591, Q = $auto$memory_bram.cc:1009:replace_memory$6595).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5084 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5077, Q = $auto$memory_bram.cc:1009:replace_memory$5081).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5097 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5090, Q = $auto$memory_bram.cc:1009:replace_memory$5094).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5110 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5103, Q = $auto$memory_bram.cc:1009:replace_memory$5107).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7082 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7075, Q = $auto$memory_bram.cc:1009:replace_memory$7079).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5123 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5116, Q = $auto$memory_bram.cc:1009:replace_memory$5120).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6611 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6604, Q = $auto$memory_bram.cc:1009:replace_memory$6608).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5136 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5129, Q = $auto$memory_bram.cc:1009:replace_memory$5133).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7285 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7278, Q = $auto$memory_bram.cc:1009:replace_memory$7282).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5149 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5142, Q = $auto$memory_bram.cc:1009:replace_memory$5146).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6624 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6617, Q = $auto$memory_bram.cc:1009:replace_memory$6621).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6161 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6154, Q = $auto$memory_bram.cc:1009:replace_memory$6158).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5162 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5155, Q = $auto$memory_bram.cc:1009:replace_memory$5159).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7415 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7408, Q = $auto$memory_bram.cc:1009:replace_memory$7412).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6957 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6950, Q = $auto$memory_bram.cc:1009:replace_memory$6954).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5175 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5168, Q = $auto$memory_bram.cc:1009:replace_memory$5172).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7389 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7382, Q = $auto$memory_bram.cc:1009:replace_memory$7386).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5188 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5181, Q = $auto$memory_bram.cc:1009:replace_memory$5185).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7095 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7088, Q = $auto$memory_bram.cc:1009:replace_memory$7092).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5201 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5194, Q = $auto$memory_bram.cc:1009:replace_memory$5198).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6637 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6630, Q = $auto$memory_bram.cc:1009:replace_memory$6634).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6174 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6167, Q = $auto$memory_bram.cc:1009:replace_memory$6171).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5214 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5207, Q = $auto$memory_bram.cc:1009:replace_memory$5211).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5227 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5220, Q = $auto$memory_bram.cc:1009:replace_memory$5224).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7324 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7317, Q = $auto$memory_bram.cc:1009:replace_memory$7321).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6650 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6643, Q = $auto$memory_bram.cc:1009:replace_memory$6647).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5240 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5233, Q = $auto$memory_bram.cc:1009:replace_memory$5237).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5253 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5246, Q = $auto$memory_bram.cc:1009:replace_memory$5250).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7108 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7101, Q = $auto$memory_bram.cc:1009:replace_memory$7105).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6187 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6180, Q = $auto$memory_bram.cc:1009:replace_memory$6184).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5266 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5259, Q = $auto$memory_bram.cc:1009:replace_memory$5263).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6663 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6656, Q = $auto$memory_bram.cc:1009:replace_memory$6660).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5279 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5272, Q = $auto$memory_bram.cc:1009:replace_memory$5276).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5292 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5285, Q = $auto$memory_bram.cc:1009:replace_memory$5289).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6434 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6427, Q = $auto$memory_bram.cc:1009:replace_memory$6431).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7259 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7252, Q = $auto$memory_bram.cc:1009:replace_memory$7256).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5313 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5306, Q = $auto$memory_bram.cc:1009:replace_memory$5310).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6676 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6669, Q = $auto$memory_bram.cc:1009:replace_memory$6673).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5326 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5319, Q = $auto$memory_bram.cc:1009:replace_memory$5323).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6200 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6193, Q = $auto$memory_bram.cc:1009:replace_memory$6197).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5339 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5332, Q = $auto$memory_bram.cc:1009:replace_memory$5336).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7121 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7114, Q = $auto$memory_bram.cc:1009:replace_memory$7118).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6970 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6963, Q = $auto$memory_bram.cc:1009:replace_memory$6967).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5352 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5345, Q = $auto$memory_bram.cc:1009:replace_memory$5349).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7337 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7330, Q = $auto$memory_bram.cc:1009:replace_memory$7334).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5365 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5358, Q = $auto$memory_bram.cc:1009:replace_memory$5362).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6689 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6682, Q = $auto$memory_bram.cc:1009:replace_memory$6686).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6213 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6206, Q = $auto$memory_bram.cc:1009:replace_memory$6210).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5378 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5371, Q = $auto$memory_bram.cc:1009:replace_memory$5375).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5391 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5384, Q = $auto$memory_bram.cc:1009:replace_memory$5388).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7056 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7049, Q = $auto$memory_bram.cc:1009:replace_memory$7053).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5404 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5397, Q = $auto$memory_bram.cc:1009:replace_memory$5401).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6702 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6695, Q = $auto$memory_bram.cc:1009:replace_memory$6699).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6226 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6219, Q = $auto$memory_bram.cc:1009:replace_memory$6223).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5417 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5410, Q = $auto$memory_bram.cc:1009:replace_memory$5414).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5430 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5423, Q = $auto$memory_bram.cc:1009:replace_memory$5427).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7134 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7127, Q = $auto$memory_bram.cc:1009:replace_memory$7131).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7428 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7421, Q = $auto$memory_bram.cc:1009:replace_memory$7425).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5443 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5436, Q = $auto$memory_bram.cc:1009:replace_memory$5440).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6447 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6440, Q = $auto$memory_bram.cc:1009:replace_memory$6444).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5456 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5449, Q = $auto$memory_bram.cc:1009:replace_memory$5453).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6715 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6708, Q = $auto$memory_bram.cc:1009:replace_memory$6712).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6239 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6232, Q = $auto$memory_bram.cc:1009:replace_memory$6236).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5469 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5462, Q = $auto$memory_bram.cc:1009:replace_memory$5466).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6983 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6976, Q = $auto$memory_bram.cc:1009:replace_memory$6980).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5482 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5475, Q = $auto$memory_bram.cc:1009:replace_memory$5479).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6728 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6721, Q = $auto$memory_bram.cc:1009:replace_memory$6725).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5495 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5488, Q = $auto$memory_bram.cc:1009:replace_memory$5492).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7350 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7343, Q = $auto$memory_bram.cc:1009:replace_memory$7347).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7147 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7140, Q = $auto$memory_bram.cc:1009:replace_memory$7144).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6252 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6245, Q = $auto$memory_bram.cc:1009:replace_memory$6249).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5508 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5501, Q = $auto$memory_bram.cc:1009:replace_memory$5505).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5521 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5514, Q = $auto$memory_bram.cc:1009:replace_memory$5518).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6741 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6734, Q = $auto$memory_bram.cc:1009:replace_memory$6738).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5534 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5527, Q = $auto$memory_bram.cc:1009:replace_memory$5531).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5547 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5540, Q = $auto$memory_bram.cc:1009:replace_memory$5544).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6265 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6258, Q = $auto$memory_bram.cc:1009:replace_memory$6262).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5560 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5553, Q = $auto$memory_bram.cc:1009:replace_memory$5557).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6754 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6747, Q = $auto$memory_bram.cc:1009:replace_memory$6751).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5573 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5566, Q = $auto$memory_bram.cc:1009:replace_memory$5570).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7160 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7153, Q = $auto$memory_bram.cc:1009:replace_memory$7157).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5586 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5579, Q = $auto$memory_bram.cc:1009:replace_memory$5583).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6278 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6271, Q = $auto$memory_bram.cc:1009:replace_memory$6275).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5599 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5592, Q = $auto$memory_bram.cc:1009:replace_memory$5596).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6996 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6989, Q = $auto$memory_bram.cc:1009:replace_memory$6993).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5612 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5605, Q = $auto$memory_bram.cc:1009:replace_memory$5609).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6767 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6760, Q = $auto$memory_bram.cc:1009:replace_memory$6764).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6460 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6453, Q = $auto$memory_bram.cc:1009:replace_memory$6457).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5625 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5618, Q = $auto$memory_bram.cc:1009:replace_memory$5622).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5638 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5631, Q = $auto$memory_bram.cc:1009:replace_memory$5635).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6291 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6284, Q = $auto$memory_bram.cc:1009:replace_memory$6288).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5651 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5644, Q = $auto$memory_bram.cc:1009:replace_memory$5648).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6780 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6773, Q = $auto$memory_bram.cc:1009:replace_memory$6777).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7043 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7036, Q = $auto$memory_bram.cc:1009:replace_memory$7040).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5664 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5657, Q = $auto$memory_bram.cc:1009:replace_memory$5661).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5677 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5670, Q = $auto$memory_bram.cc:1009:replace_memory$5674).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5690 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5683, Q = $auto$memory_bram.cc:1009:replace_memory$5687).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5703 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5696, Q = $auto$memory_bram.cc:1009:replace_memory$5700).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7173 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7166, Q = $auto$memory_bram.cc:1009:replace_memory$7170).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6304 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6297, Q = $auto$memory_bram.cc:1009:replace_memory$6301).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5716 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5709, Q = $auto$memory_bram.cc:1009:replace_memory$5713).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5737 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5730, Q = $auto$memory_bram.cc:1009:replace_memory$5734).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6801 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6794, Q = $auto$memory_bram.cc:1009:replace_memory$6798).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7363 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7356, Q = $auto$memory_bram.cc:1009:replace_memory$7360).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5750 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5743, Q = $auto$memory_bram.cc:1009:replace_memory$5747).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5763 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5756, Q = $auto$memory_bram.cc:1009:replace_memory$5760).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6317 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6310, Q = $auto$memory_bram.cc:1009:replace_memory$6314).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6814 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6807, Q = $auto$memory_bram.cc:1009:replace_memory$6811).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5776 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5769, Q = $auto$memory_bram.cc:1009:replace_memory$5773).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7186 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7179, Q = $auto$memory_bram.cc:1009:replace_memory$7183).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5789 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5782, Q = $auto$memory_bram.cc:1009:replace_memory$5786).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6473 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6466, Q = $auto$memory_bram.cc:1009:replace_memory$6470).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5802 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5795, Q = $auto$memory_bram.cc:1009:replace_memory$5799).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6827 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6820, Q = $auto$memory_bram.cc:1009:replace_memory$6824).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6330 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6323, Q = $auto$memory_bram.cc:1009:replace_memory$6327).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5815 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5808, Q = $auto$memory_bram.cc:1009:replace_memory$5812).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5828 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5821, Q = $auto$memory_bram.cc:1009:replace_memory$5825).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6840 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6833, Q = $auto$memory_bram.cc:1009:replace_memory$6837).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7272 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7265, Q = $auto$memory_bram.cc:1009:replace_memory$7269).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5841 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5834, Q = $auto$memory_bram.cc:1009:replace_memory$5838).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7199 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7192, Q = $auto$memory_bram.cc:1009:replace_memory$7196).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5854 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5847, Q = $auto$memory_bram.cc:1009:replace_memory$5851).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6343 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6336, Q = $auto$memory_bram.cc:1009:replace_memory$6340).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5867 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5860, Q = $auto$memory_bram.cc:1009:replace_memory$5864).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6853 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6846, Q = $auto$memory_bram.cc:1009:replace_memory$6850).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5880 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5873, Q = $auto$memory_bram.cc:1009:replace_memory$5877).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5893 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5886, Q = $auto$memory_bram.cc:1009:replace_memory$5890).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6866 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6859, Q = $auto$memory_bram.cc:1009:replace_memory$6863).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6356 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6349, Q = $auto$memory_bram.cc:1009:replace_memory$6353).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5906 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5899, Q = $auto$memory_bram.cc:1009:replace_memory$5903).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7212 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7205, Q = $auto$memory_bram.cc:1009:replace_memory$7209).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5919 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5912, Q = $auto$memory_bram.cc:1009:replace_memory$5916).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5932 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5925, Q = $auto$memory_bram.cc:1009:replace_memory$5929).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6879 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6872, Q = $auto$memory_bram.cc:1009:replace_memory$6876).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5945 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5938, Q = $auto$memory_bram.cc:1009:replace_memory$5942).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6369 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6362, Q = $auto$memory_bram.cc:1009:replace_memory$6366).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5958 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5951, Q = $auto$memory_bram.cc:1009:replace_memory$5955).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7017 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7010, Q = $auto$memory_bram.cc:1009:replace_memory$7014).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6892 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6885, Q = $auto$memory_bram.cc:1009:replace_memory$6889).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6486 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6479, Q = $auto$memory_bram.cc:1009:replace_memory$6483).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5971 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5964, Q = $auto$memory_bram.cc:1009:replace_memory$5968).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5984 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5977, Q = $auto$memory_bram.cc:1009:replace_memory$5981).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7376 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7369, Q = $auto$memory_bram.cc:1009:replace_memory$7373).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6382 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6375, Q = $auto$memory_bram.cc:1009:replace_memory$6379).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$5997 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$5990, Q = $auto$memory_bram.cc:1009:replace_memory$5994).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6905 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6898, Q = $auto$memory_bram.cc:1009:replace_memory$6902).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6010 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6003, Q = $auto$memory_bram.cc:1009:replace_memory$6007).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7402 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7395, Q = $auto$memory_bram.cc:1009:replace_memory$7399).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6023 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6016, Q = $auto$memory_bram.cc:1009:replace_memory$6020).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6036 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6029, Q = $auto$memory_bram.cc:1009:replace_memory$6033).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6918 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6911, Q = $auto$memory_bram.cc:1009:replace_memory$6915).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6395 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6388, Q = $auto$memory_bram.cc:1009:replace_memory$6392).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7233 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7226, Q = $auto$memory_bram.cc:1009:replace_memory$7230).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6049 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6042, Q = $auto$memory_bram.cc:1009:replace_memory$6046).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6062 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6055, Q = $auto$memory_bram.cc:1009:replace_memory$6059).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$6408 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$6401, Q = $auto$memory_bram.cc:1009:replace_memory$6405).
|
|
|
|
2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 259 unused cells and 3320 unused wires.
|
|
<suppressed ~260 debug messages>
|
|
|
|
2.30.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.30.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.30.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~372 debug messages>
|
|
Removed a total of 124 cells.
|
|
|
|
2.30.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 124 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.30.10. Finished fast OPT passes.
|
|
|
|
2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
2.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~398 debug messages>
|
|
|
|
2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2617:
|
|
Old ports: A=4'0000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 3'011 }, Y=\core_cpu._zz_130_ [3:0]
|
|
New ports: A=2'00, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 1'1 }, Y={ \core_cpu._zz_130_ [3] \core_cpu._zz_130_ [0] }
|
|
New connections: \core_cpu._zz_130_ [2:1] = { 1'0 \core_cpu._zz_130_ [0] }
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2748:
|
|
Old ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [30:25] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [30:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31:20] }, Y=\core_cpu.execute_BranchPlugin_branch_src2 [19:0]
|
|
New ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [24:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [24:20] }, Y={ \core_cpu.execute_BranchPlugin_branch_src2 [19:11] \core_cpu.execute_BranchPlugin_branch_src2 [4:0] }
|
|
New connections: \core_cpu.execute_BranchPlugin_branch_src2 [10:5] = \core_cpu.decode_to_execute_INSTRUCTION [30:25]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2999:
|
|
Old ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_69_ [7:0] \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated
|
|
New ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated [31:8]
|
|
New connections: \core_cpu.writeBack_DBusSimplePlugin_rspFormated [7:0] = \core_cpu._zz_69_ [7:0]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3016:
|
|
Old ports: A=\core_cpu.decode_to_execute_RS2, B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:0] }, Y=\_zz_20_
|
|
New ports: A=\core_cpu.decode_to_execute_RS2 [31:8], B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:8] }, Y=\_zz_20_ [31:8]
|
|
New connections: \_zz_20_ [7:0] = \core_cpu.decode_to_execute_RS2 [7:0]
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3070:
|
|
Old ports: A=0, B={ \core_cpu.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=30'000000000000000000000000000000, B=\core_cpu.CsrPlugin_mtvec_base, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5697$965:
|
|
Old ports: A=4'0001, B=4'1001, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5697$965_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5697$965_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5697$965_Y [2:0] = 3'001
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5700$966:
|
|
Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$4608 [1:0]
|
|
New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$4608 [0]
|
|
New connections: $auto$wreduce.cc:454:run$4608 [1] = $auto$wreduce.cc:454:run$4608 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969:
|
|
Old ports: A=4'0110, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y [3] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y [1] }
|
|
New connections: { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y [2] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y [0] } = { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5709$969_Y [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5715$971:
|
|
Old ports: A=4'0100, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5715$971_Y
|
|
New ports: A=2'01, B=2'10, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5715$971_Y [3:2]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5715$971_Y [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5721$973:
|
|
Old ports: A=4'1010, B=4'0010, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5721$973_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5721$973_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5721$973_Y [2:0] = 3'010
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5724$974:
|
|
Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$4611 [2:0]
|
|
New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$4611 [2] $auto$wreduce.cc:454:run$4611 [0] }
|
|
New connections: $auto$wreduce.cc:454:run$4611 [1] = $auto$wreduce.cc:454:run$4611 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5730$976:
|
|
Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:454:run$4612 [1:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4612 [1]
|
|
New connections: $auto$wreduce.cc:454:run$4612 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5736$978:
|
|
Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:454:run$4614 [2:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4614 [2]
|
|
New connections: $auto$wreduce.cc:454:run$4614 [1:0] = 2'11
|
|
Consolidated identical input bits for $pmux cell $procmux$1585:
|
|
Old ports: A=4'1111, B=8'00010011, Y=\_zz_22_
|
|
New ports: A=2'11, B=4'0001, Y=\_zz_22_ [2:1]
|
|
New connections: { \_zz_22_ [3] \_zz_22_ [0] } = { \_zz_22_ [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $ternary$PQVexRiscvUlx3s.v:8100$1280:
|
|
Old ports: A={ \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \_zz_7_ [31:2] 2'00 }, Y=$ternary$PQVexRiscvUlx3s.v:8100$1280_Y
|
|
New ports: A=\core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2], B=\_zz_7_ [31:2], Y=$ternary$PQVexRiscvUlx3s.v:8100$1280_Y [31:2]
|
|
New connections: $ternary$PQVexRiscvUlx3s.v:8100$1280_Y [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3062:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B={ \core_cpu.CsrPlugin_mepc [31:2] 2'00 }, Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=\core_cpu.CsrPlugin_mepc [31:2], Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3067:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0], Y=\core_cpu.CsrPlugin_jumpInterface_payload
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\core_cpu.CsrPlugin_jumpInterface_payload [31:2]
|
|
New connections: \core_cpu.CsrPlugin_jumpInterface_payload [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:3787$522:
|
|
Old ports: A={ \core_cpu.execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\core_cpu.CsrPlugin_jumpInterface_payload, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload
|
|
New ports: A=\core_cpu.execute_to_memory_BRANCH_CALC [31:1], B={ \core_cpu.CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1]
|
|
New connections: \core_cpu.IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3043:
|
|
Old ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527_Y [31:2] 2'00 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload, Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] }
|
|
New ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3804$527_Y [31:2] 1'0 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1] }
|
|
New connections: $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 19 changes.
|
|
|
|
2.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
2.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 7 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~5 debug messages>
|
|
|
|
2.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~398 debug messages>
|
|
|
|
2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~398 debug messages>
|
|
|
|
2.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ecp5_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Using extmapper simplemap for cells of type $adff.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $adffe.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc.
|
|
add \core_ibus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_valid (1 bits, unsigned)
|
|
add bits \core_ibus_decoder._zz_5_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
|
|
add { \core_cpu.execute_to_memory_MUL_HH \core_cpu.execute_to_memory_MUL_LL [31:16] } (48 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_LH (32 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_HL (32 bits, unsigned)
|
|
add \core_cpu.memory_to_writeBack_MUL [63:32] (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2551$297_Y (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2550$295_Y (32 bits, unsigned)
|
|
add 2 (32 bits, unsigned)
|
|
packed 2 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=33\B_WIDTH=32\Y_WIDTH=33 for cells of type $alu.
|
|
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
|
|
add \core_dbus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.dBus_rsp_ready (1 bits, unsigned)
|
|
add bits \core_dbus_decoder._zz_6_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=11 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=1\Y_WIDTH=20 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
|
|
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.77. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~2487 debug messages>
|
|
|
|
2.33.78. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~35 debug messages>
|
|
Removed 0 unused cells and 8 unused wires.
|
|
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=9 for cells of type $pmux.
|
|
add \core_cpu.decode_to_execute_SRC1 (32 bits, signed)
|
|
add { 1'0 \core_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
|
|
add \core_cpu._zz_211_ (32 bits, signed)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
add \core_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned)
|
|
add bits \core_cpu.IBusSimplePlugin_pending_inc (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=2 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa.
|
|
Using template $paramod\_90_fa\WIDTH=48 for cells of type $fa.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=3 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~2914 debug messages>
|
|
|
|
2.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~3650 debug messages>
|
|
|
|
2.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~2439 debug messages>
|
|
Removed a total of 813 cells.
|
|
|
|
2.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1251 unused cells and 4530 unused wires.
|
|
<suppressed ~1257 debug messages>
|
|
|
|
2.34.5. Finished fast OPT passes.
|
|
|
|
2.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
2.37. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.37.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
|
|
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
|
|
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
|
|
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
|
|
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
|
|
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_.
|
|
Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_.
|
|
Using template \$_DFFE_PP1N_ for cells of type $_DFFE_PP1N_.
|
|
No more expansions possible.
|
|
<suppressed ~2550 debug messages>
|
|
|
|
2.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~85 debug messages>
|
|
|
|
2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.40. Executing ECP5_GSR pass (implement FF init values).
|
|
Handling GSR in PQVexRiscvUlx3s.
|
|
|
|
2.41. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
2.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 11651 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.44. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.44.1. Extracting gate netlist of module `\PQVexRiscvUlx3s' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 7639 gates and 10178 wires to a netlist network with 2537 inputs and 1709 outputs.
|
|
|
|
2.44.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + dress
|
|
ABC: Total number of equiv classes = 2282.
|
|
ABC: Participating nodes from both networks = 4916.
|
|
ABC: Participating nodes from the first network = 2368. ( 72.33 % of nodes)
|
|
ABC: Participating nodes from the second network = 2548. ( 77.83 % of nodes)
|
|
ABC: Node pairs (any polarity) = 2368. ( 72.33 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 1833. ( 55.99 % of names can be moved)
|
|
ABC: Total runtime = 0.43 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.44.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 3272
|
|
ABC RESULTS: internal signals: 5932
|
|
ABC RESULTS: input signals: 2537
|
|
ABC RESULTS: output signals: 1709
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 5530 unused wires.
|
|
|
|
2.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.45.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2139029631 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65536 for cells of type $lut.
|
|
Using template $paramod$b5cd238a527d851ba52055b76f8b8313ff4d0a1d\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
|
|
Using template $paramod$5d8d75e2855aec517655ab9bafade7767f8236c6\$lut for cells of type $lut.
|
|
Using template $paramod$078354ad4f08d5c6e8687216ff1586f28ff6611c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011100000 for cells of type $lut.
|
|
Using template $paramod$3b5f187c29371f50ea377a8fdd5073832ff55f62\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=386990080 for cells of type $lut.
|
|
Using template $paramod$1922694d1ba66dc9e8c99f5f26ba1b86bfc1d372\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268500992 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=14614528 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=285212671 for cells of type $lut.
|
|
Using template $paramod$ef003d70d3febf7a5568510cba4a0111646430ac\$lut for cells of type $lut.
|
|
Using template $paramod$6aea0429a561ce25f5ecbc7cb2e74bd8a5c0ee5c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16777216 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
|
|
Using template $paramod$d6a97cece58353cd8de5b6e824f1d055bdb32a45\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268435456 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010101010100011111111000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=286326799 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549387 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011000010110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11010000000011010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1090519105 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001100101010101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001100111111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=47883 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429470991 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100000001000000010000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000010010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11100000000000001111000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011101110 for cells of type $lut.
|
|
Using template $paramod$0886e4550c3cbe336cd2a314faa74ba4ea86449c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001010001001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
|
|
Using template $paramod$f6783b5b9c23cd67232c94ac1b12661d5b0309d0\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=5570812 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252641501 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011101100000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429409791 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663244 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001000100011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001011010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110101110001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663091 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000111111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=125239296 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252706696 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
|
|
Using template $paramod$8a245f3265e0f9f561bd9637d36a560d96938f16\$lut for cells of type $lut.
|
|
Using template $paramod$0359540d1441c1182534de6006fa776a0f8fef62\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011111000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100110011001111000010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001111101011110000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod$02e775e4e05600309824f9566ad99816a66efd31\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110111011101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10001000100010001111000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001110101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1145310976 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=285147136 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000011101111111111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001000110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2004287600 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16639 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1431683900 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110111000010001110111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101001010110100 for cells of type $lut.
|
|
Using template $paramod$18012a671859ef22a1189b333f26233b10096373\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268400503 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32767 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=8355711 for cells of type $lut.
|
|
Using template $paramod$3f46e0de0bd7f4e5eb456f109ade71ab8fd0ca8d\$lut for cells of type $lut.
|
|
Using template $paramod$05940a3d027fa3e6541aad757dfaa285558e7fc1\$lut for cells of type $lut.
|
|
Using template $paramod$785017f818f96675cf8dee69b5d27bc9667b3b0e\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111110111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268398592 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1333248160 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196148992 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101011100110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=267444928 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000000100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100111110101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111101001111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101100 for cells of type $lut.
|
|
Using template $paramod$c58fc06784389e3ef9ec4b6af00dedaf86b21965\$lut for cells of type $lut.
|
|
Using template $paramod$b1bd2a921ec0f1ea0cc7578a2bcf32d761c7f62f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100100010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111110000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011010001001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000101010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429467376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000100010000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252654421 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=866840816 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=15724527 for cells of type $lut.
|
|
Using template $paramod$1942501f6ae04890d4dd2518ff37be8fc8822138\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010001111111111111111 for cells of type $lut.
|
|
Using template $paramod$532433d93572414dad0b6e1443f5dc5b7825a690\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101111010000001100110011001100 for cells of type $lut.
|
|
Using template $paramod$1ee2a7579c6186174c99cd3ee563c80621b7120f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10001110011100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111110100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
|
|
Using template $paramod$488828f844c7be1332a09a452d6632f1c0c81e15\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2147450880 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010111100001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
|
|
Using template $paramod$1cd6e35a42cc48d87d00cec628e4a444de672548\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111010000001111010000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2139094784 for cells of type $lut.
|
|
Using template $paramod$66b12b4face4584d4007877a011e27605a6b29bc\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065336832 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=12566463 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073709056 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
|
|
Using template $paramod$d6316c74e45dd31ff50dd80d359f2c3bc033ab74\$lut for cells of type $lut.
|
|
Using template $paramod$760ad8d3fc1e64dbf47551b1e98f431ac046c1d3\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110110110010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100011100001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101011011100001111000011100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111001100000001101111000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1142743210 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011001111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000111110000000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65534 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=33488896 for cells of type $lut.
|
|
Using template $paramod$f340a7e85fbe3e11c384ecf1cd11a7f6ad674e2c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000011111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=251723656 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=51318778 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65344 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101111000000001111111111111111 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~6801 debug messages>
|
|
|
|
2.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in PQVexRiscvUlx3s.
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33328.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32423.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32423.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32827.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32575.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32843.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32839.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32829.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32834.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32848.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32835.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32844.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32840.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32850.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32416.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32416.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32430.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32430.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32458.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32458.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut4 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut6 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut7 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30627.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30627.lut2 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30627.lut3 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32444.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32444.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32409.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32402.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32402.lut3 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32393.lut2 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31015.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31015.lut2 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31015.lut3 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32364.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31244.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31428.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31509.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31509.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31522.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32451.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32451.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32245.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32286.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32300.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32437.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32437.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32652.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32652.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32668.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32668.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32668.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32654.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32654.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31162.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31162.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31162.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32313.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32644.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32644.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32637.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32624.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32624.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32624.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30381.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31059.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31059.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31240.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31228.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31195.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31195.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31184.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31184.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31173.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31173.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32188.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30484.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30484.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut5 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut7 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32847.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32842.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32837.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32831.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32826.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32686.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32646.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32646.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut5 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut7 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32351.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32351.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32347.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32347.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32218.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32213.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32192.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32182.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32112.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32240.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32232.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32205.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32191.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32234.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32186.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32194.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32193.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31513.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31513.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31513.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32136.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32144.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32135.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32139.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32130.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32143.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32126.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32134.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32125.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32138.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32129.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32124.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32115.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32110.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32095.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31504.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31151.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31151.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31116.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31116.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31665.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31640.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31381.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31257.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31242.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31206.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31206.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32638.lut2 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32638.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31105.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31105.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31070.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31070.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30644.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut7 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31026.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31026.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31026.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30651.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30905.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30938.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30958.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30958.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30958.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30979.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30979.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30980.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30685.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31003.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31003.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31355.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31355.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31351.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31351.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30662.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30648.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31325.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31325.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31329.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31329.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31309.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31309.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31299.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31299.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31285.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31285.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30709.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31281.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31281.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30705.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31289.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31289.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30713.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30697.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut6 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut7 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31259.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31259.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31259.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30679.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32189.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32207.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32212.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32200.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32219.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut3 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut5 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut7 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut5 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut7 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut5 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut7 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut2 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut3 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut4 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut5 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut2 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut3 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut4 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut5 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30322.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30322.lut4 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30322.lut6 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut2 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut3 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut4 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut5 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut6 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30216.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30216.lut2 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30216.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30213.lut3 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30199.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30193.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30195.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30207.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30211.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30213.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30215.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30216.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30213.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30221.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30225.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30236.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30266.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30282.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30275.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30277.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30301.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30292.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30292.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30301.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30322.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30326.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30315.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30344.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32768.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30362.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30367.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30381.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30382.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30387.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30393.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30390.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30400.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30404.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30408.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30426.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30441.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30441.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32230.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30456.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30462.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32252.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30471.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30473.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30474.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30477.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32235.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30481.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30482.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30484.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30485.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30489.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32229.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30507.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32225.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30506.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30519.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30521.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30537.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30557.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31617.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30572.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30583.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31626.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30596.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32838.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30613.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30613.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30615.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30615.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30330.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30625.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30627.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30631.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30634.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30644.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30648.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30651.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30654.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30654.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30655.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30658.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30658.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30659.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30662.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30663.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30666.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30666.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30667.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30670.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30670.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30671.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30674.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30674.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30675.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30678.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30678.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30679.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30685.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30689.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30693.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30697.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30701.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30705.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30709.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30710.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30713.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30719.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30722.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30725.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30728.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30731.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30734.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30737.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30740.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30743.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30746.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30749.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30752.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30755.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30758.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30761.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30765.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30768.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30771.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32585.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30774.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30777.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30917.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30780.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30783.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30786.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30950.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30789.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30792.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30795.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30798.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31264.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30801.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30804.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30701.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30807.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30810.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30813.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30816.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31293.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30819.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30822.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31303.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30825.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30828.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31313.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30831.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30834.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30837.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30840.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31333.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30843.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30846.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30849.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30852.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30855.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30858.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30861.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30861.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31365.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30878.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30879.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30880.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30887.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30894.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30895.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30896.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30905.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30916.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30917.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30663.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30928.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30929.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30929.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30937.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30938.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30948.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30948.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30950.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30952.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30958.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30959.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30979.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30959.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30979.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30980.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30969.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30990.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31003.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31003.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31015.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31540.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31026.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30886.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31281.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31285.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31047.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31047.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31036.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31289.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31059.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31059.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30860.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31070.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31299.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31081.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31070.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31081.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31093.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30896.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31309.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31105.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30887.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31093.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31116.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31116.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31127.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31127.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31325.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31139.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31139.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31329.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31151.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31162.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31173.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31173.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31345.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31184.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31184.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31246.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31195.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31195.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31355.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31206.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31217.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31206.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31217.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31226.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31228.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31236.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31239.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31240.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31242.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31244.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31246.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31227.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31249.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31253.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31253.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31256.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31257.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31249.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31259.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31656.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31264.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31256.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31268.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30693.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31272.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31277.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31268.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31281.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31274.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31285.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31289.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31293.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31299.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31303.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31309.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31313.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31319.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31319.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31325.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31329.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31333.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31339.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31339.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31345.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30667.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31351.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31351.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31355.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31359.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31359.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31365.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31377.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31370.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31373.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31375.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31377.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31379.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31386.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31381.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31373.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31384.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31386.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31388.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31390.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31379.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31392.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31394.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31402.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31396.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31370.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31398.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31400.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31384.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31402.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31404.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31412.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31406.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31408.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31410.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31412.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31414.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31422.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31416.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31418.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31420.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31422.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31424.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31420.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31426.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31428.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31430.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31430.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31418.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32111.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31481.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31485.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31516.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31506.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31516.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31522.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31528.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31534.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31546.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31540.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31272.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31546.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31552.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31534.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31558.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31552.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31564.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31576.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31570.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31576.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31558.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31582.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31564.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31588.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31582.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31601.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31601.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31588.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31609.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31570.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31617.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31625.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31626.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31609.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31625.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31640.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31648.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31656.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31664.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31665.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31672.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31678.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31684.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31696.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31690.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31696.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31678.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31702.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31684.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31708.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31702.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31690.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31708.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30655.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30659.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30671.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30675.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30689.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31396.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31406.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31392.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31398.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31375.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31388.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31408.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31394.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31416.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31404.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31426.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31414.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31151.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31995.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31995.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31513.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30471.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30473.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32089.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32083.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31506.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32095.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32100.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32110.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32111.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32112.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32113.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32114.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32115.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32116.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32117.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32113.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32117.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32114.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32124.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32125.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32126.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32129.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32130.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32131.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32116.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32134.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32135.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32136.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32137.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32138.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32139.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32140.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32140.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32143.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32144.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32145.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32146.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32131.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32185.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32137.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32145.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32146.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32190.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32182.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32185.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32186.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32187.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32188.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32189.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32190.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32191.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32192.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32193.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32194.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32195.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32206.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31410.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32200.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32201.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32202.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32202.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32205.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32206.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32207.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32212.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32213.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32201.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32218.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32219.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32224.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32224.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32225.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32228.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32229.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32230.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32231.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32232.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32233.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32234.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32235.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32244.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32233.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32240.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32241.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32244.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32245.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32259.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32195.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32252.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32259.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30474.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32266.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32271.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32274.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32277.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32278.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32279.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32280.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32281.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32286.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32287.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32287.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32294.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32295.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32300.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32307.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32308.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32308.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32313.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32314.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32315.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32318.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32339.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32315.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32622.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32324.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32330.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32330.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32334.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32338.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32338.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32331.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32318.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32343.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32347.lut0 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32347.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32354.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32358.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32361.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32346.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32364.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32367.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32357.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32371.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32375.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32382.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32379.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32391.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32393.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31672.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32402.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32405.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32409.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32410.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32414.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32416.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32266.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32419.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32423.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32426.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33187.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32430.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32433.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32437.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32440.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32444.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32447.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32451.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32454.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32281.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32458.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31243.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32461.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32295.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32475.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32476.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32477.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32482.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32479.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32478.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31528.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32371.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32409.lut1 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32277.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32538.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32537.lut1 (4 -> 2)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32854.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32833.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32828.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32564.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32565.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32849.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32575.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32652.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31390.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32609.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30904.lut1 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32613.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32614.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32622.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32623.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32624.lut0 (4 -> 0)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32628.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32626.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32627.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32628.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32629.lut0 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32630.lut0 (4 -> 1)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32629.lut1 (4 -> 3)
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32633.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32635.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32626.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32637.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32638.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32640.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32642.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32644.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32646.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32648.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32650.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32646.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32652.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32314.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32654.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32656.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32658.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32660.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32323.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32662.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32664.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32666.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32668.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32228.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32187.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32686.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32687.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32688.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32689.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32690.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32691.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32692.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32693.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32691.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31245.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32703.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32704.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32707.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32708.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32709.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32713.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32715.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32717.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32719.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32721.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32723.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32725.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32727.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32729.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32731.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32733.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32735.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32737.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32739.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32741.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32743.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32745.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32820.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32747.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32750.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32836.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32756.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32825.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32762.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31105.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32271.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32798.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32804.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32815.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32820.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32825.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32826.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32827.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32828.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32829.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32830.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32831.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32832.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32833.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32834.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32835.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32836.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32837.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32838.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32839.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32840.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32841.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32842.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32843.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32844.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32845.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32846.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32847.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32848.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32849.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32850.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32851.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32852.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32853.lut0 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32854.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32845.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32853.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32852.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32851.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32393.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32279.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32278.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32307.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32687.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32688.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32689.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32690.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32692.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32693.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32294.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32654.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30381.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32231.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31400.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32466.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31664.lut1 (4 -> 3)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31424.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31648.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33246.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$31241.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32539.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32241.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32623.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32274.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32644.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32638.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32815.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$30626.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32810.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32627.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32846.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32832.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32841.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32830.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32385.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32378.lut1 (4 -> 0)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33185.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33187.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33189.lut1 (4 -> 1)
|
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Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33189.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33214.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33214.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33219.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33219.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33246.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33248.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33248.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33265.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33265.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$32280.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33283.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33283.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33334.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33309.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33326.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33309.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33315.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33315.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33337.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33321.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33321.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33326.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33328.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33331.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33331.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33334.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33339.lut1 (4 -> 1)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33337.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33339.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33341.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30181$auto$blifparse.cc:498:parse_blif$33341.lut1 (4 -> 1)
|
|
Removed 0 unused cells and 7165 unused wires.
|
|
|
|
2.47. Executing AUTONAME pass.
|
|
Renamed 144346 objects in module PQVexRiscvUlx3s (109 iterations).
|
|
<suppressed ~11022 debug messages>
|
|
|
|
2.48. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.48.1. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
|
|
2.48.2. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Removed 0 unused modules.
|
|
|
|
2.49. Printing statistics.
|
|
|
|
=== PQVexRiscvUlx3s ===
|
|
|
|
Number of wires: 4932
|
|
Number of wire bits: 24030
|
|
Number of public wires: 4932
|
|
Number of public wire bits: 24030
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 7762
|
|
CCU2C 236
|
|
DP16KD 192
|
|
L6MUX21 136
|
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LUT4 4036
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MULT18X18D 4
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PFUMX 701
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TRELLIS_DPR16X4 38
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TRELLIS_FF 2419
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2.50. Executing CHECK pass (checking for obvious problems).
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Checking module PQVexRiscvUlx3s...
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Found and reported 0 problems.
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2.51. Executing JSON backend.
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Warnings: 1 unique messages, 2 total
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End of script. Logfile hash: 081984a646, CPU: user 30.44s system 1.19s, MEM: 2346.27 MB peak
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Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
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Time spent: 24% 8x techmap (8 sec), 19% 30x opt_clean (6 sec), ...
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