Thorsten
/
vexriscv_mem_mapped_example
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
10 Commits
1 Branch
6.8 MiB
Tree: 78b34dd5dd
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '78b34dd5dd'
${ noResults }
vexriscv_mem_mapped_example/c_project/pqvexriscvsim.ld

14 lines
274 B
Raw Normal View History

first tiny mem-mapped example is working
4 years ago
​
​
​
​
working c for ulx3s and sim
4 years ago
first tiny mem-mapped example is working
4 years ago
​
​
working c for ulx3s and sim
4 years ago
​
first tiny mem-mapped example is working
4 years ago
​
working c for ulx3s and sim
4 years ago
 
  1. OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
  2. OUTPUT_ARCH(riscv)
  3. 

  4. ENTRY( _start )
  5. 

  6. __ram_size = 128K;
  7. 

  8. MEMORY
  9. {
  10.   rom (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
  11.   ram (wxa!ri) : ORIGIN = 0x80020000, LENGTH = 64K
  12. }
  13. 

  14. INCLUDE volatile-split.ld