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vexriscv_mem_mapped_aes128
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A VexRiscv with AES128 on the memory mapped bus. Works in simulation and on the ULX3S.
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376 KiB
Verilog
87%
C
7.8%
Scala
3.9%
Makefile
0.9%
Assembly
0.4%
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sbt.version=1.3.13