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24308 lines
3.0 MiB
24308 lines
3.0 MiB
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
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-- Parsing `PQVexRiscvUlx3s.v' using frontend `verilog' --
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1. Executing Verilog-2005 frontend: PQVexRiscvUlx3s.v
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Parsing Verilog input from `PQVexRiscvUlx3s.v' to AST representation.
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Generating RTLIL representation for module `\BufferCC'.
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Generating RTLIL representation for module `\BufferCC_1_'.
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Generating RTLIL representation for module `\UartCtrlTx'.
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Generating RTLIL representation for module `\UartCtrlRx'.
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Generating RTLIL representation for module `\AESEngine_Std'.
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Generating RTLIL representation for module `\AESKeyScheduleCore_Std'.
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Generating RTLIL representation for module `\StreamFifoLowLatency'.
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Generating RTLIL representation for module `\FlowCCByToggle'.
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Generating RTLIL representation for module `\UartCtrl'.
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Generating RTLIL representation for module `\StreamFifo'.
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Generating RTLIL representation for module `\AESCore_Std'.
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Generating RTLIL representation for module `\StreamArbiter'.
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Generating RTLIL representation for module `\StreamFork'.
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Generating RTLIL representation for module `\StreamFifoLowLatency_1_'.
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Generating RTLIL representation for module `\StreamArbiter_1_'.
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Generating RTLIL representation for module `\StreamFork_1_'.
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Generating RTLIL representation for module `\BufferCC_2_'.
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Generating RTLIL representation for module `\VexRiscv'.
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Generating RTLIL representation for module `\JtagBridge'.
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Generating RTLIL representation for module `\SystemDebugger'.
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Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'.
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Generating RTLIL representation for module `\Apb3UartCtrl'.
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Generating RTLIL representation for module `\MyMem'.
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Generating RTLIL representation for module `\Apb3Decoder'.
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Generating RTLIL representation for module `\Apb3Router'.
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Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s'.
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Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder'.
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Generating RTLIL representation for module `\PipelinedMemoryBusDecoder_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_1_'.
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Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_2_'.
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Generating RTLIL representation for module `\PQVexRiscvUlx3s'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -top PQVexRiscvUlx3s -json PQVexRiscvUlx3s.json' --
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2. Executing SYNTH_ECP5 pass.
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2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_SLICE'.
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Generating RTLIL representation for module `\DP16KD'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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2.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\DCUA'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Successfully finished Verilog frontend.
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2.3. Executing HIERARCHY pass (managing design hierarchy).
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2.3.1. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_2_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork_1_
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Used module: \StreamArbiter_1_
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s_1_
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \AESCore_Std
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Used module: \AESKeyScheduleCore_Std
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Used module: \AESEngine_Std
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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2.3.2. Analyzing design hierarchy..
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Top module: \PQVexRiscvUlx3s
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Used module: \PipelinedMemoryBusArbiter_2_
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Used module: \StreamFifoLowLatency_1_
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Used module: \StreamFork_1_
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Used module: \StreamArbiter_1_
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Used module: \PipelinedMemoryBusArbiter_1_
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Used module: \StreamFork
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Used module: \StreamArbiter
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Used module: \PipelinedMemoryBusArbiter
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Used module: \PipelinedMemoryBusDecoder_1_
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Used module: \PipelinedMemoryBusDecoder
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Used module: \PipelinedMemoryBusRamUlx3s_1_
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Used module: \PipelinedMemoryBusRamUlx3s
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Used module: \Apb3Router
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Used module: \Apb3Decoder
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Used module: \MyMem
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Used module: \AESCore_Std
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Used module: \AESKeyScheduleCore_Std
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Used module: \AESEngine_Std
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Used module: \Apb3UartCtrl
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Used module: \StreamFifo
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Used module: \UartCtrl
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Used module: \UartCtrlRx
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Used module: \BufferCC
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Used module: \UartCtrlTx
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Used module: \PipelinedMemoryBusToApbBridge
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Used module: \SystemDebugger
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Used module: \JtagBridge
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Used module: \FlowCCByToggle
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Used module: \BufferCC_1_
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Used module: \VexRiscv
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Used module: \StreamFifoLowLatency
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Used module: \BufferCC_2_
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Removed 0 unused modules.
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2.4. Executing PROC pass (convert processes to netlists).
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2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$2055'.
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Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:0$706'.
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Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:0$705'.
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Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:0$664'.
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Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:0$663'.
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Cleaned up 1 empty switch.
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2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$2136 in module TRELLIS_FF.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:12539$1908 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:12480$1895 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:12430$1888 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:12408$1883 in module PQVexRiscvUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11851$1876 in module PipelinedMemoryBusArbiter_2_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11844$1875 in module PipelinedMemoryBusArbiter_2_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11698$1872 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11691$1871 in module PipelinedMemoryBusArbiter_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11515$1867 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11503$1849 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11490$1845 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11477$1841 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11465$1838 in module PipelinedMemoryBusDecoder_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11393$1830 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11381$1809 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11368$1805 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11355$1801 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11342$1797 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11327$1794 in module PipelinedMemoryBusDecoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11252$1782 in module PipelinedMemoryBusRamUlx3s_1_.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11184$1742 in module PipelinedMemoryBusRamUlx3s.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11091$1708 in module Apb3Router.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11047$1707 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:11039$1706 in module Apb3Decoder.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10875$1695 in module MyMem.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10823$1682 in module MyMem.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10694$1673 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10674$1672 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10657$1671 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10640$1670 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10623$1669 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10606$1668 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10586$1663 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10578$1662 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10571$1661 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10551$1660 in module Apb3UartCtrl.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10515$1645 in module Apb3UartCtrl.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10325$1640 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10315$1637 in module PipelinedMemoryBusToApbBridge.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10301$1635 in module PipelinedMemoryBusToApbBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10246$1631 in module SystemDebugger.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10220$1627 in module SystemDebugger.
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Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10109$1610 in module JtagBridge.
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Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10081$1607 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:10027$1590 in module JtagBridge.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9803$1582 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9188$1426 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9179$1417 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9172$1416 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9165$1415 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9158$1414 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9150$1413 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9142$1412 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9133$1411 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9124$1410 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9115$1409 in module VexRiscv.
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Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9096$1408 in module VexRiscv.
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Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9028$1354 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:9017$1352 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8994$1351 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8970$1339 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8961$1336 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8952$1335 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8935$1330 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8921$1329 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8892$1324 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8812$1318 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8800$1311 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8764$1302 in module VexRiscv.
|
|
Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8736$1300 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8656$1292 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8639$1291 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8574$1288 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8560$1287 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8546$1283 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8537$1281 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8501$1260 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8487$1244 in module VexRiscv.
|
|
Marked 16 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8440$1239 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8427$1237 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8416$1236 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8406$1233 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8391$1227 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8377$1226 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8310$1219 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8294$1217 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8279$1216 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8269$1206 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8245$1197 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8210$1185 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8189$1179 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8163$1161 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8145$1155 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8136$1153 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8129$1152 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8121$1150 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8110$1146 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8103$1144 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8096$1143 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8080$1142 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8070$1141 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8063$1140 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8052$1138 in module VexRiscv.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8031$1137 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8017$1136 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8009$1135 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8000$1134 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7992$1133 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7979$1123 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7970$1122 in module VexRiscv.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7961$1121 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7954$1120 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7947$1119 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7935$1111 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7926$1110 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7913$1100 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7894$1099 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7883$1098 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7855$1095 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7840$1094 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7833$1092 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7825$1090 in module VexRiscv.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7787$1089 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7756$1087 in module VexRiscv.
|
|
Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7726$1085 in module VexRiscv.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5837$867 in module StreamFork_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5817$860 in module StreamFork_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5769$857 in module StreamArbiter_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5696$840 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5688$836 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5668$825 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5659$822 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5652$821 in module StreamFifoLowLatency_1_.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5641$819 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5632$816 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5625$815 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5618$814 in module StreamFifoLowLatency_1_.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5545$804 in module StreamFork.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5525$797 in module StreamFork.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5477$794 in module StreamArbiter.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5347$776 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5329$758 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5320$755 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5313$754 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5306$752 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5297$749 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5290$748 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5283$747 in module StreamFifo.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5208$737 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5193$736 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5186$735 in module UartCtrl.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5089$732 in module FlowCCByToggle.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5015$725 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5006$723 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4998$722 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4989$721 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4974$713 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4967$712 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4958$710 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4951$709 in module StreamFifoLowLatency.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4944$708 in module StreamFifoLowLatency.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4862$697 in module AESKeyScheduleCore_Std.
|
|
Marked 4 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4826$694 in module AESKeyScheduleCore_Std.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4814$693 in module AESKeyScheduleCore_Std.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4117$617 in module AESEngine_Std.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4066$614 in module AESEngine_Std.
|
|
Marked 13 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4002$612 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3759$558 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3750$554 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3743$553 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3724$552 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3705$551 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3686$550 in module AESEngine_Std.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3665$549 in module AESEngine_Std.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3598$547 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3502$545 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3449$544 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3396$543 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3343$542 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3290$541 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3237$540 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3184$539 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3131$538 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3078$537 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3025$536 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2972$535 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2919$534 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2866$533 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2813$532 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2760$531 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2707$530 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2654$529 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2601$528 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2548$527 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2495$526 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2442$525 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2389$524 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2336$523 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2283$522 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2230$521 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2177$520 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2124$519 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2071$518 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:2018$517 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1965$516 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1912$515 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1859$514 in module AESEngine_Std.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1806$513 in module AESEngine_Std.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:565$61 in module UartCtrlRx.
|
|
Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:486$43 in module UartCtrlRx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:473$41 in module UartCtrlRx.
|
|
Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:443$39 in module UartCtrlRx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:272$14 in module UartCtrlTx.
|
|
Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:250$13 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:231$11 in module UartCtrlTx.
|
|
Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:220$9 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:210$6 in module UartCtrlTx.
|
|
Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:109$1 in module BufferCC.
|
|
Removed a total of 0 dead cases.
|
|
|
|
2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 34 redundant assignments.
|
|
Promoted 454 assignments to connections.
|
|
|
|
2.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2140'.
|
|
Set init value: \Q = 1'0
|
|
Found init rule in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:9915$1622'.
|
|
Set init value: \jtag_tap_fsm_state = 4'0000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:6515$1587'.
|
|
Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:6514$1586'.
|
|
Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
|
|
Found init rule in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5050$733'.
|
|
Set init value: \inputArea_target = 1'0
|
|
|
|
2.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
Found async reset \resetCtrl_mainClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12539$1908'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11515$1867'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11393$1830'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11252$1782'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11184$1742'.
|
|
Found async reset \resetCtrl_systemClockReset in `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
Found async reset \resetCtrl_systemClockReset in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
Found async reset \resetCtrl_mainClockReset in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
Found async reset \resetCtrl_mainClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
Found async reset \resetCtrl_systemClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5769$857'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5477$794'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5208$737'.
|
|
Found async reset \resetCtrl_mainClockReset in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5089$732'.
|
|
Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5015$725'.
|
|
Found async reset \resetCtrl_systemClockReset in `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
Found async reset \resetCtrl_systemClockReset in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
Found async reset \resetCtrl_systemClockReset in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
Found async reset \resetCtrl_systemClockReset in `\BufferCC.$proc$PQVexRiscvUlx3s.v:109$1'.
|
|
|
|
2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2140'.
|
|
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$2136'.
|
|
1/1: $0\Q[0:0]
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2133'.
|
|
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
1/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_EN[3:0]$2115
|
|
2/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_DATA[3:0]$2114
|
|
3/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_ADDR[3:0]$2113
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2078'.
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
1/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_EN[3:0]$2059
|
|
2/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_DATA[3:0]$2058
|
|
3/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_ADDR[3:0]$2057
|
|
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$2055'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12539$1908'.
|
|
1/1: $0\_zz_35_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12535$1907'.
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
1/16: $0\_zz_34_[3:0]
|
|
2/16: $0\_zz_33_[31:0]
|
|
3/16: $0\_zz_32_[31:0]
|
|
4/16: $0\_zz_31_[0:0]
|
|
5/16: $0\_zz_28_[3:0]
|
|
6/16: $0\_zz_27_[31:0]
|
|
7/16: $0\_zz_26_[31:0]
|
|
8/16: $0\_zz_25_[0:0]
|
|
9/16: $0\_zz_15_[3:0]
|
|
10/16: $0\_zz_14_[31:0]
|
|
11/16: $0\_zz_13_[31:0]
|
|
12/16: $0\_zz_12_[0:0]
|
|
13/16: $0\_zz_9_[3:0]
|
|
14/16: $0\_zz_8_[31:0]
|
|
15/16: $0\_zz_7_[31:0]
|
|
16/16: $0\_zz_6_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
1/4: $0\_zz_30_[0:0]
|
|
2/4: $0\_zz_24_[0:0]
|
|
3/4: $0\_zz_11_[0:0]
|
|
4/4: $0\_zz_5_[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12472$1894'.
|
|
1/1: $0\resetCtrl_systemClockReset[0:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12430$1888'.
|
|
1/1: $1\_zz_22_[3:0]
|
|
Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12408$1883'.
|
|
1/1: $1\core_externalInterrupt[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11851$1876'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11844$1875'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11698$1872'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11691$1871'.
|
|
1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11523$1869'.
|
|
1/2: $0\logic_rspHits_1[0:0]
|
|
2/2: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11515$1867'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11503$1849'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11490$1845'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11477$1841'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11465$1838'.
|
|
1/1: $1\_zz_3_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
1/3: $0\logic_rspHits_2[0:0]
|
|
2/3: $0\logic_rspHits_1[0:0]
|
|
3/3: $0\logic_rspHits_0[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11393$1830'.
|
|
1/1: $0\logic_rspPendingCounter[1:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11381$1809'.
|
|
1/1: $1\io_input_cmd_ready[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11368$1805'.
|
|
1/1: $1\io_outputs_2_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11355$1801'.
|
|
1/1: $1\io_outputs_1_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11342$1797'.
|
|
1/1: $1\io_outputs_0_cmd_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11327$1794'.
|
|
1/1: $1\_zz_4_[31:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11252$1782'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_DATA[7:0]$1762
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_ADDR[14:0]$1761
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_DATA[7:0]$1765
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_ADDR[14:0]$1764
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_DATA[7:0]$1768
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_ADDR[14:0]$1767
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_DATA[7:0]$1771
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_ADDR[14:0]$1770
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11220$1754'.
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11184$1742'.
|
|
1/1: $0\_zz_1_[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723
|
|
2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_DATA[7:0]$1722
|
|
3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_ADDR[15:0]$1721
|
|
4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726
|
|
5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_DATA[7:0]$1725
|
|
6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_ADDR[15:0]$1724
|
|
7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729
|
|
8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_DATA[7:0]$1728
|
|
9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_ADDR[15:0]$1727
|
|
10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732
|
|
11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_DATA[7:0]$1731
|
|
12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_ADDR[15:0]$1730
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
1/4: $0\_zz_8_[7:0]
|
|
2/4: $0\_zz_7_[7:0]
|
|
3/4: $0\_zz_6_[7:0]
|
|
4/4: $0\_zz_5_[7:0]
|
|
Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11152$1714'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11120$1709'.
|
|
Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
|
|
1/3: $1\_zz_4_[0:0]
|
|
2/3: $1\_zz_3_[31:0]
|
|
3/3: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11047$1707'.
|
|
1/1: $1\io_input_PSLVERROR[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11039$1706'.
|
|
1/1: $1\io_input_PREADY[0:0]
|
|
Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11034$1699'.
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
1/10: $0\_zz_2_[127:0] [127:96]
|
|
2/10: $0\_zz_2_[127:0] [95:64]
|
|
3/10: $0\_zz_2_[127:0] [63:32]
|
|
4/10: $0\_zz_2_[127:0] [31:0]
|
|
5/10: $0\_zz_1_[127:0] [95:64]
|
|
6/10: $0\_zz_1_[127:0] [63:32]
|
|
7/10: $0\_zz_1_[127:0] [31:0]
|
|
8/10: $0\_zz_5_[127:0]
|
|
9/10: $0\_zz_3_[0:0]
|
|
10/10: $0\_zz_1_[127:0] [127:96]
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
1/3: $0\_zz_8_[0:0]
|
|
2/3: $0\_zz_6_[0:0]
|
|
3/3: $0\_zz_4_[0:0]
|
|
Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:10823$1682'.
|
|
1/2: $1\io_bus_PRDATA[31:0] [31:1]
|
|
2/2: $1\io_bus_PRDATA[31:0] [0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1679'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10754$1678'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
1/6: $0\bridge_misc_doBreak[0:0]
|
|
2/6: $0\bridge_misc_breakDetected[0:0]
|
|
3/6: $0\bridge_misc_readOverflowError[0:0]
|
|
4/6: $0\bridge_misc_readError[0:0]
|
|
5/6: $0\bridge_interruptCtrl_readIntEnable[0:0]
|
|
6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10674$1672'.
|
|
1/2: $2\_zz_6_[0:0]
|
|
2/2: $1\_zz_6_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10657$1671'.
|
|
1/2: $2\_zz_5_[0:0]
|
|
2/2: $1\_zz_5_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10640$1670'.
|
|
1/2: $2\_zz_4_[0:0]
|
|
2/2: $1\_zz_4_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10623$1669'.
|
|
1/2: $2\_zz_3_[0:0]
|
|
2/2: $1\_zz_3_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10606$1668'.
|
|
1/2: $2\_zz_2_[0:0]
|
|
2/2: $1\_zz_2_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10586$1663'.
|
|
1/2: $2\bridge_read_streamBreaked_ready[0:0]
|
|
2/2: $1\bridge_read_streamBreaked_ready[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10578$1662'.
|
|
1/1: $1\_zz_8_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10571$1661'.
|
|
1/1: $1\bridge_read_streamBreaked_valid[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10551$1660'.
|
|
1/2: $2\_zz_1_[0:0]
|
|
2/2: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10547$1659'.
|
|
Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10515$1645'.
|
|
1/9: $2\io_apb_PRDATA[20:15] [5:2]
|
|
2/9: $1\io_apb_PRDATA[9:0] [7:2]
|
|
3/9: $2\io_apb_PRDATA[20:15] [1]
|
|
4/9: $1\io_apb_PRDATA[9:0] [8]
|
|
5/9: $2\io_apb_PRDATA[20:15] [0]
|
|
6/9: $1\io_apb_PRDATA[9:0] [1]
|
|
7/9: $3\io_apb_PRDATA[28:24]
|
|
8/9: $1\io_apb_PRDATA[9:0] [9]
|
|
9/9: $1\io_apb_PRDATA[9:0] [0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10341$1641'.
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
1/2: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0]
|
|
2/2: $0\state[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10315$1637'.
|
|
1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0]
|
|
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10301$1635'.
|
|
1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10246$1631'.
|
|
1/2: $0\dispatcher_headerShifter[7:0]
|
|
2/2: $0\dispatcher_dataShifter[66:0]
|
|
Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
1/3: $0\dispatcher_counter[2:0]
|
|
2/3: $0\dispatcher_headerLoaded[0:0]
|
|
3/3: $0\dispatcher_dataLoaded[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:9915$1622'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10170$1621'.
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
1/4: $0\jtag_readArea_shifter[33:0]
|
|
2/4: $0\jtag_idcodeArea_shifter[31:0]
|
|
3/4: $0\jtag_tap_instructionShift[3:0]
|
|
4/4: $0\jtag_tap_instruction[3:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
1/3: $0\system_rsp_payload_data[31:0]
|
|
2/3: $0\system_rsp_payload_error[0:0]
|
|
3/3: $0\system_rsp_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10109$1610'.
|
|
1/2: $2\jtag_writeArea_source_valid[0:0]
|
|
2/2: $1\jtag_writeArea_source_valid[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10081$1607'.
|
|
1/5: $5\jtag_tap_tdoUnbufferd[0:0]
|
|
2/5: $4\jtag_tap_tdoUnbufferd[0:0]
|
|
3/5: $3\jtag_tap_tdoUnbufferd[0:0]
|
|
4/5: $2\jtag_tap_tdoUnbufferd[0:0]
|
|
5/5: $1\jtag_tap_tdoUnbufferd[0:0]
|
|
Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10027$1590'.
|
|
1/1: $1\_zz_1_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:6515$1587'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:6514$1586'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
1/8: $0\DebugPlugin_hardwareBreakpoints_2_valid[0:0]
|
|
2/8: $0\DebugPlugin_hardwareBreakpoints_1_valid[0:0]
|
|
3/8: $0\DebugPlugin_hardwareBreakpoints_0_valid[0:0]
|
|
4/8: $0\DebugPlugin_haltedByBreak[0:0]
|
|
5/8: $0\DebugPlugin_godmode[0:0]
|
|
6/8: $0\DebugPlugin_stepIt[0:0]
|
|
7/8: $0\DebugPlugin_haltIt[0:0]
|
|
8/8: $0\DebugPlugin_resetIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
1/5: $0\DebugPlugin_firstCycle[0:0]
|
|
2/5: $0\DebugPlugin_busReadDataReg[31:0]
|
|
3/5: $0\DebugPlugin_hardwareBreakpoints_2_pc[30:0]
|
|
4/5: $0\DebugPlugin_hardwareBreakpoints_1_pc[30:0]
|
|
5/5: $0\DebugPlugin_hardwareBreakpoints_0_pc[30:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
1/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [32]
|
|
2/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [31:0]
|
|
3/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [64:32]
|
|
4/92: $0\execute_CsrPlugin_csr_2946[0:0]
|
|
5/92: $0\execute_CsrPlugin_csr_2818[0:0]
|
|
6/92: $0\execute_CsrPlugin_csr_2944[0:0]
|
|
7/92: $0\execute_CsrPlugin_csr_2816[0:0]
|
|
8/92: $0\execute_CsrPlugin_csr_834[0:0]
|
|
9/92: $0\execute_CsrPlugin_csr_773[0:0]
|
|
10/92: $0\execute_CsrPlugin_csr_772[0:0]
|
|
11/92: $0\execute_CsrPlugin_csr_836[0:0]
|
|
12/92: $0\execute_CsrPlugin_csr_768[0:0]
|
|
13/92: $0\decode_to_execute_IS_RS1_SIGNED[0:0]
|
|
14/92: $0\memory_to_writeBack_MUL[63:0]
|
|
15/92: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
|
|
16/92: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
|
|
17/92: $0\decode_to_execute_BRANCH_CTRL[1:0]
|
|
18/92: $0\execute_to_memory_MUL_HH[31:0]
|
|
19/92: $0\execute_to_memory_MUL_HL[31:0]
|
|
20/92: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
|
|
21/92: $0\execute_to_memory_MEMORY_ENABLE[0:0]
|
|
22/92: $0\decode_to_execute_MEMORY_ENABLE[0:0]
|
|
23/92: $0\execute_to_memory_IS_DIV[0:0]
|
|
24/92: $0\decode_to_execute_IS_DIV[0:0]
|
|
25/92: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
|
|
26/92: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
|
|
27/92: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
|
|
28/92: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
|
|
29/92: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
30/92: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
|
|
31/92: $0\execute_to_memory_SHIFT_RIGHT[31:0]
|
|
32/92: $0\execute_to_memory_MUL_LH[31:0]
|
|
33/92: $0\memory_to_writeBack_SRC2[31:0]
|
|
34/92: $0\execute_to_memory_SRC2[31:0]
|
|
35/92: $0\decode_to_execute_SRC2[31:0]
|
|
36/92: $0\memory_to_writeBack_SRC1[31:0]
|
|
37/92: $0\execute_to_memory_SRC1[31:0]
|
|
38/92: $0\decode_to_execute_SRC1[31:0]
|
|
39/92: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
|
|
40/92: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
|
|
41/92: $0\execute_to_memory_BRANCH_CALC[31:0]
|
|
42/92: $0\memory_to_writeBack_IS_MUL[0:0]
|
|
43/92: $0\execute_to_memory_IS_MUL[0:0]
|
|
44/92: $0\decode_to_execute_IS_MUL[0:0]
|
|
45/92: $0\decode_to_execute_IS_CSR[0:0]
|
|
46/92: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
|
|
47/92: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
|
|
48/92: $0\execute_to_memory_INSTRUCTION[31:0]
|
|
49/92: $0\decode_to_execute_INSTRUCTION[31:0]
|
|
50/92: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
|
|
51/92: $0\decode_to_execute_DO_EBREAK[0:0]
|
|
52/92: $0\decode_to_execute_RS2[31:0]
|
|
53/92: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
|
|
54/92: $0\execute_to_memory_SHIFT_CTRL[1:0]
|
|
55/92: $0\decode_to_execute_SHIFT_CTRL[1:0]
|
|
56/92: $0\memory_to_writeBack_PC[31:0]
|
|
57/92: $0\execute_to_memory_PC[31:0]
|
|
58/92: $0\decode_to_execute_PC[31:0]
|
|
59/92: $0\execute_to_memory_BRANCH_DO[0:0]
|
|
60/92: $0\decode_to_execute_ALU_CTRL[1:0]
|
|
61/92: $0\decode_to_execute_IS_RS2_SIGNED[0:0]
|
|
62/92: $0\memory_to_writeBack_MEMORY_STORE[0:0]
|
|
63/92: $0\execute_to_memory_MEMORY_STORE[0:0]
|
|
64/92: $0\decode_to_execute_MEMORY_STORE[0:0]
|
|
65/92: $0\memory_to_writeBack_ENV_CTRL[0:0]
|
|
66/92: $0\execute_to_memory_ENV_CTRL[0:0]
|
|
67/92: $0\decode_to_execute_ENV_CTRL[0:0]
|
|
68/92: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
|
|
69/92: $0\execute_to_memory_MUL_LL[31:0]
|
|
70/92: $0\decode_to_execute_RS1[31:0]
|
|
71/92: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
|
|
72/92: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
|
|
73/92: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
|
|
74/92: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
|
|
75/92: $0\memory_MulDivIterativePlugin_div_result[31:0]
|
|
76/92: $0\memory_MulDivIterativePlugin_div_done[0:0]
|
|
77/92: $0\memory_MulDivIterativePlugin_div_needRevert[0:0]
|
|
78/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [31:0]
|
|
79/92: $0\memory_MulDivIterativePlugin_rs2[31:0]
|
|
80/92: $0\CsrPlugin_mip_MSIP[0:0]
|
|
81/92: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
82/92: $0\CsrPlugin_interrupt_code[3:0]
|
|
83/92: $0\CsrPlugin_minstret[63:0]
|
|
84/92: $0\CsrPlugin_mcause_exceptionCode[3:0]
|
|
85/92: $0\CsrPlugin_mcause_interrupt[0:0]
|
|
86/92: $0\CsrPlugin_mepc[31:0]
|
|
87/92: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0]
|
|
88/92: $0\_zz_63_[0:0]
|
|
89/92: $0\_zz_62_[31:0]
|
|
90/92: $0\_zz_61_[0:0]
|
|
91/92: $0\_zz_60_[31:0]
|
|
92/92: $0\_zz_58_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
1/38: $0\memory_MulDivIterativePlugin_div_counter_value[5:0]
|
|
2/38: $0\_zz_100_[0:0]
|
|
3/38: $0\_zz_88_[0:0]
|
|
4/38: $0\execute_CsrPlugin_wfiWake[0:0]
|
|
5/38: $0\CsrPlugin_hadException[0:0]
|
|
6/38: $0\CsrPlugin_interrupt_valid[0:0]
|
|
7/38: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0]
|
|
8/38: $0\IBusSimplePlugin_pending_value[2:0]
|
|
9/38: $0\IBusSimplePlugin_fetchPc_booted[0:0]
|
|
10/38: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
|
|
11/38: $0\memory_to_writeBack_INSTRUCTION[31:0]
|
|
12/38: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
|
|
13/38: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
|
|
14/38: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
|
|
15/38: $0\CsrPlugin_mie_MSIE[0:0]
|
|
16/38: $0\CsrPlugin_mie_MTIE[0:0]
|
|
17/38: $0\CsrPlugin_mie_MEIE[0:0]
|
|
18/38: $0\CsrPlugin_mstatus_MPP[1:0]
|
|
19/38: $0\CsrPlugin_mstatus_MPIE[0:0]
|
|
20/38: $0\CsrPlugin_mstatus_MIE[0:0]
|
|
21/38: $0\CsrPlugin_mtvec_base[29:0]
|
|
22/38: $0\CsrPlugin_mtvec_mode[1:0]
|
|
23/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0]
|
|
24/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0]
|
|
25/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0]
|
|
26/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0]
|
|
27/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0]
|
|
28/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0]
|
|
29/38: $0\IBusSimplePlugin_fetchPc_inc[0:0]
|
|
30/38: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0]
|
|
31/38: $0\IBusSimplePlugin_fetchPc_pcReg[31:0]
|
|
32/38: $0\writeBack_arbitration_isValid[0:0]
|
|
33/38: $0\memory_arbitration_isValid[0:0]
|
|
34/38: $0\execute_arbitration_isValid[0:0]
|
|
35/38: $0\_zz_125_[2:0]
|
|
36/38: $0\_zz_59_[0:0]
|
|
37/38: $0\_zz_57_[0:0]
|
|
38/38: $0\_zz_55_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9179$1417'.
|
|
1/1: $1\_zz_134_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9172$1416'.
|
|
1/1: $1\_zz_133_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9165$1415'.
|
|
1/1: $1\_zz_132_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9158$1414'.
|
|
1/1: $1\_zz_131_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9150$1413'.
|
|
1/2: $1\_zz_130_[3:0]
|
|
2/2: $2\_zz_130_[31:31]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9142$1412'.
|
|
1/2: $1\_zz_129_[31:0] [31:2]
|
|
2/2: $1\_zz_129_[31:0] [1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9133$1411'.
|
|
1/3: $1\_zz_128_[3:3]
|
|
2/3: $2\_zz_128_[7:7]
|
|
3/3: $3\_zz_128_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9124$1410'.
|
|
1/3: $1\_zz_127_[3:3]
|
|
2/3: $2\_zz_127_[7:7]
|
|
3/3: $3\_zz_127_[11:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9115$1409'.
|
|
1/3: $1\_zz_126_[3:3]
|
|
2/3: $2\_zz_126_[7:7]
|
|
3/3: $3\_zz_126_[12:11]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9096$1408'.
|
|
1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9028$1354'.
|
|
1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9017$1352'.
|
|
1/5: $1\debug_bus_rsp_data[4:0] [4]
|
|
2/5: $1\debug_bus_rsp_data[4:0] [2]
|
|
3/5: $1\debug_bus_rsp_data[4:0] [1]
|
|
4/5: $1\debug_bus_rsp_data[4:0] [0]
|
|
5/5: $1\debug_bus_rsp_data[4:0] [3]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8994$1351'.
|
|
1/3: $3\debug_bus_cmd_ready[0:0]
|
|
2/3: $2\debug_bus_cmd_ready[0:0]
|
|
3/3: $1\debug_bus_cmd_ready[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8989$1349'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8970$1339'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_valueNext[5:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8961$1336'.
|
|
1/1: $1\memory_MulDivIterativePlugin_div_counter_willClear[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8952$1335'.
|
|
1/2: $2\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
2/2: $1\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8935$1330'.
|
|
1/1: $1\writeBack_Mul16Plugin_bSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8921$1329'.
|
|
1/1: $1\writeBack_Mul16Plugin_aSigned[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8892$1324'.
|
|
1/1: $1\_zz_118_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8870$1323'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8846$1322'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8831$1321'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8812$1318'.
|
|
1/1: $1\_zz_111_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8800$1311'.
|
|
1/3: $3\_zz_110_[0:0]
|
|
2/3: $2\_zz_110_[0:0]
|
|
3/3: $1\_zz_110_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8764$1302'.
|
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1/10: $10\_zz_99_[0:0]
|
|
2/10: $9\_zz_99_[0:0]
|
|
3/10: $8\_zz_99_[0:0]
|
|
4/10: $7\_zz_99_[0:0]
|
|
5/10: $6\_zz_99_[0:0]
|
|
6/10: $5\_zz_99_[0:0]
|
|
7/10: $4\_zz_99_[0:0]
|
|
8/10: $3\_zz_99_[0:0]
|
|
9/10: $2\_zz_99_[0:0]
|
|
10/10: $1\_zz_99_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8736$1300'.
|
|
1/10: $10\_zz_98_[0:0]
|
|
2/10: $9\_zz_98_[0:0]
|
|
3/10: $8\_zz_98_[0:0]
|
|
4/10: $7\_zz_98_[0:0]
|
|
5/10: $6\_zz_98_[0:0]
|
|
6/10: $5\_zz_98_[0:0]
|
|
7/10: $4\_zz_98_[0:0]
|
|
8/10: $3\_zz_98_[0:0]
|
|
9/10: $2\_zz_98_[0:0]
|
|
10/10: $1\_zz_98_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8701$1299'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8665$1296'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8656$1292'.
|
|
1/1: $1\execute_SrcPlugin_addSub[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8639$1291'.
|
|
1/1: $1\_zz_95_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8616$1290'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8592$1289'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8574$1288'.
|
|
1/1: $1\_zz_90_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8560$1287'.
|
|
1/1: $1\_zz_89_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8546$1283'.
|
|
1/1: $1\execute_IntAluPlugin_bitwise[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8537$1281'.
|
|
1/1: $1\lastStageRegFileWrite_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8501$1260'.
|
|
1/1: $1\execute_CsrPlugin_writeData[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8487$1244'.
|
|
1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
|
|
2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8440$1239'.
|
|
1/16: $16\execute_CsrPlugin_illegalAccess[0:0]
|
|
2/16: $15\execute_CsrPlugin_illegalAccess[0:0]
|
|
3/16: $14\execute_CsrPlugin_illegalAccess[0:0]
|
|
4/16: $13\execute_CsrPlugin_illegalAccess[0:0]
|
|
5/16: $12\execute_CsrPlugin_illegalAccess[0:0]
|
|
6/16: $11\execute_CsrPlugin_illegalAccess[0:0]
|
|
7/16: $10\execute_CsrPlugin_illegalAccess[0:0]
|
|
8/16: $9\execute_CsrPlugin_illegalAccess[0:0]
|
|
9/16: $8\execute_CsrPlugin_illegalAccess[0:0]
|
|
10/16: $7\execute_CsrPlugin_illegalAccess[0:0]
|
|
11/16: $6\execute_CsrPlugin_illegalAccess[0:0]
|
|
12/16: $5\execute_CsrPlugin_illegalAccess[0:0]
|
|
13/16: $4\execute_CsrPlugin_illegalAccess[0:0]
|
|
14/16: $3\execute_CsrPlugin_illegalAccess[0:0]
|
|
15/16: $2\execute_CsrPlugin_illegalAccess[0:0]
|
|
16/16: $1\execute_CsrPlugin_illegalAccess[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8427$1237'.
|
|
1/1: $1\CsrPlugin_xtvec_base[29:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8416$1236'.
|
|
1/1: $1\CsrPlugin_xtvec_mode[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8406$1233'.
|
|
1/1: $1\CsrPlugin_pipelineLiberator_done[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8391$1227'.
|
|
1/1: $1\CsrPlugin_privilege[1:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8377$1226'.
|
|
1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8357$1225'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8328$1222'.
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8310$1219'.
|
|
1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
|
|
2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8294$1217'.
|
|
1/1: $1\_zz_67_[3:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8279$1216'.
|
|
1/1: $1\_zz_66_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8269$1206'.
|
|
1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8245$1197'.
|
|
1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8210$1185'.
|
|
1/1: $1\decode_arbitration_isValid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8189$1179'.
|
|
1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8163$1161'.
|
|
1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8145$1155'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8136$1153'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8129$1152'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8121$1150'.
|
|
1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8110$1146'.
|
|
1/1: $1\CsrPlugin_allowException[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8103$1144'.
|
|
1/1: $1\CsrPlugin_allowInterrupts[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8096$1143'.
|
|
1/1: $1\CsrPlugin_forceMachineWire[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8080$1142'.
|
|
1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
|
|
2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
|
|
3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8070$1141'.
|
|
1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
|
|
2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8063$1140'.
|
|
1/1: $1\CsrPlugin_thirdPartyWake[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8052$1138'.
|
|
1/2: $2\IBusSimplePlugin_incomingInstruction[0:0]
|
|
2/2: $1\IBusSimplePlugin_incomingInstruction[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8031$1137'.
|
|
1/6: $6\IBusSimplePlugin_fetcherHalt[0:0]
|
|
2/6: $5\IBusSimplePlugin_fetcherHalt[0:0]
|
|
3/6: $4\IBusSimplePlugin_fetcherHalt[0:0]
|
|
4/6: $3\IBusSimplePlugin_fetcherHalt[0:0]
|
|
5/6: $2\IBusSimplePlugin_fetcherHalt[0:0]
|
|
6/6: $1\IBusSimplePlugin_fetcherHalt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8017$1136'.
|
|
1/2: $2\writeBack_arbitration_flushNext[0:0]
|
|
2/2: $1\writeBack_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8009$1135'.
|
|
1/1: $1\writeBack_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8000$1134'.
|
|
1/1: $1\memory_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7992$1133'.
|
|
1/1: $1\memory_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7979$1123'.
|
|
1/3: $3\memory_arbitration_haltItself[0:0]
|
|
2/3: $2\memory_arbitration_haltItself[0:0]
|
|
3/3: $1\memory_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7970$1122'.
|
|
1/2: $2\execute_arbitration_flushNext[0:0]
|
|
2/2: $1\execute_arbitration_flushNext[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7961$1121'.
|
|
1/2: $2\execute_arbitration_flushIt[0:0]
|
|
2/2: $1\execute_arbitration_flushIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7954$1120'.
|
|
1/1: $1\execute_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7947$1119'.
|
|
1/1: $1\execute_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7935$1111'.
|
|
1/3: $3\execute_arbitration_haltItself[0:0]
|
|
2/3: $2\execute_arbitration_haltItself[0:0]
|
|
3/3: $1\execute_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7926$1110'.
|
|
1/1: $1\decode_arbitration_removeIt[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7913$1100'.
|
|
1/3: $3\decode_arbitration_haltByOther[0:0]
|
|
2/3: $2\decode_arbitration_haltByOther[0:0]
|
|
3/3: $1\decode_arbitration_haltByOther[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7894$1099'.
|
|
1/1: $1\decode_arbitration_haltItself[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7883$1098'.
|
|
1/1: $1\_zz_48_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7855$1095'.
|
|
1/3: $3\_zz_47_[31:0]
|
|
2/3: $2\_zz_47_[31:0]
|
|
3/3: $1\_zz_47_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7840$1094'.
|
|
1/1: $1\_zz_43_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7833$1092'.
|
|
1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7825$1090'.
|
|
1/1: $1\_zz_35_[0:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7787$1089'.
|
|
1/3: $3\_zz_23_[31:0]
|
|
2/3: $2\_zz_23_[31:0]
|
|
3/3: $1\_zz_23_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7756$1087'.
|
|
1/11: $11\decode_RS1[31:0]
|
|
2/11: $10\decode_RS1[31:0]
|
|
3/11: $9\decode_RS1[31:0]
|
|
4/11: $8\decode_RS1[31:0]
|
|
5/11: $7\decode_RS1[31:0]
|
|
6/11: $6\decode_RS1[31:0]
|
|
7/11: $5\decode_RS1[31:0]
|
|
8/11: $4\decode_RS1[31:0]
|
|
9/11: $3\decode_RS1[31:0]
|
|
10/11: $2\decode_RS1[31:0]
|
|
11/11: $1\decode_RS1[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7726$1085'.
|
|
1/11: $11\decode_RS2[31:0]
|
|
2/11: $10\decode_RS2[31:0]
|
|
3/11: $9\decode_RS2[31:0]
|
|
4/11: $8\decode_RS2[31:0]
|
|
5/11: $7\decode_RS2[31:0]
|
|
6/11: $6\decode_RS2[31:0]
|
|
7/11: $5\decode_RS2[31:0]
|
|
8/11: $4\decode_RS2[31:0]
|
|
9/11: $3\decode_RS2[31:0]
|
|
10/11: $2\decode_RS2[31:0]
|
|
11/11: $1\decode_RS2[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
1/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056
|
|
2/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_DATA[31:0]$1055
|
|
3/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_ADDR[4:0]$1054
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7061$1051'.
|
|
1/1: $0\_zz_138_[31:0]
|
|
Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7055$1049'.
|
|
1/1: $0\_zz_137_[31:0]
|
|
Creating decoders for process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:5868$870'.
|
|
Creating decoders for process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5817$860'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5782$859'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5769$857'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
1/3: $0\popPtr_value[2:0]
|
|
2/3: $0\pushPtr_value[2:0]
|
|
3/3: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5688$836'.
|
|
1/1: $1\io_occupancy[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5668$825'.
|
|
1/2: $2\popPtr_valueNext[2:0]
|
|
2/2: $1\popPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5659$822'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5652$821'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5641$819'.
|
|
1/2: $2\pushPtr_valueNext[2:0]
|
|
2/2: $1\pushPtr_valueNext[2:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5632$816'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5625$815'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5618$814'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
1/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813
|
|
2/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_DATA[1:0]$812
|
|
3/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_ADDR[2:0]$811
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
1/2: $0\_zz_1_[0:0]
|
|
2/2: $0\_zz_2_[0:0]
|
|
Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:5525$797'.
|
|
1/2: $2\io_input_ready[0:0]
|
|
2/2: $1\io_input_ready[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5490$796'.
|
|
1/2: $0\maskLocked_1[0:0]
|
|
2/2: $0\maskLocked_0[0:0]
|
|
Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5477$794'.
|
|
1/1: $0\locked[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
1/4: $0\_zz_2_[0:0]
|
|
2/4: $0\logic_popPtr_value[3:0]
|
|
3/4: $0\logic_pushPtr_value[3:0]
|
|
4/4: $0\logic_risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5329$758'.
|
|
1/1: $1\logic_popPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5320$755'.
|
|
1/1: $1\logic_popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5313$754'.
|
|
1/1: $1\logic_popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5306$752'.
|
|
1/1: $1\logic_pushPtr_valueNext[3:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5297$749'.
|
|
1/1: $1\logic_pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5290$748'.
|
|
1/1: $1\logic_pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5283$747'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
1/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746
|
|
2/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_DATA[7:0]$745
|
|
3/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_ADDR[3:0]$744
|
|
Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5271$741'.
|
|
1/1: $0\_zz_3_[7:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5208$737'.
|
|
1/1: $0\clockDivider_counter[19:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5193$736'.
|
|
1/1: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5186$735'.
|
|
1/1: $1\io_write_thrown_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5050$733'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5089$732'.
|
|
1/1: $0\outputArea_flow_regNext_valid[0:0]
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5083$731'.
|
|
Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
1/3: $0\inputArea_data_fragment[0:0]
|
|
2/3: $0\inputArea_data_last[0:0]
|
|
3/3: $0\inputArea_target[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5028$727'.
|
|
1/1: $0\_zz_3_[32:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5015$725'.
|
|
1/1: $0\risingOccupancy[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5006$723'.
|
|
1/1: $1\io_pop_payload_inst[31:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4998$722'.
|
|
1/1: $1\io_pop_payload_error[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4989$721'.
|
|
1/1: $1\io_pop_valid[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4974$713'.
|
|
1/1: $1\popPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4967$712'.
|
|
1/1: $1\popPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4958$710'.
|
|
1/1: $1\pushPtr_willClear[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4951$709'.
|
|
1/1: $1\pushPtr_willIncrement[0:0]
|
|
Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4944$708'.
|
|
1/1: $1\_zz_1_[0:0]
|
|
Creating decoders for process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
1/7: $0\selKey[1:0]
|
|
2/7: $0\cntStage[3:0]
|
|
3/7: $0\stateKey_3[31:0]
|
|
4/7: $0\stateKey_2[31:0]
|
|
5/7: $0\stateKey_1[31:0]
|
|
6/7: $0\stateKey_0[31:0]
|
|
7/7: $0\cntRound[3:0]
|
|
Creating decoders for process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
1/2: $0\cmdready[0:0]
|
|
2/2: $0\autoUpdate[0:0]
|
|
Creating decoders for process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4814$693'.
|
|
1/3: $3\updateKey_storeKey[0:0]
|
|
2/3: $2\updateKey_storeKey[0:0]
|
|
3/3: $1\updateKey_storeKey[0:0]
|
|
Creating decoders for process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4800$687'.
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
1/18: $0\mixColumn_cntColumn[3:0]
|
|
2/18: $0\cntRound[3:0]
|
|
3/18: $0\dataState_15[7:0]
|
|
4/18: $0\dataState_14[7:0]
|
|
5/18: $0\dataState_13[7:0]
|
|
6/18: $0\dataState_12[7:0]
|
|
7/18: $0\dataState_11[7:0]
|
|
8/18: $0\dataState_10[7:0]
|
|
9/18: $0\dataState_9[7:0]
|
|
10/18: $0\dataState_8[7:0]
|
|
11/18: $0\dataState_7[7:0]
|
|
12/18: $0\dataState_6[7:0]
|
|
13/18: $0\dataState_5[7:0]
|
|
14/18: $0\dataState_4[7:0]
|
|
15/18: $0\dataState_3[7:0]
|
|
16/18: $0\dataState_2[7:0]
|
|
17/18: $0\dataState_1[7:0]
|
|
18/18: $0\dataState_0[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
1/5: $0\sm_stateReg[2:0]
|
|
2/5: $0\byteSubstitution_cntByte_value[3:0]
|
|
3/5: $0\smDone_regNext[0:0]
|
|
4/5: $0\keyMode[0:0]
|
|
5/5: $0\keyValid[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4002$612'.
|
|
1/13: $13\sm_stateNext[2:0]
|
|
2/13: $12\sm_stateNext[2:0]
|
|
3/13: $11\sm_stateNext[2:0]
|
|
4/13: $10\sm_stateNext[2:0]
|
|
5/13: $9\sm_stateNext[2:0]
|
|
6/13: $8\sm_stateNext[2:0]
|
|
7/13: $7\sm_stateNext[2:0]
|
|
8/13: $6\sm_stateNext[2:0]
|
|
9/13: $5\sm_stateNext[2:0]
|
|
10/13: $4\sm_stateNext[2:0]
|
|
11/13: $3\sm_stateNext[2:0]
|
|
12/13: $2\sm_stateNext[2:0]
|
|
13/13: $1\sm_stateNext[2:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3759$558'.
|
|
1/1: $1\byteSubstitution_cntByte_valueNext[3:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3750$554'.
|
|
1/1: $1\byteSubstitution_cntByte_willClear[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3743$553'.
|
|
1/1: $1\byteSubstitution_cntByte_willIncrement[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3724$552'.
|
|
1/1: $1\sm_mixCol_cmd_valid[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3705$551'.
|
|
1/1: $1\sm_shiftRow_cmd[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3686$550'.
|
|
1/1: $1\sm_byteSub_cmd_valid[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3665$549'.
|
|
1/2: $2\sm_keyAddition_cmd[0:0]
|
|
2/2: $1\sm_keyAddition_cmd[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3598$547'.
|
|
1/6: $6\smDone[0:0]
|
|
2/6: $5\smDone[0:0]
|
|
3/6: $4\smDone[0:0]
|
|
4/6: $3\smDone[0:0]
|
|
5/6: $2\smDone[0:0]
|
|
6/6: $1\smDone[0:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3502$545'.
|
|
1/1: $1\_zz_269_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3449$544'.
|
|
1/1: $1\_zz_268_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3396$543'.
|
|
1/1: $1\_zz_267_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3343$542'.
|
|
1/1: $1\_zz_266_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3290$541'.
|
|
1/1: $1\_zz_265_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3237$540'.
|
|
1/1: $1\_zz_264_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3184$539'.
|
|
1/1: $1\_zz_263_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3131$538'.
|
|
1/1: $1\_zz_262_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3078$537'.
|
|
1/1: $1\_zz_261_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3025$536'.
|
|
1/1: $1\_zz_260_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2972$535'.
|
|
1/1: $1\_zz_259_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2919$534'.
|
|
1/1: $1\_zz_258_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2866$533'.
|
|
1/1: $1\_zz_257_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2813$532'.
|
|
1/1: $1\_zz_256_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2760$531'.
|
|
1/1: $1\_zz_255_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2707$530'.
|
|
1/1: $1\_zz_254_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2654$529'.
|
|
1/1: $1\_zz_253_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2601$528'.
|
|
1/1: $1\_zz_252_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2548$527'.
|
|
1/1: $1\_zz_251_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2495$526'.
|
|
1/1: $1\_zz_250_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2442$525'.
|
|
1/1: $1\_zz_249_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2389$524'.
|
|
1/1: $1\_zz_248_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2336$523'.
|
|
1/1: $1\_zz_247_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2283$522'.
|
|
1/1: $1\_zz_246_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2230$521'.
|
|
1/1: $1\_zz_245_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2177$520'.
|
|
1/1: $1\_zz_244_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2124$519'.
|
|
1/1: $1\_zz_243_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2071$518'.
|
|
1/1: $1\_zz_242_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2018$517'.
|
|
1/1: $1\_zz_241_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1965$516'.
|
|
1/1: $1\_zz_240_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1912$515'.
|
|
1/1: $1\_zz_239_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1859$514'.
|
|
1/1: $1\_zz_238_[7:0]
|
|
Creating decoders for process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1806$513'.
|
|
1/1: $1\_zz_237_[7:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
1/9: $2$lookahead\stateMachine_shifter$60[7:0]$74
|
|
2/9: $2$bitselwrite$data$PQVexRiscvUlx3s.v:592$28[7:0]$73
|
|
3/9: $2$bitselwrite$mask$PQVexRiscvUlx3s.v:592$27[7:0]$72
|
|
4/9: $1$lookahead\stateMachine_shifter$60[7:0]$70
|
|
5/9: $1$bitselwrite$data$PQVexRiscvUlx3s.v:592$28[7:0]$69
|
|
6/9: $1$bitselwrite$mask$PQVexRiscvUlx3s.v:592$27[7:0]$68
|
|
7/9: $0\bitCounter_value[2:0]
|
|
8/9: $0\bitTimer_counter[2:0]
|
|
9/9: $0\stateMachine_parity[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
1/8: $0\stateMachine_validReg[0:0]
|
|
2/8: $0\sampler_tick[0:0]
|
|
3/8: $0\sampler_value[0:0]
|
|
4/8: $0\_zz_1_[0:0]
|
|
5/8: $0\break_counter[6:0]
|
|
6/8: $0\sampler_samples_2[0:0]
|
|
7/8: $0\sampler_samples_1[0:0]
|
|
8/8: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:473$41'.
|
|
1/2: $2\bitTimer_tick[0:0]
|
|
2/2: $1\bitTimer_tick[0:0]
|
|
Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:443$39'.
|
|
1/5: $5\io_error[0:0]
|
|
2/5: $4\io_error[0:0]
|
|
3/5: $3\io_error[0:0]
|
|
4/5: $2\io_error[0:0]
|
|
5/5: $1\io_error[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:318$23'.
|
|
1/2: $0\stateMachine_parity[0:0]
|
|
2/2: $0\tickCounter_value[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
1/3: $0\_zz_1_[0:0]
|
|
2/3: $0\clockDivider_counter_value[2:0]
|
|
3/3: $0\stateMachine_state[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:250$13'.
|
|
1/3: $3\io_write_ready[0:0]
|
|
2/3: $2\io_write_ready[0:0]
|
|
3/3: $1\io_write_ready[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:231$11'.
|
|
1/1: $1\stateMachine_txd[0:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:220$9'.
|
|
1/2: $2\clockDivider_counter_valueNext[2:0]
|
|
2/2: $1\clockDivider_counter_valueNext[2:0]
|
|
Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:210$6'.
|
|
1/1: $1\clockDivider_counter_willIncrement[0:0]
|
|
Creating decoders for process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:132$2'.
|
|
Creating decoders for process `\BufferCC.$proc$PQVexRiscvUlx3s.v:109$1'.
|
|
1/2: $0\buffers_1[0:0]
|
|
2/2: $0\buffers_0[0:0]
|
|
|
|
2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `\PQVexRiscvUlx3s.\_zz_22_' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12430$1888'.
|
|
No latch inferred for signal `\PQVexRiscvUlx3s.\core_externalInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12408$1883'.
|
|
No latch inferred for signal `\PipelinedMemoryBusArbiter_2_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11851$1876'.
|
|
No latch inferred for signal `\PipelinedMemoryBusArbiter_2_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11844$1875'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11698$1872'.
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No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11691$1871'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11503$1849'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11490$1845'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11477$1841'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\_zz_3_' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11465$1838'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11381$1809'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_2_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11368$1805'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11355$1801'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11342$1797'.
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No latch inferred for signal `\PipelinedMemoryBusDecoder.\_zz_4_' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11327$1794'.
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No latch inferred for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11220$1754'.
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No latch inferred for signal `\PipelinedMemoryBusRamUlx3s.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11152$1714'.
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No latch inferred for signal `\Apb3Router.\_zz_2_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
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No latch inferred for signal `\Apb3Router.\_zz_3_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
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No latch inferred for signal `\Apb3Router.\_zz_4_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
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No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11047$1707'.
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No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11039$1706'.
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No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11034$1699'.
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No latch inferred for signal `\MyMem.\io_bus_PRDATA' from process `\MyMem.$proc$PQVexRiscvUlx3s.v:10823$1682'.
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No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:10546$1642$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1679'.
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No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:10546$1643$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1679'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_6_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10674$1672'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_5_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10657$1671'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_4_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10640$1670'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_3_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10623$1669'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_2_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10606$1668'.
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No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10586$1663'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_8_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10578$1662'.
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No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10571$1661'.
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No latch inferred for signal `\Apb3UartCtrl.\_zz_1_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10551$1660'.
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No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10547$1659'.
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No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10515$1645'.
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No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10315$1637'.
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No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10301$1635'.
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No latch inferred for signal `\JtagBridge.\jtag_writeArea_source_valid' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10109$1610'.
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No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10081$1607'.
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No latch inferred for signal `\JtagBridge.\_zz_1_' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10027$1590'.
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No latch inferred for signal `\VexRiscv.\_zz_134_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9179$1417'.
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No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9172$1416'.
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No latch inferred for signal `\VexRiscv.\_zz_132_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9165$1415'.
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No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9158$1414'.
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No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9150$1413'.
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No latch inferred for signal `\VexRiscv.\_zz_129_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9142$1412'.
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No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9133$1411'.
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No latch inferred for signal `\VexRiscv.\_zz_127_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9124$1410'.
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No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9115$1409'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9096$1408'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9028$1354'.
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No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9017$1352'.
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No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8994$1351'.
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No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8989$1349'.
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No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_valueNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8970$1339'.
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No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willClear' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8961$1336'.
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No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8952$1335'.
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No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_bSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8935$1330'.
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No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_aSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8921$1329'.
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No latch inferred for signal `\VexRiscv.\_zz_118_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8892$1324'.
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No latch inferred for signal `\VexRiscv.\_zz_117_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8870$1323'.
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No latch inferred for signal `\VexRiscv.\_zz_115_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8846$1322'.
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No latch inferred for signal `\VexRiscv.\_zz_113_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8831$1321'.
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No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8812$1318'.
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No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8800$1311'.
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No latch inferred for signal `\VexRiscv.\_zz_99_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8764$1302'.
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No latch inferred for signal `\VexRiscv.\_zz_98_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8736$1300'.
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No latch inferred for signal `\VexRiscv.\_zz_97_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8701$1299'.
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No latch inferred for signal `\VexRiscv.\_zz_96_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8665$1296'.
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No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8656$1292'.
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No latch inferred for signal `\VexRiscv.\_zz_95_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8639$1291'.
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No latch inferred for signal `\VexRiscv.\_zz_94_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8616$1290'.
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No latch inferred for signal `\VexRiscv.\_zz_92_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8592$1289'.
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No latch inferred for signal `\VexRiscv.\_zz_90_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8574$1288'.
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No latch inferred for signal `\VexRiscv.\_zz_89_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8560$1287'.
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No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8546$1283'.
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No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8537$1281'.
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No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8501$1260'.
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No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8487$1244'.
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No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8440$1239'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8427$1237'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8416$1236'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8406$1233'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8391$1227'.
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No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8377$1226'.
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No latch inferred for signal `\VexRiscv.\_zz_71_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8357$1225'.
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No latch inferred for signal `\VexRiscv.\_zz_69_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8328$1222'.
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No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8310$1219'.
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No latch inferred for signal `\VexRiscv.\_zz_67_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8294$1217'.
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No latch inferred for signal `\VexRiscv.\_zz_66_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8279$1216'.
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No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8269$1206'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8245$1197'.
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No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8210$1185'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8189$1179'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8163$1161'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8145$1155'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8136$1153'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8129$1152'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8121$1150'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8110$1146'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8103$1144'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8096$1143'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8080$1142'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8070$1141'.
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No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8063$1140'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8052$1138'.
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No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8031$1137'.
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No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8017$1136'.
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No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8009$1135'.
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No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8000$1134'.
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No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7992$1133'.
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No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7979$1123'.
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No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7970$1122'.
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|
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7961$1121'.
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|
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7954$1120'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7947$1119'.
|
|
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7935$1111'.
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|
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7926$1110'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7913$1100'.
|
|
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7894$1099'.
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No latch inferred for signal `\VexRiscv.\_zz_48_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7883$1098'.
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No latch inferred for signal `\VexRiscv.\_zz_47_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7855$1095'.
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|
No latch inferred for signal `\VexRiscv.\_zz_43_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7840$1094'.
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|
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7833$1092'.
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|
No latch inferred for signal `\VexRiscv.\_zz_35_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7825$1090'.
|
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No latch inferred for signal `\VexRiscv.\_zz_23_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7787$1089'.
|
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No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7756$1087'.
|
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No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7726$1085'.
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|
No latch inferred for signal `\StreamFork_1_.\io_input_ready' from process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5817$860'.
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No latch inferred for signal `\StreamFifoLowLatency_1_.\io_occupancy' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5688$836'.
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|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5668$825'.
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|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5659$822'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5652$821'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5641$819'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5632$816'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5625$815'.
|
|
No latch inferred for signal `\StreamFifoLowLatency_1_.\_zz_1_' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5618$814'.
|
|
No latch inferred for signal `\StreamFork.\io_input_ready' from process `\StreamFork.$proc$PQVexRiscvUlx3s.v:5525$797'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5329$758'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5320$755'.
|
|
No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5313$754'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5306$752'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5297$749'.
|
|
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5290$748'.
|
|
No latch inferred for signal `\StreamFifo.\_zz_1_' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5283$747'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5193$736'.
|
|
No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5186$735'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5006$723'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4998$722'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4989$721'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4974$713'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4967$712'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4958$710'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4951$709'.
|
|
No latch inferred for signal `\StreamFifoLowLatency.\_zz_1_' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4944$708'.
|
|
No latch inferred for signal `\AESKeyScheduleCore_Std.\updateKey_storeKey' from process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4814$693'.
|
|
No latch inferred for signal `\AESKeyScheduleCore_Std.\_zz_1_' from process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4800$687'.
|
|
No latch inferred for signal `\AESEngine_Std.\sm_stateNext' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4002$612'.
|
|
No latch inferred for signal `\AESEngine_Std.\byteSubstitution_cntByte_valueNext' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3759$558'.
|
|
No latch inferred for signal `\AESEngine_Std.\byteSubstitution_cntByte_willClear' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3750$554'.
|
|
No latch inferred for signal `\AESEngine_Std.\byteSubstitution_cntByte_willIncrement' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3743$553'.
|
|
No latch inferred for signal `\AESEngine_Std.\sm_mixCol_cmd_valid' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3724$552'.
|
|
No latch inferred for signal `\AESEngine_Std.\sm_shiftRow_cmd' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3705$551'.
|
|
No latch inferred for signal `\AESEngine_Std.\sm_byteSub_cmd_valid' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3686$550'.
|
|
No latch inferred for signal `\AESEngine_Std.\sm_keyAddition_cmd' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3665$549'.
|
|
No latch inferred for signal `\AESEngine_Std.\smDone' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3598$547'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_269_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3502$545'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_268_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3449$544'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_267_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3396$543'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_266_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3343$542'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_265_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3290$541'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_264_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3237$540'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_263_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3184$539'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_262_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3131$538'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_261_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3078$537'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_260_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3025$536'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_259_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2972$535'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_258_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2919$534'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_257_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2866$533'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_256_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2813$532'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_255_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2760$531'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_254_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2707$530'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_253_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2654$529'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_252_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2601$528'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_251_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2548$527'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_250_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2495$526'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_249_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2442$525'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_248_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2389$524'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_247_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2336$523'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_246_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2283$522'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_245_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2230$521'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_244_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2177$520'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_243_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2124$519'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_242_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2071$518'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_241_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2018$517'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_240_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1965$516'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_239_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1912$515'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_238_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1859$514'.
|
|
No latch inferred for signal `\AESEngine_Std.\_zz_237_' from process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1806$513'.
|
|
No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:473$41'.
|
|
No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:443$39'.
|
|
No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:250$13'.
|
|
No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:231$11'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:220$9'.
|
|
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:210$6'.
|
|
|
|
2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$2136'.
|
|
created $dff cell `$procdff$6037' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2133'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
created $dff cell `$procdff$6038' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
created $dff cell `$procdff$6039' with positive edge clock.
|
|
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$2111_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
created $dff cell `$procdff$6040' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2078'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
created $dff cell `$procdff$6041' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
created $dff cell `$procdff$6042' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$2054_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
created $dff cell `$procdff$6043' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$2055'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_35_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12539$1908'.
|
|
created $adff cell `$procdff$6044' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\core_cpu_debug_resetOut_regNext' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12535$1907'.
|
|
created $dff cell `$procdff$6045' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_6_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6046' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_7_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6047' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_8_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6048' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_9_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6049' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_12_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6050' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_13_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6051' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_14_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6052' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_15_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6053' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_25_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6054' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_26_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6055' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_27_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6056' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_28_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6057' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_31_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6058' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_32_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6059' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_33_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6060' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_34_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
created $dff cell `$procdff$6061' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_5_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
created $adff cell `$procdff$6062' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_11_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
created $adff cell `$procdff$6063' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_24_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
created $adff cell `$procdff$6064' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\_zz_30_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
created $adff cell `$procdff$6065' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_systemClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12472$1894'.
|
|
created $dff cell `$procdff$6066' with positive edge clock.
|
|
Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_mainClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12472$1894'.
|
|
created $dff cell `$procdff$6067' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11523$1869'.
|
|
created $dff cell `$procdff$6068' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11523$1869'.
|
|
created $dff cell `$procdff$6069' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11515$1867'.
|
|
created $adff cell `$procdff$6070' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
created $dff cell `$procdff$6071' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
created $dff cell `$procdff$6072' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_2' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
created $dff cell `$procdff$6073' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11393$1830'.
|
|
created $adff cell `$procdff$6074' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11252$1782'.
|
|
created $adff cell `$procdff$6075' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6076' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6077' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6078' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6079' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6080' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6081' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6082' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6083' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6084' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_ADDR' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6085' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_DATA' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6086' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
created $dff cell `$procdff$6087' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
created $dff cell `$procdff$6088' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
created $dff cell `$procdff$6089' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
created $dff cell `$procdff$6090' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s_1_.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
created $dff cell `$procdff$6091' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11184$1742'.
|
|
created $adff cell `$procdff$6092' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6093' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6094' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6095' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6096' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6097' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6098' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6099' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6100' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6101' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6102' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6103' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
created $dff cell `$procdff$6104' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
created $dff cell `$procdff$6105' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
created $dff cell `$procdff$6106' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
created $dff cell `$procdff$6107' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
created $dff cell `$procdff$6108' with positive edge clock.
|
|
Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11120$1709'.
|
|
created $dff cell `$procdff$6109' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_2_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
created $dff cell `$procdff$6110' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_3_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
created $dff cell `$procdff$6111' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_5_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
created $dff cell `$procdff$6112' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_1_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
created $dff cell `$procdff$6113' with positive edge clock.
|
|
Creating register for signal `\MyMem.\_zz_4_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
created $adff cell `$procdff$6114' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MyMem.\_zz_6_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
created $adff cell `$procdff$6115' with positive edge clock and positive level reset.
|
|
Creating register for signal `\MyMem.\_zz_8_' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
created $adff cell `$procdff$6116' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\uartCtrl_1__io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10754$1678'.
|
|
created $dff cell `$procdff$6117' with positive edge clock.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6118' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6119' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6120' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6121' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6122' with positive edge clock and positive level reset.
|
|
Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
created $adff cell `$procdff$6123' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10341$1641'.
|
|
created $dff cell `$procdff$6124' with positive edge clock.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
created $adff cell `$procdff$6125' with positive edge clock and positive level reset.
|
|
Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
created $adff cell `$procdff$6126' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10246$1631'.
|
|
created $dff cell `$procdff$6127' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10246$1631'.
|
|
created $dff cell `$procdff$6128' with positive edge clock.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
created $adff cell `$procdff$6129' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
created $adff cell `$procdff$6130' with positive edge clock and positive level reset.
|
|
Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
created $adff cell `$procdff$6131' with positive edge clock and positive level reset.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10170$1621'.
|
|
created $dff cell `$procdff$6132' with negative edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6133' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6134' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6135' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6136' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6137' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\jtag_readArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
created $dff cell `$procdff$6138' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
created $dff cell `$procdff$6139' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
created $dff cell `$procdff$6140' with positive edge clock.
|
|
Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
created $dff cell `$procdff$6141' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6142' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6143' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6144' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6145' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6146' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6147' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6148' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
created $adff cell `$procdff$6149' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_124_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6150' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6151' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6152' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6153' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6154' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6155' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6156' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6157' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
created $dff cell `$procdff$6158' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_58_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6159' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_60_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6160' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_61_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6161' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_62_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6162' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_63_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6163' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6164' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_102_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6165' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6166' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6167' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6168' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6169' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6170' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6171' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6172' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6173' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6174' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6175' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6176' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6177' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6178' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_accumulator' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6179' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_needRevert' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6180' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_done' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6181' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_result' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6182' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6183' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6184' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6185' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6186' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6187' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6188' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6189' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6190' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6191' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6192' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6193' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6194' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6195' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6196' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6197' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6198' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6199' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6200' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6201' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6202' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6203' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6204' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6205' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6206' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6207' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6208' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6209' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6210' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6211' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6212' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6213' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6214' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6215' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6216' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6217' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6218' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6219' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6220' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6221' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6222' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6223' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6224' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6225' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6226' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6227' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6228' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6229' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6230' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6231' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6232' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6233' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6234' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6235' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6236' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6237' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6238' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6239' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6240' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6241' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6242' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6243' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6244' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6245' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6246' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6247' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6248' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6249' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2816' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6250' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2944' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6251' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2818' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6252' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2946' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
created $dff cell `$procdff$6253' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_55_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6254' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_57_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6255' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_59_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6256' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_88_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6257' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_100_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6258' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\_zz_125_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6259' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6260' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6261' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6262' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6263' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6264' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6265' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6266' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6267' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6268' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6269' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6270' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6271' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6272' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6273' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6274' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6275' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6276' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6277' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6278' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6279' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6280' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6281' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6282' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6283' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6284' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6285' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6286' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6287' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6288' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6289' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6290' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
created $adff cell `$procdff$6291' with positive edge clock and positive level reset.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_ADDR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
created $dff cell `$procdff$6292' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
created $dff cell `$procdff$6293' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
created $dff cell `$procdff$6294' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_138_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7061$1051'.
|
|
created $dff cell `$procdff$6295' with positive edge clock.
|
|
Creating register for signal `\VexRiscv.\_zz_137_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7055$1049'.
|
|
created $dff cell `$procdff$6296' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_0' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:5868$870'.
|
|
created $dff cell `$procdff$6297' with positive edge clock.
|
|
Creating register for signal `\BufferCC_2_.\buffers_1' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:5868$870'.
|
|
created $dff cell `$procdff$6298' with positive edge clock.
|
|
Creating register for signal `\StreamFork_1_.\_zz_2_' using process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
created $adff cell `$procdff$6299' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork_1_.\_zz_1_' using process `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
created $adff cell `$procdff$6300' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter_1_.\maskLocked_0' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5782$859'.
|
|
created $dff cell `$procdff$6301' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter_1_.\maskLocked_1' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5782$859'.
|
|
created $dff cell `$procdff$6302' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter_1_.\locked' using process `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5769$857'.
|
|
created $adff cell `$procdff$6303' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\risingOccupancy' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
created $adff cell `$procdff$6304' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\pushPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
created $adff cell `$procdff$6305' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.\popPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
created $adff cell `$procdff$6306' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_ADDR' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
created $dff cell `$procdff$6307' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_DATA' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
created $dff cell `$procdff$6308' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
created $dff cell `$procdff$6309' with positive edge clock.
|
|
Creating register for signal `\StreamFork.\_zz_2_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
created $adff cell `$procdff$6310' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFork.\_zz_1_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
created $adff cell `$procdff$6311' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_0' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5490$796'.
|
|
created $dff cell `$procdff$6312' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\maskLocked_1' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5490$796'.
|
|
created $dff cell `$procdff$6313' with positive edge clock.
|
|
Creating register for signal `\StreamArbiter.\locked' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5477$794'.
|
|
created $adff cell `$procdff$6314' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\_zz_2_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
created $adff cell `$procdff$6315' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
created $adff cell `$procdff$6316' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
created $adff cell `$procdff$6317' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
created $adff cell `$procdff$6318' with positive edge clock and positive level reset.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_ADDR' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
created $dff cell `$procdff$6319' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_DATA' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
created $dff cell `$procdff$6320' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
created $dff cell `$procdff$6321' with positive edge clock.
|
|
Creating register for signal `\StreamFifo.\_zz_3_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5271$741'.
|
|
created $dff cell `$procdff$6322' with positive edge clock.
|
|
Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5208$737'.
|
|
created $adff cell `$procdff$6323' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_valid' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5089$732'.
|
|
created $adff cell `$procdff$6324' with positive edge clock and positive level reset.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5083$731'.
|
|
created $dff cell `$procdff$6325' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5083$731'.
|
|
created $dff cell `$procdff$6326' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5083$731'.
|
|
created $dff cell `$procdff$6327' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
created $dff cell `$procdff$6328' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
created $dff cell `$procdff$6329' with positive edge clock.
|
|
Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
created $dff cell `$procdff$6330' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\_zz_3_' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5028$727'.
|
|
created $dff cell `$procdff$6331' with positive edge clock.
|
|
Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5015$725'.
|
|
created $adff cell `$procdff$6332' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\cntRound' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6333' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\stateKey_0' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6334' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\stateKey_1' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6335' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\stateKey_2' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6336' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\stateKey_3' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6337' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\cntStage' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6338' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\selKey' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
created $dff cell `$procdff$6339' with positive edge clock.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\autoUpdate' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
created $adff cell `$procdff$6340' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESKeyScheduleCore_Std.\cmdready' using process `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
created $adff cell `$procdff$6341' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESEngine_Std.\dataState_0' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6342' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_1' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6343' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_2' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6344' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_3' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6345' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_4' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6346' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_5' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6347' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_6' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6348' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_7' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6349' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_8' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6350' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_9' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6351' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_10' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6352' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_11' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6353' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_12' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6354' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_13' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6355' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_14' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6356' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\dataState_15' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6357' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\cntRound' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6358' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\mixColumn_cntColumn' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
created $dff cell `$procdff$6359' with positive edge clock.
|
|
Creating register for signal `\AESEngine_Std.\keyValid' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
created $adff cell `$procdff$6360' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESEngine_Std.\keyMode' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
created $adff cell `$procdff$6361' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESEngine_Std.\smDone_regNext' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
created $adff cell `$procdff$6362' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESEngine_Std.\byteSubstitution_cntByte_value' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
created $adff cell `$procdff$6363' with positive edge clock and positive level reset.
|
|
Creating register for signal `\AESEngine_Std.\sm_stateReg' using process `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
created $adff cell `$procdff$6364' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6365' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6366' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6367' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6368' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$mask$PQVexRiscvUlx3s.v:592$27' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6369' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$bitselwrite$data$PQVexRiscvUlx3s.v:592$28' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6370' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$60' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
created $dff cell `$procdff$6371' with positive edge clock.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6372' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\_zz_1_' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6373' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6374' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6375' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6376' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6377' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6378' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
created $adff cell `$procdff$6379' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:318$23'.
|
|
created $dff cell `$procdff$6380' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:318$23'.
|
|
created $dff cell `$procdff$6381' with positive edge clock.
|
|
Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
created $adff cell `$procdff$6382' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
created $adff cell `$procdff$6383' with positive edge clock and positive level reset.
|
|
Creating register for signal `\UartCtrlTx.\_zz_1_' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
created $adff cell `$procdff$6384' with positive edge clock and positive level reset.
|
|
Creating register for signal `\BufferCC_1_.\buffers_0' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:132$2'.
|
|
created $dff cell `$procdff$6385' with positive edge clock.
|
|
Creating register for signal `\BufferCC_1_.\buffers_1' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:132$2'.
|
|
created $dff cell `$procdff$6386' with positive edge clock.
|
|
Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:109$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$6387' with positive edge clock and positive level non-const reset.
|
|
Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:109$1'.
|
|
Warning: Async reset value `\io_initial' is not constant!
|
|
created $dffsr cell `$procdff$6394' with positive edge clock and positive level non-const reset.
|
|
|
|
2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2140'.
|
|
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$2136'.
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$2136'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2133'.
|
|
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$2112'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$2078'.
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$2056'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$2055'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12539$1908'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12535$1907'.
|
|
Found and cleaned up 4 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12508$1898'.
|
|
Found and cleaned up 6 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12480$1895'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12472$1894'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12472$1894'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12430$1888'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12430$1888'.
|
|
Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12408$1883'.
|
|
Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:12408$1883'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11851$1876'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11851$1876'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11844$1875'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_2_.$proc$PQVexRiscvUlx3s.v:11844$1875'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11698$1872'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11698$1872'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11691$1871'.
|
|
Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:11691$1871'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11523$1869'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11523$1869'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11515$1867'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11503$1849'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11503$1849'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11490$1845'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11490$1845'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11477$1841'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11477$1841'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11465$1838'.
|
|
Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:11465$1838'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11401$1832'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11393$1830'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11381$1809'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11381$1809'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11368$1805'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11368$1805'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11355$1801'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11355$1801'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11342$1797'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11342$1797'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11327$1794'.
|
|
Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:11327$1794'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11252$1782'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11232$1760'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11223$1755'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s_1_.$proc$PQVexRiscvUlx3s.v:11220$1754'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11184$1742'.
|
|
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11164$1720'.
|
|
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11155$1715'.
|
|
Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:11152$1714'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:11120$1709'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
|
|
Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:11091$1708'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11047$1707'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11047$1707'.
|
|
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11039$1706'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11039$1706'.
|
|
Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:11034$1699'.
|
|
Found and cleaned up 11 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:10937$1696'.
|
|
Found and cleaned up 7 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:10875$1695'.
|
|
Found and cleaned up 1 empty switch in `\MyMem.$proc$PQVexRiscvUlx3s.v:10823$1682'.
|
|
Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:10823$1682'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1679'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10754$1678'.
|
|
Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10694$1673'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10674$1672'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10674$1672'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10657$1671'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10657$1671'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10640$1670'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10640$1670'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10623$1669'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10623$1669'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10606$1668'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10606$1668'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10586$1663'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10586$1663'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10578$1662'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10578$1662'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10571$1661'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10571$1661'.
|
|
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10551$1660'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10551$1660'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10547$1659'.
|
|
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10515$1645'.
|
|
Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:10515$1645'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10341$1641'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10325$1640'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10315$1637'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10315$1637'.
|
|
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10301$1635'.
|
|
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:10301$1635'.
|
|
Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10246$1631'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:10246$1631'.
|
|
Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:10220$1627'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:9915$1622'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10170$1621'.
|
|
Found and cleaned up 7 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10135$1615'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10124$1613'.
|
|
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10109$1610'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10109$1610'.
|
|
Found and cleaned up 5 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10081$1607'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10081$1607'.
|
|
Found and cleaned up 1 empty switch in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:10027$1590'.
|
|
Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:10027$1590'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:6515$1587'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:6514$1586'.
|
|
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9803$1582'.
|
|
Found and cleaned up 8 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9761$1579'.
|
|
Found and cleaned up 90 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9450$1476'.
|
|
Found and cleaned up 61 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9188$1426'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9179$1417'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9179$1417'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9172$1416'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9172$1416'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9165$1415'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9165$1415'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9158$1414'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9158$1414'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9150$1413'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9150$1413'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9142$1412'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9142$1412'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9133$1411'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9133$1411'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9124$1410'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9124$1410'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9115$1409'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9115$1409'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9096$1408'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9096$1408'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9028$1354'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9028$1354'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:9017$1352'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:9017$1352'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8994$1351'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8994$1351'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8989$1349'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8970$1339'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8970$1339'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8961$1336'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8961$1336'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8952$1335'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8952$1335'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8935$1330'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8935$1330'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8921$1329'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8921$1329'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8892$1324'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8892$1324'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8870$1323'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8846$1322'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8831$1321'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8812$1318'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8812$1318'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8800$1311'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8800$1311'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8764$1302'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8764$1302'.
|
|
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8736$1300'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8736$1300'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8701$1299'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8665$1296'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8656$1292'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8656$1292'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8639$1291'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8639$1291'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8616$1290'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8592$1289'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8574$1288'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8574$1288'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8560$1287'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8560$1287'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8546$1283'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8546$1283'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8537$1281'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8537$1281'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8501$1260'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8501$1260'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8487$1244'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8487$1244'.
|
|
Found and cleaned up 16 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8440$1239'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8440$1239'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8427$1237'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8427$1237'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8416$1236'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8416$1236'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8406$1233'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8406$1233'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8391$1227'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8391$1227'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8377$1226'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8377$1226'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8357$1225'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8328$1222'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8310$1219'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8310$1219'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8294$1217'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8294$1217'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8279$1216'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8279$1216'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8269$1206'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8269$1206'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8245$1197'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8245$1197'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8210$1185'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8210$1185'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8189$1179'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8189$1179'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8163$1161'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8163$1161'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8145$1155'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8145$1155'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8136$1153'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8136$1153'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8129$1152'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8129$1152'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8121$1150'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8121$1150'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8110$1146'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8110$1146'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8103$1144'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8103$1144'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8096$1143'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8096$1143'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8080$1142'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8080$1142'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8070$1141'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8070$1141'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8063$1140'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8063$1140'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8052$1138'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8052$1138'.
|
|
Found and cleaned up 6 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8031$1137'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8031$1137'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8017$1136'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8017$1136'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8009$1135'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8009$1135'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:8000$1134'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:8000$1134'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7992$1133'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7992$1133'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7979$1123'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7979$1123'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7970$1122'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7970$1122'.
|
|
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7961$1121'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7961$1121'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7954$1120'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7954$1120'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7947$1119'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7947$1119'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7935$1111'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7935$1111'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7926$1110'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7926$1110'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7913$1100'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7913$1100'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7894$1099'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7894$1099'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7883$1098'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7883$1098'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7855$1095'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7855$1095'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7840$1094'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7840$1094'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7833$1092'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7833$1092'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7825$1090'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7825$1090'.
|
|
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7787$1089'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7787$1089'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7756$1087'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7756$1087'.
|
|
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7726$1085'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7726$1085'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7067$1053'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7061$1051'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7061$1051'.
|
|
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:7055$1049'.
|
|
Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:7055$1049'.
|
|
Removing empty process `BufferCC_2_.$proc$PQVexRiscvUlx3s.v:5868$870'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
Removing empty process `StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5837$867'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5817$860'.
|
|
Removing empty process `StreamFork_1_.$proc$PQVexRiscvUlx3s.v:5817$860'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5782$859'.
|
|
Removing empty process `StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5782$859'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5769$857'.
|
|
Removing empty process `StreamArbiter_1_.$proc$PQVexRiscvUlx3s.v:5769$857'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5696$840'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5688$836'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5688$836'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5668$825'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5668$825'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5659$822'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5659$822'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5652$821'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5652$821'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5641$819'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5641$819'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5632$816'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5632$816'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5625$815'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5625$815'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5618$814'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5618$814'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:5612$810'.
|
|
Found and cleaned up 3 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:5545$804'.
|
|
Found and cleaned up 2 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:5525$797'.
|
|
Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:5525$797'.
|
|
Found and cleaned up 1 empty switch in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5490$796'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:5490$796'.
|
|
Found and cleaned up 2 empty switches in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:5477$794'.
|
|
Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:5477$794'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5347$776'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5329$758'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5329$758'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5320$755'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5320$755'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5313$754'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5313$754'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5306$752'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5306$752'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5297$749'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5297$749'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5290$748'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5290$748'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5283$747'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5283$747'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5277$743'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:5271$741'.
|
|
Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:5271$741'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5208$737'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:5208$737'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5193$736'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:5193$736'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:5186$735'.
|
|
Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:5186$735'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5050$733'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5089$732'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5083$731'.
|
|
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:5075$729'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5028$727'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5028$727'.
|
|
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5015$725'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5015$725'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5006$723'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:5006$723'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4998$722'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4998$722'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4989$721'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4989$721'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4974$713'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4974$713'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4967$712'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4967$712'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4958$710'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4958$710'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4951$709'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4951$709'.
|
|
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4944$708'.
|
|
Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:4944$708'.
|
|
Found and cleaned up 7 empty switches in `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4862$697'.
|
|
Found and cleaned up 8 empty switches in `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4826$694'.
|
|
Found and cleaned up 3 empty switches in `\AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4814$693'.
|
|
Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4814$693'.
|
|
Removing empty process `AESKeyScheduleCore_Std.$proc$PQVexRiscvUlx3s.v:4800$687'.
|
|
Found and cleaned up 174 empty switches in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4117$617'.
|
|
Found and cleaned up 8 empty switches in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4066$614'.
|
|
Found and cleaned up 13 empty switches in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4002$612'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:4002$612'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3759$558'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3759$558'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3750$554'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3750$554'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3743$553'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3743$553'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3724$552'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3724$552'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3705$551'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3705$551'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3686$550'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3686$550'.
|
|
Found and cleaned up 2 empty switches in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3665$549'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3665$549'.
|
|
Found and cleaned up 6 empty switches in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3598$547'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3598$547'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3502$545'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3502$545'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3449$544'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3449$544'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3396$543'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3396$543'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3343$542'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3343$542'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3290$541'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3290$541'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3237$540'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3237$540'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3184$539'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3184$539'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3131$538'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3131$538'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3078$537'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3078$537'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3025$536'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:3025$536'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2972$535'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2972$535'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2919$534'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2919$534'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2866$533'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2866$533'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2813$532'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2813$532'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2760$531'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2760$531'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2707$530'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2707$530'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2654$529'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2654$529'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2601$528'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2601$528'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2548$527'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2548$527'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2495$526'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2495$526'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2442$525'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2442$525'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2389$524'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2389$524'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2336$523'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2336$523'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2283$522'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2283$522'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2230$521'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2230$521'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2177$520'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2177$520'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2124$519'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2124$519'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2071$518'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2071$518'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2018$517'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:2018$517'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1965$516'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1965$516'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1912$515'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1912$515'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1859$514'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1859$514'.
|
|
Found and cleaned up 1 empty switch in `\AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1806$513'.
|
|
Removing empty process `AESEngine_Std.$proc$PQVexRiscvUlx3s.v:1806$513'.
|
|
Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:565$61'.
|
|
Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:486$43'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:473$41'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:473$41'.
|
|
Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:443$39'.
|
|
Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:443$39'.
|
|
Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:318$23'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:318$23'.
|
|
Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:272$14'.
|
|
Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:250$13'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:250$13'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:231$11'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:231$11'.
|
|
Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:220$9'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:220$9'.
|
|
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:210$6'.
|
|
Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:210$6'.
|
|
Removing empty process `BufferCC_1_.$proc$PQVexRiscvUlx3s.v:132$2'.
|
|
Removing empty process `BufferCC.$proc$PQVexRiscvUlx3s.v:109$1'.
|
|
Cleaned up 839 empty switches.
|
|
|
|
2.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module PipelinedMemoryBusArbiter_2_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter_1_.
|
|
Deleting now unused module PipelinedMemoryBusArbiter.
|
|
Deleting now unused module PipelinedMemoryBusDecoder_1_.
|
|
Deleting now unused module PipelinedMemoryBusDecoder.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s_1_.
|
|
Deleting now unused module PipelinedMemoryBusRamUlx3s.
|
|
Deleting now unused module Apb3Router.
|
|
Deleting now unused module Apb3Decoder.
|
|
Deleting now unused module MyMem.
|
|
Deleting now unused module Apb3UartCtrl.
|
|
Deleting now unused module PipelinedMemoryBusToApbBridge.
|
|
Deleting now unused module SystemDebugger.
|
|
Deleting now unused module JtagBridge.
|
|
Deleting now unused module VexRiscv.
|
|
Deleting now unused module BufferCC_2_.
|
|
Deleting now unused module StreamFork_1_.
|
|
Deleting now unused module StreamArbiter_1_.
|
|
Deleting now unused module StreamFifoLowLatency_1_.
|
|
Deleting now unused module StreamFork.
|
|
Deleting now unused module StreamArbiter.
|
|
Deleting now unused module AESCore_Std.
|
|
Deleting now unused module StreamFifo.
|
|
Deleting now unused module UartCtrl.
|
|
Deleting now unused module FlowCCByToggle.
|
|
Deleting now unused module StreamFifoLowLatency.
|
|
Deleting now unused module AESKeyScheduleCore_Std.
|
|
Deleting now unused module AESEngine_Std.
|
|
Deleting now unused module UartCtrlRx.
|
|
Deleting now unused module UartCtrlTx.
|
|
Deleting now unused module BufferCC_1_.
|
|
Deleting now unused module BufferCC.
|
|
<suppressed ~34 debug messages>
|
|
|
|
2.6. Executing TRIBUF pass.
|
|
|
|
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
2.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~521 debug messages>
|
|
|
|
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 311 unused cells and 3537 unused wires.
|
|
<suppressed ~409 debug messages>
|
|
|
|
2.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~1992 debug messages>
|
|
Removed a total of 664 cells.
|
|
|
|
2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port A of cell $flatten\myMem_1_.\aesCore.\keySchedule.$procmux$4226: \myMem_1_.aesCore.keySchedule.cmdready -> 1'0
|
|
Replacing known input bits on port B of cell $flatten\systemDebugger_1_.$procmux$2642: \systemDebugger_1_.dispatcher_headerLoaded -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\systemDebugger_1_.$procmux$2640: \systemDebugger_1_.dispatcher_headerLoaded -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3303.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3305.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3314.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3342.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3344.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3353.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3371.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3397.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3400.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3406.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3419.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3421.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3427.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3437.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3439.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3445.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3463.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3476.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3478.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3484.
|
|
dead port 1/2 on $mux $flatten\core_cpu.$procmux$3494.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3496.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3502.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3520.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3701.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3734.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3764.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3776.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3785.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3800.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3832.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3857.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3867.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3869.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3875.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3885.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3887.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3893.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3905.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3911.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3920.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3930.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3932.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3938.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3948.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3950.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3956.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3968.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3974.
|
|
dead port 2/2 on $mux $flatten\core_cpu.$procmux$3983.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2688.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2697.
|
|
dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2706.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5785.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$4976.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$4978.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$4984.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$4992.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$4994.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5001.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5010.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5012.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5020.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5031.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5034.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5036.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5038.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5049.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5051.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5053.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5064.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5066.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5068.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5078.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5080.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5089.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5099.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5136.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5153.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5156.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5158.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5160.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5171.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5173.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5175.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5186.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5188.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5190.
|
|
dead port 1/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5200.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5202.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\engine.$procmux$5211.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2488.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5910.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5919.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5922.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5922.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5922.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5922.
|
|
dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5931.
|
|
dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5931.
|
|
dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5931.
|
|
dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5931.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2497.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5941.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5943.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5949.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2506.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2515.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6008.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6010.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6017.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2524.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2535.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$2554.
|
|
dead port 2/2 on $mux $flatten\myMem_1_.\aesCore.\keySchedule.$procmux$4269.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2610.
|
|
dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2619.
|
|
Removed 117 multiplexer ports.
|
|
<suppressed ~533 debug messages>
|
|
|
|
2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3381: $auto$opt_reduce.cc:134:opt_mux$6402
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3389: { $flatten\core_cpu.$procmux$3392_CMP $auto$opt_reduce.cc:134:opt_mux$6404 }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$3466: { }
|
|
New ctrl vector for $mux cell $flatten\core_cpu.$procmux$3523: { }
|
|
New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3664: $auto$opt_reduce.cc:134:opt_mux$6406
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3988:
|
|
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056
|
|
New ports: A=1'0, B=1'1, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0]
|
|
New connections: $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [31:1] = { $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN[31:0]$1056 [0] }
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Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$4107:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746
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New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0]
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New connections: $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [7:1] = { $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$2293:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0]
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New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN[7:0]$1723 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$2299:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0]
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New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN[7:0]$1726 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$2305:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0]
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New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN[7:0]$1729 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$2311:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0]
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New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN[7:0]$1732 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4054:
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Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [0]
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New connections: $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [1] = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [0]
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$2261:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0]
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New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN[7:0]$1763 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$2267:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0]
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New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN[7:0]$1766 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$2273:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0]
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New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN[7:0]$1769 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$2279:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0]
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New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN[7:0]$1772 [0] }
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Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4054:
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Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813
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New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [0]
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New connections: $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [1] = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN[1:0]$813 [0]
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New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5952: { $auto$opt_reduce.cc:134:opt_mux$6408 $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5819_CMP }
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Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$4107:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746
|
|
New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0]
|
|
New connections: $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [7:1] = { $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN[7:0]$746 [0] }
|
|
New ctrl vector for $mux cell $flatten\myMem_1_.\aesCore.\keySchedule.$procmux$4226: { }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 20 changes.
|
|
|
|
2.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~399 debug messages>
|
|
Removed a total of 133 cells.
|
|
|
|
2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$6287 ($adff) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$6394 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$6387 ($dffsr) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$6169 ($dff) from module PQVexRiscvUlx3s.
|
|
|
|
2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 837 unused wires.
|
|
<suppressed ~43 debug messages>
|
|
|
|
2.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~8 debug messages>
|
|
|
|
2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~488 debug messages>
|
|
|
|
2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5818: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5786_CMP $auto$opt_reduce.cc:134:opt_mux$6410 }
|
|
New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5969: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5975_CMP $auto$opt_reduce.cc:134:opt_mux$6412 }
|
|
New ctrl vector for $pmux cell $flatten\jtagBridge_1_.$procmux$2716: { $flatten\jtagBridge_1_.$procmux$2730_CMP $auto$opt_reduce.cc:134:opt_mux$6418 $flatten\jtagBridge_1_.$procmux$2727_CMP $flatten\jtagBridge_1_.$procmux$2726_CMP $flatten\jtagBridge_1_.$procmux$2725_CMP $flatten\jtagBridge_1_.$procmux$2723_CMP $auto$opt_reduce.cc:134:opt_mux$6416 $flatten\jtagBridge_1_.$procmux$2720_CMP $flatten\jtagBridge_1_.$procmux$2719_CMP $flatten\jtagBridge_1_.$procmux$2718_CMP $auto$opt_reduce.cc:134:opt_mux$6414 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 3 changes.
|
|
|
|
2.11.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 4 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.11.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~488 debug messages>
|
|
|
|
2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.11.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.11.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.11.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.11.23. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:5279$739_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7069$871_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:5614$807_EN as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_8_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s._zz_9_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state.
|
|
Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state.
|
|
Not marking PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_code as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_targetPrivilege.
|
|
Not marking PQVexRiscvUlx3s.core_cpu._zz_125_ as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking PQVexRiscvUlx3s.jtagBridge_1_.jtag_tap_fsm_state as FSM state register:
|
|
Register has an initialization value.
|
|
Not marking PQVexRiscvUlx3s.myMem_1_.aesCore.engine.sm_stateReg as FSM state register:
|
|
Circuit seems to be self-resetting.
|
|
|
|
2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$6372
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5819_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5786_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5828_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5840_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:555$59_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
found state code: 3'010
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
found state code: 3'001
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5840_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5828_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5819_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5786_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:555$59_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5786_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5819_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5828_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5840_CMP }
|
|
transition: 3'000 6'-0---- -> 3'000 7'0000001
|
|
transition: 3'000 6'-1---- -> 3'001 7'0010001
|
|
transition: 3'100 6'----0- -> 3'100 7'1000000
|
|
transition: 3'100 6'---01- -> 3'000 7'0000000
|
|
transition: 3'100 6'---110 -> 3'100 7'1000000
|
|
transition: 3'100 6'---111 -> 3'000 7'0000000
|
|
transition: 3'010 6'----0- -> 3'010 7'0101000
|
|
transition: 3'010 6'--0-1- -> 3'010 7'0101000
|
|
transition: 3'010 6'--1-1- -> 3'100 7'1001000
|
|
transition: 3'001 6'----0- -> 3'001 7'0010010
|
|
transition: 3'001 6'---01- -> 3'010 7'0100010
|
|
transition: 3'001 6'---11- -> 3'000 7'0000010
|
|
Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state' from module `\PQVexRiscvUlx3s'.
|
|
found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procdff$6383
|
|
root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0]
|
|
found reset state: 3'000 (from async reset)
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5970_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5975_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5964_CMP
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6001_CMP
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:308$19_Y
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
found state code: 3'001
|
|
found state code: 3'100
|
|
found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
found state code: 3'010
|
|
found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:281$17_Y
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6001_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5975_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5970_CMP
|
|
found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5964_CMP
|
|
ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:281$17_Y $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:308$19_Y }
|
|
ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5964_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5970_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5975_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6001_CMP }
|
|
transition: 3'000 5'---0- -> 3'000 7'0000001
|
|
transition: 3'000 5'---1- -> 3'001 7'0010001
|
|
transition: 3'100 5'--0-- -> 3'100 7'1000000
|
|
transition: 3'100 5'--1-0 -> 3'100 7'1000000
|
|
transition: 3'100 5'0-1-1 -> 3'000 7'0000000
|
|
transition: 3'100 5'1-1-1 -> 3'001 7'0010000
|
|
transition: 3'010 5'--0-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-01-- -> 3'010 7'0100010
|
|
transition: 3'010 5'-11-- -> 3'100 7'1000010
|
|
transition: 3'001 5'--0-- -> 3'001 7'0011000
|
|
transition: 3'001 5'--1-- -> 3'010 7'0101000
|
|
Extracting FSM `\core_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\PQVexRiscvUlx3s'.
|
|
found $dff cell for state register: $flatten\core_cpu.$procdff$6176
|
|
root of input selection tree: $flatten\core_cpu.$0\CsrPlugin_interrupt_targetPrivilege[1:0]
|
|
found ctrl input: \core_cpu.CsrPlugin_mstatus_MIE
|
|
found ctrl input: \core_cpu._zz_164_
|
|
found ctrl input: \core_cpu._zz_163_
|
|
found state code: 2'11
|
|
fsm extraction failed: at least two states are required.
|
|
|
|
2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425' from module `\PQVexRiscvUlx3s'.
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused input signal \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_.
|
|
|
|
2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 30 unused cells and 30 unused wires.
|
|
<suppressed ~31 debug messages>
|
|
|
|
2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [2].
|
|
Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425' from module `\PQVexRiscvUlx3s'.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6001_CMP.
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [0].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [1].
|
|
Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [2].
|
|
|
|
2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425' from module `\PQVexRiscvUlx3s' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ---1
|
|
100 -> --1-
|
|
010 -> -1--
|
|
001 -> 1---
|
|
|
|
2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419 (\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:555$59_Y
|
|
1: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5840_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5828_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5819_CMP
|
|
3: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5786_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'0---- -> 0 4'0001
|
|
1: 0 5'1---- -> 3 4'0001
|
|
2: 1 5'--111 -> 0 4'0000
|
|
3: 1 5'--01- -> 0 4'0000
|
|
4: 1 5'--110 -> 1 4'0000
|
|
5: 1 5'---0- -> 1 4'0000
|
|
6: 2 5'-1-1- -> 1 4'1000
|
|
7: 2 5'---0- -> 2 4'1000
|
|
8: 2 5'-0-1- -> 2 4'1000
|
|
9: 3 5'--11- -> 0 4'0010
|
|
10: 3 5'--01- -> 2 4'0010
|
|
11: 3 5'---0- -> 3 4'0010
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425' from module `PQVexRiscvUlx3s':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425 (\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 3
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:308$19_Y
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:281$17_Y
|
|
2: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow
|
|
3: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_
|
|
4: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid
|
|
|
|
Output signals:
|
|
0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5975_CMP
|
|
1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5970_CMP
|
|
2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$5964_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'---0- -> 0 3'000
|
|
1: 0 5'---1- -> 3 3'000
|
|
2: 1 5'0-1-1 -> 0 3'000
|
|
3: 1 5'--1-0 -> 1 3'000
|
|
4: 1 5'--0-- -> 1 3'000
|
|
5: 1 5'1-1-1 -> 3 3'000
|
|
6: 2 5'-11-- -> 1 3'001
|
|
7: 2 5'--0-- -> 2 3'001
|
|
8: 2 5'-01-- -> 2 3'001
|
|
9: 3 5'--1-- -> 2 3'100
|
|
10: 3 5'--0-- -> 3 3'100
|
|
|
|
-------------------------------------
|
|
|
|
2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$6419' from module `\PQVexRiscvUlx3s'.
|
|
Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$6425' from module `\PQVexRiscvUlx3s'.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~13 debug messages>
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5852.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5852.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5854.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5854.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5856.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5939.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5939.
|
|
dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5947.
|
|
dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5947.
|
|
dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5952.
|
|
dead port 1/4 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$6024.
|
|
Removed 11 multiplexer ports.
|
|
<suppressed ~486 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$6066 ($dff) from module PQVexRiscvUlx3s (D = \asyncReset_buffercc.buffers_1, Q = \resetCtrl_systemClockReset, rval = 1'1).
|
|
Adding EN signal on $procdff$6065 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:12503$1897_Y, Q = \_zz_30_).
|
|
Adding EN signal on $procdff$6064 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_24_[0:0], Q = \_zz_24_).
|
|
Adding EN signal on $procdff$6063 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:12494$1896_Y, Q = \_zz_11_).
|
|
Adding EN signal on $procdff$6062 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_5_[0:0], Q = \_zz_5_).
|
|
Adding EN signal on $procdff$6061 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12531$1906_Y, Q = \_zz_34_).
|
|
Adding EN signal on $procdff$6060 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12530$1905_Y, Q = \_zz_33_).
|
|
Adding EN signal on $procdff$6059 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12529$1904_Y, Q = \_zz_32_).
|
|
Adding EN signal on $procdff$6058 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12528$1903_Y, Q = \_zz_31_).
|
|
Adding EN signal on $procdff$6057 ($dff) from module PQVexRiscvUlx3s (D = \_zz_21_, Q = \_zz_28_).
|
|
Adding EN signal on $procdff$6056 ($dff) from module PQVexRiscvUlx3s (D = \_zz_20_, Q = \_zz_27_).
|
|
Adding EN signal on $procdff$6055 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB, Q = \_zz_26_).
|
|
Adding EN signal on $procdff$6054 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \_zz_25_).
|
|
Adding EN signal on $procdff$6053 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12519$1902_Y, Q = \_zz_15_).
|
|
Adding EN signal on $procdff$6052 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12518$1901_Y, Q = \_zz_14_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6557 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_8_, Q = \_zz_14_, rval = 0).
|
|
Adding EN signal on $procdff$6051 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12517$1900_Y, Q = \_zz_13_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6559 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_7_ [1:0], Q = \_zz_13_ [1:0], rval = 2'00).
|
|
Adding EN signal on $procdff$6050 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:12516$1899_Y, Q = \_zz_12_).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6561 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_6_, Q = \_zz_12_, rval = 1'0).
|
|
Adding EN signal on $procdff$6049 ($dff) from module PQVexRiscvUlx3s (D = 4'xxxx, Q = \_zz_9_).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$6563 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$6563 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$6563 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$6563 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$6048 ($dff) from module PQVexRiscvUlx3s (D = 0, Q = \_zz_8_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$6564 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$6047 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, Q = \_zz_7_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6565 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6565 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $procdff$6046 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \_zz_6_).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6566 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$6131 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$procmux$2636_Y, Q = \systemDebugger_1_.dispatcher_counter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$6130 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_headerLoaded[0:0], Q = \systemDebugger_1_.dispatcher_headerLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$6129 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_dataLoaded[0:0], Q = \systemDebugger_1_.dispatcher_dataLoaded).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$6128 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_headerShifter [7:1] }, Q = \systemDebugger_1_.dispatcher_headerShifter).
|
|
Adding EN signal on $flatten\systemDebugger_1_.$procdff$6127 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_dataShifter [66:1] }, Q = \systemDebugger_1_.dispatcher_dataShifter).
|
|
Adding SRST signal on $flatten\pipelinedMemoryBusToApbBridge_1_.$procdff$6124 ($dff) from module PQVexRiscvUlx3s (D = { \apb3Router_1_.io_outputs_1_PRDATA [31:29] \apb3Router_1_.io_outputs_1_PRDATA [23:21] \apb3Router_1_.io_outputs_1_PRDATA [14:10] }, Q = { \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [31:29] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [23:21] \pipelinedMemoryBusToApbBridge_1_.pipelinedMemoryBusStage_rsp_regNext_payload_data [14:10] }, rval = 11'00000000000).
|
|
Adding EN signal on $flatten\myMem_1_.\aesCore.\keySchedule.$procdff$6333 ($dff) from module PQVexRiscvUlx3s (D = $flatten\myMem_1_.\aesCore.\keySchedule.$0\cntRound[3:0], Q = \myMem_1_.aesCore.keySchedule.cntRound).
|
|
Adding EN signal on $flatten\myMem_1_.\aesCore.\engine.$procdff$6364 ($adff) from module PQVexRiscvUlx3s (D = \myMem_1_.aesCore.engine.sm_stateNext, Q = \myMem_1_.aesCore.engine.sm_stateReg).
|
|
Adding EN signal on $flatten\myMem_1_.\aesCore.\engine.$procdff$6361 ($adff) from module PQVexRiscvUlx3s (D = $flatten\myMem_1_.\aesCore.\engine.$0\keyMode[0:0], Q = \myMem_1_.aesCore.engine.keyMode).
|
|
Adding SRST signal on $flatten\myMem_1_.\aesCore.\engine.$procdff$6359 ($dff) from module PQVexRiscvUlx3s (D = $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:4681$656_Y, Q = \myMem_1_.aesCore.engine.mixColumn_cntColumn, rval = 4'0000).
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Adding EN signal on $flatten\myMem_1_.\aesCore.\engine.$procdff$6358 ($dff) from module PQVexRiscvUlx3s (D = $flatten\myMem_1_.\aesCore.\engine.$0\cntRound[3:0], Q = \myMem_1_.aesCore.engine.cntRound).
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Adding EN signal on $flatten\myMem_1_.$procdff$6116 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \myMem_1_._zz_8_).
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Adding EN signal on $flatten\myMem_1_.$procdff$6113 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_1_ [127:96]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6113 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_1_ [31:0]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6113 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_1_ [63:32]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6113 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_1_ [95:64]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6112 ($dff) from module PQVexRiscvUlx3s (D = { \myMem_1_.aesCore.engine.dataState_0 \myMem_1_.aesCore.engine.dataState_1 \myMem_1_.aesCore.engine.dataState_2 \myMem_1_.aesCore.engine.dataState_3 \myMem_1_.aesCore.engine.dataState_4 \myMem_1_.aesCore.engine.dataState_5 \myMem_1_.aesCore.engine.dataState_6 \myMem_1_.aesCore.engine.dataState_7 \myMem_1_.aesCore.engine.dataState_8 \myMem_1_.aesCore.engine.dataState_9 \myMem_1_.aesCore.engine.dataState_10 \myMem_1_.aesCore.engine.dataState_11 \myMem_1_.aesCore.engine.dataState_12 \myMem_1_.aesCore.engine.dataState_13 \myMem_1_.aesCore.engine.dataState_14 \myMem_1_.aesCore.engine.dataState_15 }, Q = \myMem_1_._zz_5_).
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Adding EN signal on $flatten\myMem_1_.$procdff$6111 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \myMem_1_._zz_3_).
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Adding EN signal on $flatten\myMem_1_.$procdff$6110 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [31:0]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6110 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [63:32]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6110 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [95:64]).
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Adding EN signal on $flatten\myMem_1_.$procdff$6110 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_._zz_2_ [127:96]).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$6304 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$6300 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_1_).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$6299 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_2_).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$6303 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.locked).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$6302 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_1).
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Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$6301 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_0).
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Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$6091 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:11228$1759_DATA, Q = \memory_ramBlocks_1._zz_8_).
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Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$6090 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:11227$1758_DATA, Q = \memory_ramBlocks_1._zz_7_).
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Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$6089 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:11226$1757_DATA, Q = \memory_ramBlocks_1._zz_6_).
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Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$6088 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:11225$1756_DATA, Q = \memory_ramBlocks_1._zz_5_).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$6304 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$6311 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_1_).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$6310 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_2_).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$6314 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.locked).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$6313 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_1).
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Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$6312 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_0).
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Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$6108 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:11160$1719_DATA, Q = \memory_ramBlocks_0._zz_8_).
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Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$6107 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:11159$1718_DATA, Q = \memory_ramBlocks_0._zz_7_).
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Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$6106 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:11158$1717_DATA, Q = \memory_ramBlocks_0._zz_6_).
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Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$6105 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:11157$1716_DATA, Q = \memory_ramBlocks_0._zz_5_).
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Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$6330 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tdi, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_fragment).
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Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$6329 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tms, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_last).
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Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$6328 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.\flowCCByToggle_1_.$logic_not$PQVexRiscvUlx3s.v:5077$730_Y, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_target).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$6141 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.DebugPlugin_busReadDataReg [31:5] \jtagBridge_1_.io_remote_rsp_payload_data [4:0] }, Q = \jtagBridge_1_.system_rsp_payload_data).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$6140 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_payload_error).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6701 ($dffe) from module PQVexRiscvUlx3s.
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$6139 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2680_Y, Q = \jtagBridge_1_.system_rsp_valid, rval = 1'1).
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Adding EN signal on $auto$opt_dff.cc:702:run$6702 ($sdff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_valid).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$6138 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2658_Y, Q = \jtagBridge_1_.jtag_readArea_shifter).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$6137 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2664_Y, Q = \jtagBridge_1_.jtag_idcodeArea_shifter, rval = 268443647).
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Adding EN signal on $auto$opt_dff.cc:702:run$6709 ($sdff) from module PQVexRiscvUlx3s (D = { \io_jtag_tdi \jtagBridge_1_.jtag_idcodeArea_shifter [31:1] }, Q = \jtagBridge_1_.jtag_idcodeArea_shifter).
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Adding EN signal on $flatten\jtagBridge_1_.$procdff$6135 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$0\jtag_tap_instructionShift[3:0], Q = \jtagBridge_1_.jtag_tap_instructionShift).
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Adding SRST signal on $flatten\jtagBridge_1_.$procdff$6134 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2672_Y, Q = \jtagBridge_1_.jtag_tap_instruction, rval = 4'0001).
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Adding EN signal on $auto$opt_dff.cc:702:run$6716 ($sdff) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_tap_instructionShift, Q = \jtagBridge_1_.jtag_tap_instruction).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$6069 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_1, Q = \core_ibus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_ibus_decoder.$procdff$6068 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_0, Q = \core_ibus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$6073 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_2, Q = \core_dbus_decoder.logic_rspHits_2).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$6072 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_1, Q = \core_dbus_decoder.logic_rspHits_1).
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Adding EN signal on $flatten\core_dbus_decoder.$procdff$6071 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_0, Q = \core_dbus_decoder.logic_rspHits_0).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$6332 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.pushing, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.risingOccupancy).
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Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$6331 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_payload_inst 1'0 }, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c._zz_3_).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6724 ($dffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$6286 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_2).
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Adding EN signal on $flatten\core_cpu.$procdff$6285 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_1).
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Adding EN signal on $flatten\core_cpu.$procdff$6284 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_0).
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Adding EN signal on $flatten\core_cpu.$procdff$6282 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mie_MSIE).
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Adding EN signal on $flatten\core_cpu.$procdff$6281 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [7], Q = \core_cpu.CsrPlugin_mie_MTIE).
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Adding EN signal on $flatten\core_cpu.$procdff$6280 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [11], Q = \core_cpu.CsrPlugin_mie_MEIE).
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Adding EN signal on $flatten\core_cpu.$procdff$6276 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [31:2], Q = \core_cpu.CsrPlugin_mtvec_base).
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Adding EN signal on $flatten\core_cpu.$procdff$6275 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [1:0], Q = \core_cpu.CsrPlugin_mtvec_mode).
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Adding EN signal on $flatten\core_cpu.$procdff$6266 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \core_cpu.IBusSimplePlugin_fetchPc_inc).
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Adding EN signal on $flatten\core_cpu.$procdff$6263 ($adff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \core_cpu.IBusSimplePlugin_fetchPc_pcReg).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6760 ($adffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6760 ($adffe) from module PQVexRiscvUlx3s.
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Adding EN signal on $flatten\core_cpu.$procdff$6261 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_arbitration_isValid[0:0], Q = \core_cpu.memory_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$6260 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\execute_arbitration_isValid[0:0], Q = \core_cpu.execute_arbitration_isValid).
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Adding EN signal on $flatten\core_cpu.$procdff$6259 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_125_[2:0], Q = \core_cpu._zz_125_).
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Adding EN signal on $flatten\core_cpu.$procdff$6256 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_59_[0:0], Q = \core_cpu._zz_59_).
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Adding EN signal on $flatten\core_cpu.$procdff$6255 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_57_[0:0], Q = \core_cpu._zz_57_).
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Adding EN signal on $flatten\core_cpu.$procdff$6254 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_55_[0:0], Q = \core_cpu._zz_55_).
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Adding EN signal on $flatten\core_cpu.$procdff$6253 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9752$1578_Y, Q = \core_cpu.execute_CsrPlugin_csr_2946).
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Adding EN signal on $flatten\core_cpu.$procdff$6252 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9749$1576_Y, Q = \core_cpu.execute_CsrPlugin_csr_2818).
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Adding EN signal on $flatten\core_cpu.$procdff$6251 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9746$1574_Y, Q = \core_cpu.execute_CsrPlugin_csr_2944).
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Adding EN signal on $flatten\core_cpu.$procdff$6250 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9743$1572_Y, Q = \core_cpu.execute_CsrPlugin_csr_2816).
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Adding EN signal on $flatten\core_cpu.$procdff$6249 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9740$1570_Y, Q = \core_cpu.execute_CsrPlugin_csr_834).
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Adding EN signal on $flatten\core_cpu.$procdff$6248 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9737$1568_Y, Q = \core_cpu.execute_CsrPlugin_csr_773).
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Adding EN signal on $flatten\core_cpu.$procdff$6247 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9734$1566_Y, Q = \core_cpu.execute_CsrPlugin_csr_772).
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Adding EN signal on $flatten\core_cpu.$procdff$6246 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9731$1564_Y, Q = \core_cpu.execute_CsrPlugin_csr_836).
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Adding EN signal on $flatten\core_cpu.$procdff$6245 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9728$1562_Y, Q = \core_cpu.execute_CsrPlugin_csr_768).
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Adding EN signal on $flatten\core_cpu.$procdff$6244 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS1_SIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$6242 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_LESS_UNSIGNED, Q = \core_cpu.decode_to_execute_SRC_LESS_UNSIGNED).
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Adding EN signal on $flatten\core_cpu.$procdff$6241 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_43_, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_DATA).
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Adding EN signal on $flatten\core_cpu.$procdff$6240 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_353_ \core_cpu._zz_354_ }, Q = \core_cpu.decode_to_execute_BRANCH_CTRL).
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Adding EN signal on $flatten\core_cpu.$procdff$6239 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HH, Q = \core_cpu.execute_to_memory_MUL_HH).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6238 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HL, Q = \core_cpu.execute_to_memory_MUL_HL).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6236 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_ENABLE, Q = \core_cpu.execute_to_memory_MEMORY_ENABLE).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6235 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_ENABLE, Q = \core_cpu.decode_to_execute_MEMORY_ENABLE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6234 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_DIV, Q = \core_cpu.execute_to_memory_IS_DIV).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6233 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_DIV, Q = \core_cpu.decode_to_execute_IS_DIV).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6232 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_CSR_WRITE_OPCODE, Q = \core_cpu.decode_to_execute_CSR_WRITE_OPCODE).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6230 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_VALID).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6229 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_REGFILE_WRITE_VALID, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID).
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|
Adding SRST signal on $auto$opt_dff.cc:764:run$6806 ($dffe) from module PQVexRiscvUlx3s (D = \core_cpu._zz_191_, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6228 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.execute_to_memory_BYPASSABLE_MEMORY_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6227 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6226 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_175_ [31:0], Q = \core_cpu.execute_to_memory_SHIFT_RIGHT).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6225 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LH, Q = \core_cpu.execute_to_memory_MUL_LH).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6223 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC2, Q = \core_cpu.execute_to_memory_SRC2).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6222 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2, Q = \core_cpu.decode_to_execute_SRC2).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6220 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC1, Q = \core_cpu.execute_to_memory_SRC1).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6219 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC1, Q = \core_cpu.decode_to_execute_SRC1).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6218 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2_FORCE_ZERO, Q = \core_cpu.decode_to_execute_SRC2_FORCE_ZERO).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6217 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_291_ \core_cpu._zz_303_ }, Q = \core_cpu.decode_to_execute_ALU_BITWISE_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6216 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \core_cpu.execute_to_memory_BRANCH_CALC).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6818 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6214 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_MUL, Q = \core_cpu.execute_to_memory_IS_MUL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6213 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_MUL, Q = \core_cpu.decode_to_execute_IS_MUL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6212 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_CSR, Q = \core_cpu.decode_to_execute_IS_CSR).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6210 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB [1:0], Q = \core_cpu.execute_to_memory_MEMORY_ADDRESS_LOW).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6209 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_INSTRUCTION, Q = \core_cpu.execute_to_memory_INSTRUCTION).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6208 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_62_, Q = \core_cpu.decode_to_execute_INSTRUCTION).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6206 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_DO_EBREAK, Q = \core_cpu.decode_to_execute_DO_EBREAK).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6205 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_27_, Q = \core_cpu.decode_to_execute_RS2).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6204 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_EXECUTE_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6203 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SHIFT_CTRL, Q = \core_cpu.execute_to_memory_SHIFT_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6202 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_10_ [1] \core_cpu._zz_313_ }, Q = \core_cpu.decode_to_execute_SHIFT_CTRL).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6199 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.decode_to_execute_PC).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6198 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_BRANCH_DO, Q = \core_cpu.execute_to_memory_BRANCH_DO).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6197 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_329_ \core_cpu._zz_331_ }, Q = \core_cpu.decode_to_execute_ALU_CTRL).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6196 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS2_SIGNED).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6194 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \core_cpu.execute_to_memory_MEMORY_STORE).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6193 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_STORE, Q = \core_cpu.decode_to_execute_MEMORY_STORE).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6191 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_ENV_CTRL, Q = \core_cpu.execute_to_memory_ENV_CTRL).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6190 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_20_, Q = \core_cpu.decode_to_execute_ENV_CTRL).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6188 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LL, Q = \core_cpu.execute_to_memory_MUL_LL).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6187 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_29_, Q = \core_cpu.decode_to_execute_RS1).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6186 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_USE_SUB_LESS, Q = \core_cpu.decode_to_execute_SRC_USE_SUB_LESS).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6182 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_228_ [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_div_result).
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|
Adding SRST signal on $flatten\core_cpu.$procdff$6181 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$3009_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_done, rval = 1'0).
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|
Adding EN signal on $auto$opt_dff.cc:702:run$6846 ($sdff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.memory_MulDivIterativePlugin_div_done).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6180 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$logic_and$PQVexRiscvUlx3s.v:9536$1497_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_needRevert).
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Adding SRST signal on $flatten\core_cpu.$procdff$6179 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2855_Y, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0], rval = 0).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6179 ($dff) from module PQVexRiscvUlx3s (D = 33'000000000000000000000000000000000, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [64:32]).
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Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$6850 ($dffe) from module PQVexRiscvUlx3s.
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|
Adding EN signal on $auto$opt_dff.cc:702:run$6849 ($sdff) from module PQVexRiscvUlx3s (D = \core_cpu.memory_MulDivIterativePlugin_div_stage_0_outRemainder, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0]).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6178 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9535$1488_Y, Q = \core_cpu.memory_MulDivIterativePlugin_rs2).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6177 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485_Y [32], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [32]).
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Adding EN signal on $flatten\core_cpu.$procdff$6177 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0] [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [31:0]).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6176 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$3031_Y, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege).
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Adding SRST signal on $auto$opt_dff.cc:764:run$6869 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege, rval = 2'11).
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|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$6872 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$6872 ($sdffce) from module PQVexRiscvUlx3s.
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|
Adding EN signal on $flatten\core_cpu.$procdff$6175 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$3039_Y, Q = \core_cpu.CsrPlugin_interrupt_code).
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|
Adding SRST signal on $auto$opt_dff.cc:764:run$6877 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$3037_Y [3], Q = \core_cpu.CsrPlugin_interrupt_code [3], rval = 1'1).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6877 ($dffe) from module PQVexRiscvUlx3s (D = 3'xxx, Q = \core_cpu.CsrPlugin_interrupt_code [2:0], rval = 3'011).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$6881 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$6881 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$6881 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6174 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9488$1478_Y, Q = \core_cpu.CsrPlugin_minstret).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6172 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.CsrPlugin_interrupt_code, Q = \core_cpu.CsrPlugin_mcause_exceptionCode).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6171 ($dff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.CsrPlugin_mcause_interrupt).
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$6888 ($dffe) from module PQVexRiscvUlx3s.
|
|
Adding SRST signal on $flatten\core_cpu.$procdff$6170 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mip_MSIP, rval = 1'0).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6167 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.CsrPlugin_mepc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6162 ($dff) from module PQVexRiscvUlx3s (D = { $flatten\core_cpu.$0\_zz_62_[31:0] [31:25] $flatten\core_cpu.$0\_zz_62_[31:0] [14:0] }, Q = { \core_cpu._zz_62_ [31:25] \core_cpu._zz_62_ [14:0] }).
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|
Adding EN signal on $flatten\core_cpu.$procdff$6160 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_58_, Q = \core_cpu._zz_60_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6159 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_fetchPc_pcReg, Q = \core_cpu._zz_58_).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6157 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\DebugPlugin_busReadDataReg[31:0], Q = \core_cpu.DebugPlugin_busReadDataReg).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6156 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6155 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6154 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_pc).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6149 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6148 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6147 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_valid).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6144 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [36], Q = \core_cpu.DebugPlugin_stepIt).
|
|
Adding EN signal on $flatten\core_cpu.$procdff$6142 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2816_Y, Q = \core_cpu.DebugPlugin_resetIt).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$6318 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$6378 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\break_counter[6:0], Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.break_counter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$6375 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_2).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$6374 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.io_rxd_buffercc.buffers_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$6368 ($dff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$or$PQVexRiscvUlx3s.v:0$80_Y, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_shifter).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$6318 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_risingOccupancy).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$6121 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readOverflowError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readOverflowError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$6120 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readError).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$6119 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_readIntEnable).
|
|
Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$6118 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_writeIntEnable).
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 228 unused cells and 250 unused wires.
|
|
<suppressed ~233 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~34 debug messages>
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~344 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~51 debug messages>
|
|
Removed a total of 17 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6899 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6899 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$6885 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$6885 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$6885 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$6562 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$6560 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$6560 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 30 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 31 on $auto$opt_dff.cc:702:run$6558 ($sdffce) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 25 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.13.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~345 debug messages>
|
|
|
|
2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6898 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6898 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$6556 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$6556 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$6556 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$6556 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~345 debug messages>
|
|
|
|
2.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6894 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6894 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$6830 ($dffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$6830 ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~345 debug messages>
|
|
|
|
2.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6902 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2826_Y [1:0], Q = \core_cpu.DebugPlugin_busReadDataReg [1:0], rval = 2'00).
|
|
|
|
2.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.37. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~346 debug messages>
|
|
|
|
2.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.40. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.41. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.13.43. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.13.44. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 24 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$meminit$\sBoxMem$PQVexRiscvUlx3s.v:0$661 (myMem_1_.aesCore.engine.sBoxMem).
|
|
Removed top 24 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$meminit$\sBoxMemInv$PQVexRiscvUlx3s.v:0$662 (myMem_1_.aesCore.engine.sBoxMemInv).
|
|
Removed top 28 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$meminit$\rconMem$PQVexRiscvUlx3s.v:0$703 (myMem_1_.aesCore.keySchedule.rconMem).
|
|
Removed top 24 address bits (of 32) from memory init port PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$meminit$\sBoxMem$PQVexRiscvUlx3s.v:0$704 (myMem_1_.aesCore.keySchedule.sBoxMem).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$2192 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$procmux$2198 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6861 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6777 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6770 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6686 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6670 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$6492 ($eq).
|
|
Removed top 31 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$6294 ($dff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$6290 ($adff).
|
|
Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$auto$opt_dff.cc:764:run$6823 ($dffe).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3992 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3990 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3856_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3654_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3647_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3544_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3540_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3535_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3531_CMP0 ($eq).
|
|
Removed top 12 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3385 ($pmux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3379_CMP0 ($eq).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3304_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3233 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3229 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3226 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3225_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3224_CMP0 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3223_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3221 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3215 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3211 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3195 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3101 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3099 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3095 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3093 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3089 ($mux).
|
|
Removed top 7 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3061 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3037 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3017 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3015 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2826 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2814 ($mux).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2750_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2742_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2735_CMP0 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9740$1570 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9737$1568 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9734$1566 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9731$1564 ($eq).
|
|
Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:9728$1562 ($eq).
|
|
Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9535$1488 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485 ($add).
|
|
Removed top 1 bits (of 33) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:9534$1484 ($mux).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:9534$1483 ($not).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:9534$1483 ($not).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9488$1478 ($add).
|
|
Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9486$1477 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:9318$1449 ($sub).
|
|
Removed top 20 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:9186$1419 ($or).
|
|
Removed top 19 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:9186$1418 ($or).
|
|
Removed top 20 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:9186$1418 ($or).
|
|
Removed top 19 bits (of 32) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:9186$1418 ($or).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8983$1341 ($sub).
|
|
Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8974$1340 ($add).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8920$1328 ($add).
|
|
Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8920$1328 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8803$1313 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8700$1297 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8518$1279 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8518$1278 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8517$1274 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:8517$1273 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8516$1272 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:8516$1271 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8514$1268 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:8514$1267 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:8513$1266 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:8513$1265 ($and).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8233$1186 ($sub).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7658$1059 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7051$1042 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7051$1041 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7051$1040 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7051$1039 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7051$1038 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7051$1037 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7049$1036 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7049$1035 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7041$1031 ($eq).
|
|
Removed top 3 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7041$1030 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7040$1029 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7040$1028 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7039$1027 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7039$1026 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7038$1025 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7038$1024 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7037$1023 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7037$1022 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7036$1021 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7036$1020 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7034$1019 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7028$1015 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7026$1014 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7026$1013 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7025$1012 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7017$1006 ($eq).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7015$1005 ($eq).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7015$1004 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7007$1000 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7007$999 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7006$998 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7005$996 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7005$995 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7004$994 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:7003$992 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7003$991 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:7001$990 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6999$989 ($and).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6997$988 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6995$987 ($and).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6989$983 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6989$982 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6988$981 ($eq).
|
|
Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6988$980 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6987$979 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6983$973 ($eq).
|
|
Removed top 11 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6983$972 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6981$971 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6981$970 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6980$969 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6980$968 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6976$966 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6974$965 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6968$961 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6966$960 ($eq).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6966$959 ($eq).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6965$957 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6963$956 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6963$955 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6961$953 ($and).
|
|
Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6960$952 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6960$951 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6959$950 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6959$949 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6957$948 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6949$945 ($eq).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6949$944 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6947$943 ($and).
|
|
Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6945$942 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6944$941 ($eq).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6944$940 ($and).
|
|
Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6943$939 ($eq).
|
|
Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6943$938 ($and).
|
|
Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6941$937 ($and).
|
|
Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:6935$934 ($eq).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6930$931 ($and).
|
|
Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6928$930 ($and).
|
|
Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6926$929 ($and).
|
|
Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928 ($add).
|
|
Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928 ($add).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6899$924 ($add).
|
|
Removed top 31 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:6890$919 ($mux).
|
|
Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6886$915 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6874$912 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911 ($sub).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6870$910 ($and).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6870$910 ($and).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:6870$910 ($and).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:6870$909 ($not).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:6870$909 ($not).
|
|
Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sshr$PQVexRiscvUlx3s.v:6853$903 ($sshr).
|
|
Removed top 15 bits (of 48) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6847$902 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2731_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2730_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2727_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2726_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2725_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2671_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2670_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2656 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:10123$1612 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:10108$1609 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:10107$1608 ($eq).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10075$1606 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10069$1604 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10066$1603 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10063$1602 ($mux).
|
|
Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10057$1600 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10045$1596 ($mux).
|
|
Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10036$1593 ($mux).
|
|
Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10033$1592 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2652 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2650 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2646 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2634 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:10228$1628 ($add).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6630 ($ne).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6610 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6608 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6601 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6597 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$6595 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$6518 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$4109 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$4111 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$6321 ($dff).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$4109 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$4111 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$6321 ($dff).
|
|
Removed top 19 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5212$738 ($sub).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:320$24 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:224$10 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$6474 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$6470 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$5866 ($mux).
|
|
Removed top 7 bits (of 8) from port A of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$shl$PQVexRiscvUlx3s.v:0$77 ($shl).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:573$66 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:567$65 ($sub).
|
|
Removed top 6 bits (of 7) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:510$56 ($add).
|
|
Removed top 2 bits (of 5) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$2479_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$2472 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$2470 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$2466 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$2464 ($mux).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5778_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5777_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5776_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5775_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5774_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5773_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5772_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5285_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5284_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5283_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5282_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5281_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5280_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5279_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5268_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5267_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5266_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5265_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5264_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5263_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5262_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5251_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5250_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5249_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5248_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5247_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5246_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5245_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5234_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5233_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5232_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5231_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5230_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5229_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5228_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5097 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5087 ($mux).
|
|
Removed top 1 bits (of 3) from mux cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5062 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$5018 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4982 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4950 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4946 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4942 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4939 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4290_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4288 ($mux).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4287_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4285 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4283 ($mux).
|
|
Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP0 ($eq).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4279 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$procmux$4277 ($mux).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sub$PQVexRiscvUlx3s.v:4694$659 ($sub).
|
|
Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:4681$656 ($add).
|
|
Removed top 15 bits (of 16) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577 ($sshl).
|
|
Removed top 15 bits (of 16) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl).
|
|
Removed top 15 bits (of 16) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 ($sshl).
|
|
Removed top 15 bits (of 16) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 ($sshl).
|
|
Removed top 15 bits (of 16) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560 ($sshl).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3760$559 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3595$546 ($add).
|
|
Removed top 2 bits (of 4) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1398$93 ($add).
|
|
Removed top 2 bits (of 4) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1397$92 ($add).
|
|
Removed top 3 bits (of 4) from port A of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1396$91 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$procmux$4217 ($mux).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$add$PQVexRiscvUlx3s.v:4878$698 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$eq$PQVexRiscvUlx3s.v:4846$695 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\keySchedule.$sub$PQVexRiscvUlx3s.v:4771$681 ($sub).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2441_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2440_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2439_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2438_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2434_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2426_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2417_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2413_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2404_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2398_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2386_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2375_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2365_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2357_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2350_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$2344_CMP0 ($eq).
|
|
Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:11036$1704 ($eq).
|
|
Removed top 3 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:11035$1701 ($eq).
|
|
Removed top 3 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\apb3Router_1_.$procmux$2329 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$6104 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$6101 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$6098 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$6095 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2315 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2313 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2309 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2307 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2303 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2301 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2297 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$2295 ($mux).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$6087 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$6084 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$6081 ($dff).
|
|
Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$6078 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2283 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2281 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2277 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2275 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2271 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2269 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2265 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$2263 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$procmux$2259_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:11397$1831 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:11321$1790 ($add).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:11519$1868 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:11459$1834 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4056 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4058 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$6309 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$4060 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$4064 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5461$782 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:5471$791 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procmux$4078 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820 ($add).
|
|
Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826 ($add).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4056 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$4058 ($mux).
|
|
Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$6309 ($dff).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3998 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$4002 ($mux).
|
|
Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5753$845 ($sub).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:5763$854 ($mux).
|
|
Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procmux$4016 ($mux).
|
|
Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911 ($sub).
|
|
Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911 ($sub).
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0].
|
|
Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485_Y.
|
|
Removed top 1 bits (of 2) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:6870$909_Y.
|
|
Removed top 19 bits (of 32) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:9186$1418_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10033$1592_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10036$1593_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10045$1596_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10057$1600_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10063$1602_Y.
|
|
Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10066$1603_Y.
|
|
Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10069$1604_Y.
|
|
Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10075$1606_Y.
|
|
Removed top 1 bits (of 3) from wire PQVexRiscvUlx3s.$flatten\myMem_1_.\aesCore.\engine.$5\sm_stateNext[2:0].
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3Router_1__io_input_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3UartCtrl_1__io_apb_PRDATA.
|
|
Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.io_apb_decoder_io_input_PRDATA.
|
|
|
|
2.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 91 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.17. Executing SHARE pass (SAT-based resource sharing).
|
|
Found 12 cells in module PQVexRiscvUlx3s that may be considered for resource sharing.
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4782$686 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Found 3 candidates: $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685 $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684 $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4782$686: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4782$686: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4782$686: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Found 2 candidates: $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684 $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Found 1 candidates: $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Size of SAT problem: 11 cells, 113 variables, 274 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.keySchedule.updateKey_storeKey = 1'1
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\rconMem$PQVexRiscvUlx3s.v:4775$682 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.keySchedule.updateKey_storeKey.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577 ($sshl):
|
|
Found 1 activation_patterns using ctrl signal \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid.
|
|
Found 4 candidates: $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Size of SAT problem: 2 cells, 24 variables, 57 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_68_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [0] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [1] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [2] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [3] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [4] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [5] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [6] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [7] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [8] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [9] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [10] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [11] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [12] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [13] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [14] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [15] } = 2'10
|
|
Size of SAT problem: 2 cells, 90 variables, 222 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ } = 17'10000000000000000
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_68_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [0] \myMem_1_.aesCore.engine._zz_53_ [0] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [1] \myMem_1_.aesCore.engine._zz_53_ [1] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [2] \myMem_1_.aesCore.engine._zz_53_ [2] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [3] \myMem_1_.aesCore.engine._zz_53_ [3] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [4] \myMem_1_.aesCore.engine._zz_53_ [4] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [5] \myMem_1_.aesCore.engine._zz_53_ [5] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [6] \myMem_1_.aesCore.engine._zz_53_ [6] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [7] \myMem_1_.aesCore.engine._zz_53_ [7] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [8] \myMem_1_.aesCore.engine._zz_53_ [8] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [9] \myMem_1_.aesCore.engine._zz_53_ [9] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [10] \myMem_1_.aesCore.engine._zz_53_ [10] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [11] \myMem_1_.aesCore.engine._zz_53_ [11] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [12] \myMem_1_.aesCore.engine._zz_53_ [12] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [13] \myMem_1_.aesCore.engine._zz_53_ [13] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [14] \myMem_1_.aesCore.engine._zz_53_ [14] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [15] \myMem_1_.aesCore.engine._zz_53_ [15] } = 3'100
|
|
Size of SAT problem: 2 cells, 137 variables, 331 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ } = 33'100000000000000010111111111011110
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560 ($sshl):
|
|
Found 17 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_2_ \myMem_1_.aesCore.engine._zz_68_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [0] \myMem_1_.aesCore.engine._zz_38_ [0] \myMem_1_.aesCore.engine._zz_53_ [0] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [1] \myMem_1_.aesCore.engine._zz_38_ [1] \myMem_1_.aesCore.engine._zz_53_ [1] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [2] \myMem_1_.aesCore.engine._zz_38_ [2] \myMem_1_.aesCore.engine._zz_53_ [2] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [3] \myMem_1_.aesCore.engine._zz_38_ [3] \myMem_1_.aesCore.engine._zz_53_ [3] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [4] \myMem_1_.aesCore.engine._zz_38_ [4] \myMem_1_.aesCore.engine._zz_53_ [4] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [5] \myMem_1_.aesCore.engine._zz_38_ [5] \myMem_1_.aesCore.engine._zz_53_ [5] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [6] \myMem_1_.aesCore.engine._zz_38_ [6] \myMem_1_.aesCore.engine._zz_53_ [6] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [7] \myMem_1_.aesCore.engine._zz_38_ [7] \myMem_1_.aesCore.engine._zz_53_ [7] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [8] \myMem_1_.aesCore.engine._zz_38_ [8] \myMem_1_.aesCore.engine._zz_53_ [8] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [9] \myMem_1_.aesCore.engine._zz_38_ [9] \myMem_1_.aesCore.engine._zz_53_ [9] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [10] \myMem_1_.aesCore.engine._zz_38_ [10] \myMem_1_.aesCore.engine._zz_53_ [10] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [11] \myMem_1_.aesCore.engine._zz_38_ [11] \myMem_1_.aesCore.engine._zz_53_ [11] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [12] \myMem_1_.aesCore.engine._zz_38_ [12] \myMem_1_.aesCore.engine._zz_53_ [12] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [13] \myMem_1_.aesCore.engine._zz_38_ [13] \myMem_1_.aesCore.engine._zz_53_ [13] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [14] \myMem_1_.aesCore.engine._zz_38_ [14] \myMem_1_.aesCore.engine._zz_53_ [14] } = 6'101000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [15] \myMem_1_.aesCore.engine._zz_38_ [15] \myMem_1_.aesCore.engine._zz_53_ [15] } = 6'101000
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Size of SAT problem: 6 cells, 223 variables, 588 clauses
|
|
According to the SAT solver this pair of cells can be shared.
|
|
Activation signal for $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577: $auto$share.cc:976:make_cell_activation_logic$6976
|
|
New cell: $auto$share.cc:666:make_supercell$6983 ($sshl)
|
|
Analyzing resource sharing options for $auto$share.cc:666:make_supercell$6983 ($sshl):
|
|
Found 18 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ }.
|
|
Found 3 candidates: $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571
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Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 ($sshl):
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Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
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Forbidden control signals for this pair of cells: \myMem_1_.aesCore.engine._zz_38_
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [0] \myMem_1_.aesCore.engine._zz_53_ [0] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid } = 3'100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [1] \myMem_1_.aesCore.engine._zz_53_ [1] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [2] \myMem_1_.aesCore.engine._zz_53_ [2] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [3] \myMem_1_.aesCore.engine._zz_53_ [3] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [4] \myMem_1_.aesCore.engine._zz_53_ [4] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [5] \myMem_1_.aesCore.engine._zz_53_ [5] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [6] \myMem_1_.aesCore.engine._zz_53_ [6] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [7] \myMem_1_.aesCore.engine._zz_53_ [7] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [8] \myMem_1_.aesCore.engine._zz_53_ [8] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [9] \myMem_1_.aesCore.engine._zz_53_ [9] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [10] \myMem_1_.aesCore.engine._zz_53_ [10] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [11] \myMem_1_.aesCore.engine._zz_53_ [11] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [12] \myMem_1_.aesCore.engine._zz_53_ [12] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [13] \myMem_1_.aesCore.engine._zz_53_ [13] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [14] \myMem_1_.aesCore.engine._zz_53_ [14] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [15] \myMem_1_.aesCore.engine._zz_53_ [15] } = 5'10100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [0] \myMem_1_.aesCore.engine._zz_68_ [0] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [1] \myMem_1_.aesCore.engine._zz_68_ [1] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [2] \myMem_1_.aesCore.engine._zz_68_ [2] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [3] \myMem_1_.aesCore.engine._zz_68_ [3] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [4] \myMem_1_.aesCore.engine._zz_68_ [4] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [5] \myMem_1_.aesCore.engine._zz_68_ [5] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [6] \myMem_1_.aesCore.engine._zz_68_ [6] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [7] \myMem_1_.aesCore.engine._zz_68_ [7] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [8] \myMem_1_.aesCore.engine._zz_68_ [8] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [9] \myMem_1_.aesCore.engine._zz_68_ [9] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [10] \myMem_1_.aesCore.engine._zz_68_ [10] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [11] \myMem_1_.aesCore.engine._zz_68_ [11] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [12] \myMem_1_.aesCore.engine._zz_68_ [12] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [13] \myMem_1_.aesCore.engine._zz_68_ [13] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [14] \myMem_1_.aesCore.engine._zz_68_ [14] } = 3'100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [15] \myMem_1_.aesCore.engine._zz_68_ [15] } = 3'100
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Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
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Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP
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Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
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Size of SAT problem: 6 cells, 310 variables, 929 clauses
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According to the SAT solver this pair of cells can not be shared.
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Model from SAT solver: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ } = 51'001000000000000000001111011111111100000000000000001
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Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 ($sshl):
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Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
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Forbidden control signals for this pair of cells: \myMem_1_.aesCore.engine._zz_23_
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [0] \myMem_1_.aesCore.engine._zz_53_ [0] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid } = 3'100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [1] \myMem_1_.aesCore.engine._zz_53_ [1] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [2] \myMem_1_.aesCore.engine._zz_53_ [2] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [3] \myMem_1_.aesCore.engine._zz_53_ [3] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [4] \myMem_1_.aesCore.engine._zz_53_ [4] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [5] \myMem_1_.aesCore.engine._zz_53_ [5] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [6] \myMem_1_.aesCore.engine._zz_53_ [6] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [7] \myMem_1_.aesCore.engine._zz_53_ [7] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [8] \myMem_1_.aesCore.engine._zz_53_ [8] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [9] \myMem_1_.aesCore.engine._zz_53_ [9] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [10] \myMem_1_.aesCore.engine._zz_53_ [10] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [11] \myMem_1_.aesCore.engine._zz_53_ [11] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [12] \myMem_1_.aesCore.engine._zz_53_ [12] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [13] \myMem_1_.aesCore.engine._zz_53_ [13] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [14] \myMem_1_.aesCore.engine._zz_53_ [14] } = 5'10100
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Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [15] \myMem_1_.aesCore.engine._zz_53_ [15] } = 5'10100
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [0] \myMem_1_.aesCore.engine._zz_53_ [0] \myMem_1_.aesCore.engine._zz_68_ [0] } = 4'1000
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [1] \myMem_1_.aesCore.engine._zz_53_ [1] \myMem_1_.aesCore.engine._zz_68_ [1] } = 4'1000
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [2] \myMem_1_.aesCore.engine._zz_53_ [2] \myMem_1_.aesCore.engine._zz_68_ [2] } = 4'1000
|
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [3] \myMem_1_.aesCore.engine._zz_53_ [3] \myMem_1_.aesCore.engine._zz_68_ [3] } = 4'1000
|
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [4] \myMem_1_.aesCore.engine._zz_53_ [4] \myMem_1_.aesCore.engine._zz_68_ [4] } = 4'1000
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [5] \myMem_1_.aesCore.engine._zz_53_ [5] \myMem_1_.aesCore.engine._zz_68_ [5] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [6] \myMem_1_.aesCore.engine._zz_53_ [6] \myMem_1_.aesCore.engine._zz_68_ [6] } = 4'1000
|
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Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [7] \myMem_1_.aesCore.engine._zz_53_ [7] \myMem_1_.aesCore.engine._zz_68_ [7] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [8] \myMem_1_.aesCore.engine._zz_53_ [8] \myMem_1_.aesCore.engine._zz_68_ [8] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [9] \myMem_1_.aesCore.engine._zz_53_ [9] \myMem_1_.aesCore.engine._zz_68_ [9] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [10] \myMem_1_.aesCore.engine._zz_53_ [10] \myMem_1_.aesCore.engine._zz_68_ [10] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [11] \myMem_1_.aesCore.engine._zz_53_ [11] \myMem_1_.aesCore.engine._zz_68_ [11] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [12] \myMem_1_.aesCore.engine._zz_53_ [12] \myMem_1_.aesCore.engine._zz_68_ [12] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [13] \myMem_1_.aesCore.engine._zz_53_ [13] \myMem_1_.aesCore.engine._zz_68_ [13] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [14] \myMem_1_.aesCore.engine._zz_53_ [14] \myMem_1_.aesCore.engine._zz_68_ [14] } = 4'1000
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [15] \myMem_1_.aesCore.engine._zz_53_ [15] \myMem_1_.aesCore.engine._zz_68_ [15] } = 4'1000
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Size of SAT problem: 6 cells, 326 variables, 993 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ } = 51'001000000000000000111111111011111100000000000000000
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: \myMem_1_.aesCore.engine._zz_53_
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid = 1'1
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [0] \myMem_1_.aesCore.engine._zz_38_ [0] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid } = 3'100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [1] \myMem_1_.aesCore.engine._zz_38_ [1] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [2] \myMem_1_.aesCore.engine._zz_38_ [2] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [3] \myMem_1_.aesCore.engine._zz_38_ [3] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [4] \myMem_1_.aesCore.engine._zz_38_ [4] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [5] \myMem_1_.aesCore.engine._zz_38_ [5] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [6] \myMem_1_.aesCore.engine._zz_38_ [6] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [7] \myMem_1_.aesCore.engine._zz_38_ [7] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [8] \myMem_1_.aesCore.engine._zz_38_ [8] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [9] \myMem_1_.aesCore.engine._zz_38_ [9] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [10] \myMem_1_.aesCore.engine._zz_38_ [10] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [11] \myMem_1_.aesCore.engine._zz_38_ [11] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [12] \myMem_1_.aesCore.engine._zz_38_ [12] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [13] \myMem_1_.aesCore.engine._zz_38_ [13] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [14] \myMem_1_.aesCore.engine._zz_38_ [14] } = 5'10100
|
|
Activation pattern for cell $auto$share.cc:666:make_supercell$6983: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ [15] \myMem_1_.aesCore.engine._zz_38_ [15] } = 5'10100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [0] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [1] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [2] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [3] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [4] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [5] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [6] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [7] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [8] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [9] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [10] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [11] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [12] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [13] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [14] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [15] } = 2'10
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4979_CMP
|
|
Adding exclusive control bits: $flatten\myMem_1_.\aesCore.\engine.$procmux$4995_CMP vs. $flatten\myMem_1_.\aesCore.\engine.$procmux$4282_CMP
|
|
Size of SAT problem: 6 cells, 295 variables, 868 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_68_ } = 51'001000000000000000000000000000000000000000000000000
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Found 2 candidates: $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [0] \myMem_1_.aesCore.engine._zz_68_ [0] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [1] \myMem_1_.aesCore.engine._zz_68_ [1] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [2] \myMem_1_.aesCore.engine._zz_68_ [2] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [3] \myMem_1_.aesCore.engine._zz_68_ [3] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [4] \myMem_1_.aesCore.engine._zz_68_ [4] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [5] \myMem_1_.aesCore.engine._zz_68_ [5] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [6] \myMem_1_.aesCore.engine._zz_68_ [6] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [7] \myMem_1_.aesCore.engine._zz_68_ [7] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [8] \myMem_1_.aesCore.engine._zz_68_ [8] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [9] \myMem_1_.aesCore.engine._zz_68_ [9] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [10] \myMem_1_.aesCore.engine._zz_68_ [10] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [11] \myMem_1_.aesCore.engine._zz_68_ [11] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [12] \myMem_1_.aesCore.engine._zz_68_ [12] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [13] \myMem_1_.aesCore.engine._zz_68_ [13] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [14] \myMem_1_.aesCore.engine._zz_68_ [14] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [15] \myMem_1_.aesCore.engine._zz_68_ [15] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [0] \myMem_1_.aesCore.engine._zz_68_ [0] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [1] \myMem_1_.aesCore.engine._zz_68_ [1] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [2] \myMem_1_.aesCore.engine._zz_68_ [2] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [3] \myMem_1_.aesCore.engine._zz_68_ [3] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [4] \myMem_1_.aesCore.engine._zz_68_ [4] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [5] \myMem_1_.aesCore.engine._zz_68_ [5] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [6] \myMem_1_.aesCore.engine._zz_68_ [6] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [7] \myMem_1_.aesCore.engine._zz_68_ [7] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [8] \myMem_1_.aesCore.engine._zz_68_ [8] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [9] \myMem_1_.aesCore.engine._zz_68_ [9] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [10] \myMem_1_.aesCore.engine._zz_68_ [10] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [11] \myMem_1_.aesCore.engine._zz_68_ [11] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [12] \myMem_1_.aesCore.engine._zz_68_ [12] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [13] \myMem_1_.aesCore.engine._zz_68_ [13] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [14] \myMem_1_.aesCore.engine._zz_68_ [14] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ [15] \myMem_1_.aesCore.engine._zz_68_ [15] } = 3'100
|
|
Size of SAT problem: 2 cells, 137 variables, 330 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ } = 33'100000000000000010110111111111110
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [0] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [1] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [2] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [3] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [4] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [5] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [6] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [7] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [8] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [9] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [10] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [11] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [12] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [13] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [14] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3805$566: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [15] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [0] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [1] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [2] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [3] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [4] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [5] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [6] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [7] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [8] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [9] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [10] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [11] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [12] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [13] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [14] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [15] } = 2'10
|
|
Size of SAT problem: 2 cells, 89 variables, 218 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ } = 17'10000000000000000
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Found 1 candidates: $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571
|
|
Analyzing resource sharing with $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ }.
|
|
Forbidden control signals for this pair of cells: { \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_53_ }
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [0] \myMem_1_.aesCore.engine._zz_68_ [0] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [1] \myMem_1_.aesCore.engine._zz_68_ [1] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [2] \myMem_1_.aesCore.engine._zz_68_ [2] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [3] \myMem_1_.aesCore.engine._zz_68_ [3] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [4] \myMem_1_.aesCore.engine._zz_68_ [4] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [5] \myMem_1_.aesCore.engine._zz_68_ [5] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [6] \myMem_1_.aesCore.engine._zz_68_ [6] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [7] \myMem_1_.aesCore.engine._zz_68_ [7] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [8] \myMem_1_.aesCore.engine._zz_68_ [8] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [9] \myMem_1_.aesCore.engine._zz_68_ [9] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [10] \myMem_1_.aesCore.engine._zz_68_ [10] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [11] \myMem_1_.aesCore.engine._zz_68_ [11] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [12] \myMem_1_.aesCore.engine._zz_68_ [12] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [13] \myMem_1_.aesCore.engine._zz_68_ [13] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [14] \myMem_1_.aesCore.engine._zz_68_ [14] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3790$562: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ [15] \myMem_1_.aesCore.engine._zz_68_ [15] } = 3'100
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [0] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [1] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [2] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [3] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [4] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [5] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [6] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [7] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [8] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [9] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [10] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [11] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [12] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [13] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [14] } = 2'10
|
|
Activation pattern for cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ [15] } = 2'10
|
|
Size of SAT problem: 2 cells, 220 variables, 624 clauses
|
|
According to the SAT solver this pair of cells can not be shared.
|
|
Model from SAT solver: { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_68_ } = 33'100000000000000011011111111111110
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3820$571 ($sshl):
|
|
Found 16 activation_patterns using ctrl signal { \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_68_ }.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$memrd$\sBoxMemInv$PQVexRiscvUlx3s.v:1805$512 ($memrd):
|
|
Found 32 activation_patterns using ctrl signal { \myMem_1_._zz_3_ \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_2_ \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $flatten\myMem_1_.\aesCore.\engine.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:1801$511 ($memrd):
|
|
Found 32 activation_patterns using ctrl signal { \myMem_1_._zz_3_ \myMem_1_.aesCore.engine.sm_byteSub_cmd_valid \myMem_1_.aesCore.engine.sm_shiftRow_cmd \myMem_1_.aesCore.engine.sm_mixCol_cmd_valid \myMem_1_.aesCore.engine._zz_2_ \myMem_1_.aesCore.engine._zz_23_ \myMem_1_.aesCore.engine._zz_38_ \myMem_1_.aesCore.engine._zz_53_ \myMem_1_.aesCore.engine._zz_68_ }.
|
|
No candidates found.
|
|
Removing 2 cells in module PQVexRiscvUlx3s:
|
|
Removing cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3768$560 ($sshl).
|
|
Removing cell $flatten\myMem_1_.\aesCore.\engine.$sshl$PQVexRiscvUlx3s.v:3835$577 ($sshl).
|
|
|
|
2.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 4 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.21. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.21.3. Continuing TECHMAP pass.
|
|
Using template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\_80_mul for cells of type $mul.
|
|
Using template $paramod\$__MUL18X18\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=32\A_SIGNED=0\B_SIGNED=0 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~98 debug messages>
|
|
|
|
2.22. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module PQVexRiscvUlx3s:
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:10449$1644 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5212$738 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:510$56 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:573$66 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:567$65 ($sub).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:224$10 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:320$24 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759 ($add).
|
|
creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6847$902 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6874$912 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6886$915 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6887$916 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6897$920 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6898$922 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6899$924 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8907$1325 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8920$1328 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8974$1340 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9486$1477 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9488$1478 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485 ($add).
|
|
creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9535$1488 ($add).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8233$1186 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8983$1341 ($sub).
|
|
creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:9318$1449 ($sub).
|
|
creating $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:11321$1790 ($add).
|
|
creating $macc model for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:11397$1831 ($sub).
|
|
creating $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:11459$1834 ($add).
|
|
creating $macc model for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:11519$1868 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5461$782 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5753$845 ($sub).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820 ($add).
|
|
creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1396$91 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1397$92 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1398$93 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3595$546 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3760$559 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:4681$656 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\engine.$sub$PQVexRiscvUlx3s.v:4694$659 ($sub).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\keySchedule.$add$PQVexRiscvUlx3s.v:4878$698 ($add).
|
|
creating $macc model for $flatten\myMem_1_.\aesCore.\keySchedule.$sub$PQVexRiscvUlx3s.v:4771$681 ($sub).
|
|
creating $macc model for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:10228$1628 ($add).
|
|
merging $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:11459$1834 into $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:11519$1868.
|
|
merging $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:11321$1790 into $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:11397$1831.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6874$912 into $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8233$1186.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6898$922 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6897$920.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6899$924 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6897$920.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6887$916 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6886$915.
|
|
merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8920$1328 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6847$902.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1398$93.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1397$92.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1396$91.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5753$845.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820.
|
|
creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5461$782.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3595$546.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3760$559.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:9318$1449.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8983$1341.
|
|
creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9535$1488.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9488$1478.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9486$1477.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8974$1340.
|
|
creating $alu model for $macc $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:10228$1628.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8907$1325.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154.
|
|
creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\keySchedule.$add$PQVexRiscvUlx3s.v:4878$698.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$sub$PQVexRiscvUlx3s.v:4694$659.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\keySchedule.$sub$PQVexRiscvUlx3s.v:4771$681.
|
|
creating $alu model for $macc $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:4681$656.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:320$24.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:224$10.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:567$65.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:573$66.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:510$56.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5212$738.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753.
|
|
creating $alu model for $macc $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:10449$1644.
|
|
creating $macc cell for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:11397$1831: $auto$alumacc.cc:365:replace_macc$6994
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6886$915: $auto$alumacc.cc:365:replace_macc$6995
|
|
creating $macc cell for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:11519$1868: $auto$alumacc.cc:365:replace_macc$6996
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6897$920: $auto$alumacc.cc:365:replace_macc$6997
|
|
creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6847$902: $auto$alumacc.cc:365:replace_macc$6998
|
|
creating $macc cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8233$1186: $auto$alumacc.cc:365:replace_macc$6999
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:5336$760 ($eq): merged with $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772.
|
|
creating $alu model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:5336$760 ($eq): merged with $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772.
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:10449$1644: $auto$alumacc.cc:485:replace_alu$7000
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753: $auto$alumacc.cc:485:replace_alu$7003
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759: $auto$alumacc.cc:485:replace_alu$7006
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772, $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:5336$760: $auto$alumacc.cc:485:replace_alu$7009
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:5212$738: $auto$alumacc.cc:485:replace_alu$7014
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:510$56: $auto$alumacc.cc:485:replace_alu$7017
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:573$66: $auto$alumacc.cc:485:replace_alu$7020
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:567$65: $auto$alumacc.cc:485:replace_alu$7023
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:224$10: $auto$alumacc.cc:485:replace_alu$7026
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:320$24: $auto$alumacc.cc:485:replace_alu$7029
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5307$753: $auto$alumacc.cc:485:replace_alu$7032
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:5330$759: $auto$alumacc.cc:485:replace_alu$7035
|
|
creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:5344$772, $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:5336$760: $auto$alumacc.cc:485:replace_alu$7038
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:4681$656: $auto$alumacc.cc:485:replace_alu$7043
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\keySchedule.$sub$PQVexRiscvUlx3s.v:4771$681: $auto$alumacc.cc:485:replace_alu$7046
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$sub$PQVexRiscvUlx3s.v:4694$659: $auto$alumacc.cc:485:replace_alu$7049
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\keySchedule.$add$PQVexRiscvUlx3s.v:4878$698: $auto$alumacc.cc:485:replace_alu$7052
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:6908$928: $auto$alumacc.cc:485:replace_alu$7055
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154: $auto$alumacc.cc:485:replace_alu$7058
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8907$1325: $auto$alumacc.cc:485:replace_alu$7061
|
|
creating $alu cell for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:10228$1628: $auto$alumacc.cc:485:replace_alu$7064
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8974$1340: $auto$alumacc.cc:485:replace_alu$7067
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9486$1477: $auto$alumacc.cc:485:replace_alu$7070
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9488$1478: $auto$alumacc.cc:485:replace_alu$7073
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9534$1485: $auto$alumacc.cc:485:replace_alu$7076
|
|
creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:9535$1488: $auto$alumacc.cc:485:replace_alu$7079
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:6871$911: $auto$alumacc.cc:485:replace_alu$7082
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:8983$1341: $auto$alumacc.cc:485:replace_alu$7085
|
|
creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:9318$1449: $auto$alumacc.cc:485:replace_alu$7088
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3760$559: $auto$alumacc.cc:485:replace_alu$7091
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:3595$546: $auto$alumacc.cc:485:replace_alu$7094
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5461$782: $auto$alumacc.cc:485:replace_alu$7097
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820: $auto$alumacc.cc:485:replace_alu$7100
|
|
creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826: $auto$alumacc.cc:485:replace_alu$7103
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:5753$845: $auto$alumacc.cc:485:replace_alu$7106
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5645$820: $auto$alumacc.cc:485:replace_alu$7109
|
|
creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:5672$826: $auto$alumacc.cc:485:replace_alu$7112
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1396$91: $auto$alumacc.cc:485:replace_alu$7115
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1397$92: $auto$alumacc.cc:485:replace_alu$7118
|
|
creating $alu cell for $flatten\myMem_1_.\aesCore.\engine.$add$PQVexRiscvUlx3s.v:1398$93: $auto$alumacc.cc:485:replace_alu$7121
|
|
created 40 $alu and 6 $macc cells.
|
|
|
|
2.23. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.23.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~24 debug messages>
|
|
Removed a total of 8 cells.
|
|
|
|
2.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~317 debug messages>
|
|
|
|
2.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
2.23.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$6086 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11243$1753_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$6083 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11240$1752_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$6080 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11237$1751_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$6077 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11234$1750_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$6103 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:11175$1713_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$6100 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:11172$1712_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$6097 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:11169$1711_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$6094 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:11166$1710_DATA, rval = 8'00000000).
|
|
Adding SRST signal on $auto$opt_dff.cc:764:run$6708 ($dffe) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_readArea_shifter [2], Q = \jtagBridge_1_.jtag_readArea_shifter [1], rval = 1'0).
|
|
|
|
2.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 9 unused cells and 75 unused wires.
|
|
<suppressed ~38 debug messages>
|
|
|
|
2.23.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~311 debug messages>
|
|
|
|
2.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.23.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.23.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.23.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.23.16. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.24. Executing MEMORY pass.
|
|
|
|
2.24.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.24.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$779' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$779' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:0$1585' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1746' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1747' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1748' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1749' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$842' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1786' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1787' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1788' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1789' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$842' in module `\PQVexRiscvUlx3s': merged $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:5273$742' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:5273$742' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7057$1050' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:7063$1052' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:11157$1716' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:11158$1717' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:11159$1718' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:11160$1719' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:5611$809' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:11225$1756' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:11226$1757' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:11227$1758' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:11228$1759' in module `\PQVexRiscvUlx3s': merged data $dff to cell.
|
|
Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:5611$809' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\engine.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:1801$511' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\engine.$memrd$\sBoxMemInv$PQVexRiscvUlx3s.v:1805$512' in module `\PQVexRiscvUlx3s': no (compatible) $dff found.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\rconMem$PQVexRiscvUlx3s.v:4775$682' in module `\PQVexRiscvUlx3s': merged address $dff to cell.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4779$683' in module `\PQVexRiscvUlx3s': merged address $dff to cell.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4780$684' in module `\PQVexRiscvUlx3s': merged address $dff to cell.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4781$685' in module `\PQVexRiscvUlx3s': merged address $dff to cell.
|
|
Checking cell `$flatten\myMem_1_.\aesCore.\keySchedule.$memrd$\sBoxMem$PQVexRiscvUlx3s.v:4782$686' in module `\PQVexRiscvUlx3s': merged address $dff to cell.
|
|
|
|
2.24.3. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 43 unused cells and 55 unused wires.
|
|
<suppressed ~44 debug messages>
|
|
|
|
2.24.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.24.6. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.25. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol0:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol0.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol0.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol0.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol0.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol0.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol0.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol0.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol0.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol0.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol0.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol0.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol0.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol0.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol0.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol0.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol0.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol0.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol0.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol0.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol0.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol0.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol0.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol0.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol0.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol0.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol1:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol1.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol1.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol1.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol1.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol1.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol1.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol1.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol1.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol1.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol1.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol1.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol1.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol1.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol1.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol1.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol1.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol1.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol1.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol1.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol1.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol1.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol1.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol1.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol1.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol1.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol2:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol2.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol2.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol2.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol2.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol2.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol2.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol2.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol2.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol2.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol2.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol2.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol2.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol2.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol2.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol2.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol2.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol2.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol2.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol2.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol2.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol2.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol2.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol2.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol2.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol2.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol3:
|
|
Properties: ports=2 bits=524288 rports=1 wports=1 dbits=8 abits=16 words=65536
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=32, acells=4
|
|
Efficiency for rule 4.4: efficiency=100, cells=32, acells=8
|
|
Efficiency for rule 4.3: efficiency=100, cells=32, acells=16
|
|
Efficiency for rule 4.2: efficiency=88, cells=32, acells=32
|
|
Efficiency for rule 4.1: efficiency=44, cells=64, acells=64
|
|
Efficiency for rule 1.1: efficiency=22, cells=128, acells=128
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_0.ram_symbol3.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 2 0>: memory_ramBlocks_0.ram_symbol3.0.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 3 0>: memory_ramBlocks_0.ram_symbol3.0.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_0.ram_symbol3.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 2 0>: memory_ramBlocks_0.ram_symbol3.1.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 3 0>: memory_ramBlocks_0.ram_symbol3.1.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_0.ram_symbol3.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 2 0>: memory_ramBlocks_0.ram_symbol3.2.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 3 0>: memory_ramBlocks_0.ram_symbol3.2.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_0.ram_symbol3.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 2 0>: memory_ramBlocks_0.ram_symbol3.3.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 3 0>: memory_ramBlocks_0.ram_symbol3.3.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_0.ram_symbol3.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 2 0>: memory_ramBlocks_0.ram_symbol3.4.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 3 0>: memory_ramBlocks_0.ram_symbol3.4.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_0.ram_symbol3.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 2 0>: memory_ramBlocks_0.ram_symbol3.5.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 3 0>: memory_ramBlocks_0.ram_symbol3.5.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_0.ram_symbol3.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 2 0>: memory_ramBlocks_0.ram_symbol3.6.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 3 0>: memory_ramBlocks_0.ram_symbol3.6.3.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol3.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_0.ram_symbol3.7.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 2 0>: memory_ramBlocks_0.ram_symbol3.7.2.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 3 0>: memory_ramBlocks_0.ram_symbol3.7.3.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol0:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol0.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol0.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol0.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol0.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol0.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol0.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol0.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol0.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol0.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol0.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol0.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol0.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol0.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol0.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol0.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol0.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol1:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol1.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol1.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol1.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol1.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol1.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol1.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol1.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol1.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol1.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol1.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol1.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol1.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol1.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol1.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol1.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol1.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol2:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol2.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol2.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol2.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol2.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol2.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol2.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol2.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol2.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol2.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol2.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol2.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol2.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol2.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol2.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol2.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol2.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol3:
|
|
Properties: ports=2 bits=262144 rports=1 wports=1 dbits=8 abits=15 words=32768
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Shuffle bit order to accommodate enable buckets of size 9..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Shuffle bit order to accommodate enable buckets of size 4..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Shuffle bit order to accommodate enable buckets of size 2..
|
|
Results of bit order shuffling: 0 1 2 3 4 5 6 7
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=100, cells=16, acells=2
|
|
Efficiency for rule 4.4: efficiency=100, cells=16, acells=4
|
|
Efficiency for rule 4.3: efficiency=100, cells=16, acells=8
|
|
Efficiency for rule 4.2: efficiency=88, cells=16, acells=16
|
|
Efficiency for rule 4.1: efficiency=44, cells=32, acells=32
|
|
Efficiency for rule 1.1: efficiency=22, cells=64, acells=64
|
|
Selected rule 4.5 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol3.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <0 1 0>: memory_ramBlocks_1.ram_symbol3.0.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol3.1.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 1 0>: memory_ramBlocks_1.ram_symbol3.1.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol3.2.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <2 1 0>: memory_ramBlocks_1.ram_symbol3.2.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol3.3.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <3 1 0>: memory_ramBlocks_1.ram_symbol3.3.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol3.4.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <4 1 0>: memory_ramBlocks_1.ram_symbol3.4.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol3.5.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <5 1 0>: memory_ramBlocks_1.ram_symbol3.5.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol3.6.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <6 1 0>: memory_ramBlocks_1.ram_symbol3.6.1.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol3.7.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <7 1 0>: memory_ramBlocks_1.ram_symbol3.7.1.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0
|
|
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.engine.sBoxMem:
|
|
Properties: ports=1 bits=2048 rports=1 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=256 dwaste=28 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_PDPW16KD failed.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=768 dwaste=10 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1792 dwaste=1 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=3840 dwaste=0 bwaste=15360 waste=15360 efficiency=6
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.engine.sBoxMemInv:
|
|
Properties: ports=1 bits=2048 rports=1 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=256 dwaste=28 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_PDPW16KD failed.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=768 dwaste=10 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1792 dwaste=1 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=3840 dwaste=0 bwaste=15360 waste=15360 efficiency=6
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Read port #0 is in clock domain !~async~.
|
|
Bram port B1.1 has incompatible clock type.
|
|
Failed to map read port #0.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.rconMem:
|
|
Properties: ports=1 bits=88 rports=1 wports=0 dbits=8 abits=4 words=11
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=501 dwaste=28 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=501 dwaste=28 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #2 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=501 dwaste=28 bwaste=18344 waste=18344 efficiency=0
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1013 dwaste=10 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2037 dwaste=1 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4085 dwaste=0 bwaste=16340 waste=16340 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8181 dwaste=0 bwaste=16362 waste=16362 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16373 dwaste=0 bwaste=16373 waste=16373 efficiency=0
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1013 dwaste=10 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2037 dwaste=1 bwaste=18344 waste=18344 efficiency=0
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4085 dwaste=0 bwaste=16340 waste=16340 efficiency=0
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8181 dwaste=0 bwaste=16362 waste=16362 efficiency=0
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16373 dwaste=0 bwaste=16373 waste=16373 efficiency=0
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1013 dwaste=10 bwaste=18344 waste=18344 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=2037 dwaste=1 bwaste=18344 waste=18344 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4085 dwaste=0 bwaste=16340 waste=16340 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=8181 dwaste=0 bwaste=16362 waste=16362 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16373 dwaste=0 bwaste=16373 waste=16373 efficiency=0
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem:
|
|
Properties: ports=4 bits=2048 rports=4 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=256 dwaste=28 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Failed to map read port #2.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Failed to map read port #3.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.4.
|
|
Updated properties: dups=4 waste=65536 efficiency=2
|
|
Rule for bram type $__ECP5_PDPW16KD rejected: requirement 'min efficiency 5' not met.
|
|
Mapping to bram type $__ECP5_PDPW16KD failed.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=768 dwaste=10 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Failed to map read port #2.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Failed to map read port #3.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.4.
|
|
Updated properties: dups=4 waste=65536 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD rejected: requirement 'min efficiency 5' not met.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=1792 dwaste=1 bwaste=16384 waste=16384 efficiency=11
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Failed to map read port #2.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Failed to map read port #3.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.4.
|
|
Updated properties: dups=4 waste=65536 efficiency=2
|
|
Rule for bram type $__ECP5_DP16KD rejected: requirement 'min efficiency 5' not met.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=3840 dwaste=0 bwaste=15360 waste=15360 efficiency=6
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Failed to map read port #2.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Failed to map read port #3.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.2.
|
|
Read port #2 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.3.
|
|
Read port #3 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.4.
|
|
Updated properties: dups=4 waste=61440 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD rejected: requirement 'min efficiency 5' not met.
|
|
Mapping to bram type $__ECP5_DP16KD failed.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=7936 dwaste=0 bwaste=15872 waste=15872 efficiency=3
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=16128 dwaste=0 bwaste=16128 waste=16128 efficiency=1
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
No acceptable bram resources found.
|
|
|
|
2.27. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
|
|
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.27.2. Continuing TECHMAP pass.
|
|
Using template $paramod$38262e435a9f54db3b5bdc33b5e39b1fffa1b883\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
No more expansions possible.
|
|
<suppressed ~217 debug messages>
|
|
|
|
2.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram:
|
|
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.1.0.0
|
|
Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile:
|
|
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Failed to map read port #1.
|
|
Growing more read ports by duplicating bram cells.
|
|
Read port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.1.
|
|
Read port #1 is in clock domain \io_mainClock.
|
|
Mapped to bram port A1.2.
|
|
Updated properties: dups=2 waste=0 efficiency=50
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: core_cpu.RegFilePlugin_regFile.0.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: core_cpu.RegFilePlugin_regFile.0.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: core_cpu.RegFilePlugin_regFile.0.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: core_cpu.RegFilePlugin_regFile.0.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: core_cpu.RegFilePlugin_regFile.1.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: core_cpu.RegFilePlugin_regFile.1.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: core_cpu.RegFilePlugin_regFile.1.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: core_cpu.RegFilePlugin_regFile.1.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: core_cpu.RegFilePlugin_regFile.2.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: core_cpu.RegFilePlugin_regFile.2.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: core_cpu.RegFilePlugin_regFile.2.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: core_cpu.RegFilePlugin_regFile.2.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: core_cpu.RegFilePlugin_regFile.3.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: core_cpu.RegFilePlugin_regFile.3.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: core_cpu.RegFilePlugin_regFile.3.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: core_cpu.RegFilePlugin_regFile.3.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: core_cpu.RegFilePlugin_regFile.4.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: core_cpu.RegFilePlugin_regFile.4.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: core_cpu.RegFilePlugin_regFile.4.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: core_cpu.RegFilePlugin_regFile.4.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: core_cpu.RegFilePlugin_regFile.5.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: core_cpu.RegFilePlugin_regFile.5.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: core_cpu.RegFilePlugin_regFile.5.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: core_cpu.RegFilePlugin_regFile.5.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: core_cpu.RegFilePlugin_regFile.6.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: core_cpu.RegFilePlugin_regFile.6.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: core_cpu.RegFilePlugin_regFile.6.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: core_cpu.RegFilePlugin_regFile.6.1.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: core_cpu.RegFilePlugin_regFile.7.0.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: core_cpu.RegFilePlugin_regFile.7.0.1
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: core_cpu.RegFilePlugin_regFile.7.1.0
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: core_cpu.RegFilePlugin_regFile.7.1.1
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram:
|
|
Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
|
|
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Write port #0 is in clock domain \io_mainClock.
|
|
Mapped to bram port B1.
|
|
Read port #0 is in clock domain !~async~.
|
|
Mapped to bram port A1.1.
|
|
Updated properties: dups=1 waste=50 efficiency=21
|
|
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.engine.sBoxMem:
|
|
Properties: ports=1 bits=2048 rports=1 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) rejected: requirement 'min wports 1' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.engine.sBoxMemInv:
|
|
Properties: ports=1 bits=2048 rports=1 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) rejected: requirement 'min wports 1' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.rconMem:
|
|
Properties: ports=1 bits=88 rports=1 wports=0 dbits=8 abits=4 words=11
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=5 dwaste=0 bwaste=20 waste=20 efficiency=68
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) rejected: requirement 'min wports 1' not met.
|
|
No acceptable bram resources found.
|
|
Processing PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem:
|
|
Properties: ports=4 bits=2048 rports=4 wports=0 dbits=8 abits=8 words=256
|
|
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
|
|
Bram geometry: abits=4 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) rejected: requirement 'min wports 1' not met.
|
|
No acceptable bram resources found.
|
|
|
|
2.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.29.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~52 debug messages>
|
|
|
|
2.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~1182 debug messages>
|
|
|
|
2.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~2280 debug messages>
|
|
Removed a total of 760 cells.
|
|
|
|
2.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9400 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9393, Q = $auto$memory_bram.cc:1009:replace_memory$9397).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9434 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9427, Q = $auto$memory_bram.cc:1009:replace_memory$9431).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9754 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9747, Q = $auto$memory_bram.cc:1009:replace_memory$9751).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8916 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8909, Q = $auto$memory_bram.cc:1009:replace_memory$8913).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9832 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9825, Q = $auto$memory_bram.cc:1009:replace_memory$9829).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8929 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8922, Q = $auto$memory_bram.cc:1009:replace_memory$8926).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9676 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9669, Q = $auto$memory_bram.cc:1009:replace_memory$9673).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8466 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8459, Q = $auto$memory_bram.cc:1009:replace_memory$8463).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8942 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8935, Q = $auto$memory_bram.cc:1009:replace_memory$8939).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7293 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7286, Q = $auto$memory_bram.cc:1009:replace_memory$7290).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8479 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8472, Q = $auto$memory_bram.cc:1009:replace_memory$8476).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7306 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7299, Q = $auto$memory_bram.cc:1009:replace_memory$7303).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8955 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8948, Q = $auto$memory_bram.cc:1009:replace_memory$8952).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9603 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9596, Q = $auto$memory_bram.cc:1009:replace_memory$9600).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9447 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9440, Q = $auto$memory_bram.cc:1009:replace_memory$9444).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7319 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7312, Q = $auto$memory_bram.cc:1009:replace_memory$7316).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9296 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9289, Q = $auto$memory_bram.cc:1009:replace_memory$9293).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8812 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8805, Q = $auto$memory_bram.cc:1009:replace_memory$8809).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7332 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7325, Q = $auto$memory_bram.cc:1009:replace_memory$7329).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8492 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8485, Q = $auto$memory_bram.cc:1009:replace_memory$8489).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8968 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8961, Q = $auto$memory_bram.cc:1009:replace_memory$8965).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7345 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7338, Q = $auto$memory_bram.cc:1009:replace_memory$7342).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7358 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7351, Q = $auto$memory_bram.cc:1009:replace_memory$7355).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7371 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7364, Q = $auto$memory_bram.cc:1009:replace_memory$7368).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8505 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8498, Q = $auto$memory_bram.cc:1009:replace_memory$8502).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7384 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7377, Q = $auto$memory_bram.cc:1009:replace_memory$7381).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7397 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7390, Q = $auto$memory_bram.cc:1009:replace_memory$7394).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7410 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7403, Q = $auto$memory_bram.cc:1009:replace_memory$7407).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8989 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8982, Q = $auto$memory_bram.cc:1009:replace_memory$8986).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7423 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7416, Q = $auto$memory_bram.cc:1009:replace_memory$7420).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8518 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8511, Q = $auto$memory_bram.cc:1009:replace_memory$8515).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9309 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9302, Q = $auto$memory_bram.cc:1009:replace_memory$9306).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7436 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7429, Q = $auto$memory_bram.cc:1009:replace_memory$7433).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7449 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7442, Q = $auto$memory_bram.cc:1009:replace_memory$7446).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9460 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9453, Q = $auto$memory_bram.cc:1009:replace_memory$9457).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7462 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7455, Q = $auto$memory_bram.cc:1009:replace_memory$7459).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9002 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8995, Q = $auto$memory_bram.cc:1009:replace_memory$8999).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8531 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8524, Q = $auto$memory_bram.cc:1009:replace_memory$8528).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7475 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7468, Q = $auto$memory_bram.cc:1009:replace_memory$7472).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7488 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7481, Q = $auto$memory_bram.cc:1009:replace_memory$7485).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9689 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9682, Q = $auto$memory_bram.cc:1009:replace_memory$9686).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9616 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9609, Q = $auto$memory_bram.cc:1009:replace_memory$9613).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7501 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7494, Q = $auto$memory_bram.cc:1009:replace_memory$7498).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9015 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9008, Q = $auto$memory_bram.cc:1009:replace_memory$9012).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8544 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8537, Q = $auto$memory_bram.cc:1009:replace_memory$8541).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7514 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7507, Q = $auto$memory_bram.cc:1009:replace_memory$7511).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7527 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7520, Q = $auto$memory_bram.cc:1009:replace_memory$7524).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7540 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7533, Q = $auto$memory_bram.cc:1009:replace_memory$7537).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9473 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9466, Q = $auto$memory_bram.cc:1009:replace_memory$9470).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7553 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7546, Q = $auto$memory_bram.cc:1009:replace_memory$7550).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9028 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9021, Q = $auto$memory_bram.cc:1009:replace_memory$9025).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7566 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7559, Q = $auto$memory_bram.cc:1009:replace_memory$7563).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9793 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9786, Q = $auto$memory_bram.cc:1009:replace_memory$9790).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7579 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7572, Q = $auto$memory_bram.cc:1009:replace_memory$7576).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7592 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7585, Q = $auto$memory_bram.cc:1009:replace_memory$7589).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8565 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8558, Q = $auto$memory_bram.cc:1009:replace_memory$8562).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9041 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9034, Q = $auto$memory_bram.cc:1009:replace_memory$9038).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7605 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7598, Q = $auto$memory_bram.cc:1009:replace_memory$7602).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9322 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9315, Q = $auto$memory_bram.cc:1009:replace_memory$9319).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9486 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9479, Q = $auto$memory_bram.cc:1009:replace_memory$9483).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8825 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8818, Q = $auto$memory_bram.cc:1009:replace_memory$8822).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7618 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7611, Q = $auto$memory_bram.cc:1009:replace_memory$7615).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7631 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7624, Q = $auto$memory_bram.cc:1009:replace_memory$7628).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8578 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8571, Q = $auto$memory_bram.cc:1009:replace_memory$8575).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9054 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9047, Q = $auto$memory_bram.cc:1009:replace_memory$9051).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7644 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7637, Q = $auto$memory_bram.cc:1009:replace_memory$7641).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7657 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7650, Q = $auto$memory_bram.cc:1009:replace_memory$7654).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9702 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9695, Q = $auto$memory_bram.cc:1009:replace_memory$9699).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7670 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7663, Q = $auto$memory_bram.cc:1009:replace_memory$7667).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9067 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9060, Q = $auto$memory_bram.cc:1009:replace_memory$9064).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7683 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7676, Q = $auto$memory_bram.cc:1009:replace_memory$7680).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9499 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9492, Q = $auto$memory_bram.cc:1009:replace_memory$9496).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7696 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7689, Q = $auto$memory_bram.cc:1009:replace_memory$7693).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8591 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8584, Q = $auto$memory_bram.cc:1009:replace_memory$8588).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7717 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7710, Q = $auto$memory_bram.cc:1009:replace_memory$7714).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7730 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7723, Q = $auto$memory_bram.cc:1009:replace_memory$7727).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9080 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9073, Q = $auto$memory_bram.cc:1009:replace_memory$9077).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7743 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7736, Q = $auto$memory_bram.cc:1009:replace_memory$7740).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7756 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7749, Q = $auto$memory_bram.cc:1009:replace_memory$7753).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8604 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8597, Q = $auto$memory_bram.cc:1009:replace_memory$8601).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9512 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9505, Q = $auto$memory_bram.cc:1009:replace_memory$9509).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7769 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7762, Q = $auto$memory_bram.cc:1009:replace_memory$7766).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9093 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9086, Q = $auto$memory_bram.cc:1009:replace_memory$9090).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7782 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7775, Q = $auto$memory_bram.cc:1009:replace_memory$7779).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9335 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9328, Q = $auto$memory_bram.cc:1009:replace_memory$9332).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8838 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8831, Q = $auto$memory_bram.cc:1009:replace_memory$8835).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7795 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7788, Q = $auto$memory_bram.cc:1009:replace_memory$7792).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8617 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8610, Q = $auto$memory_bram.cc:1009:replace_memory$8614).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7808 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7801, Q = $auto$memory_bram.cc:1009:replace_memory$7805).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7821 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7814, Q = $auto$memory_bram.cc:1009:replace_memory$7818).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9106 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9099, Q = $auto$memory_bram.cc:1009:replace_memory$9103).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9715 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9708, Q = $auto$memory_bram.cc:1009:replace_memory$9712).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7834 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7827, Q = $auto$memory_bram.cc:1009:replace_memory$7831).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7847 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7840, Q = $auto$memory_bram.cc:1009:replace_memory$7844).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9525 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9518, Q = $auto$memory_bram.cc:1009:replace_memory$9522).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8630 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8623, Q = $auto$memory_bram.cc:1009:replace_memory$8627).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7860 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7853, Q = $auto$memory_bram.cc:1009:replace_memory$7857).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9119 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9112, Q = $auto$memory_bram.cc:1009:replace_memory$9116).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8903 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8896, Q = $auto$memory_bram.cc:1009:replace_memory$8900).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7873 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7866, Q = $auto$memory_bram.cc:1009:replace_memory$7870).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7886 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7879, Q = $auto$memory_bram.cc:1009:replace_memory$7883).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8643 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8636, Q = $auto$memory_bram.cc:1009:replace_memory$8640).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7899 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7892, Q = $auto$memory_bram.cc:1009:replace_memory$7896).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9132 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9125, Q = $auto$memory_bram.cc:1009:replace_memory$9129).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7912 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7905, Q = $auto$memory_bram.cc:1009:replace_memory$7909).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9806 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9799, Q = $auto$memory_bram.cc:1009:replace_memory$9803).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9348 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9341, Q = $auto$memory_bram.cc:1009:replace_memory$9345).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7925 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7918, Q = $auto$memory_bram.cc:1009:replace_memory$7922).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9538 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9531, Q = $auto$memory_bram.cc:1009:replace_memory$9535).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7938 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7931, Q = $auto$memory_bram.cc:1009:replace_memory$7935).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8656 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8649, Q = $auto$memory_bram.cc:1009:replace_memory$8653).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7951 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7944, Q = $auto$memory_bram.cc:1009:replace_memory$7948).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9145 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9138, Q = $auto$memory_bram.cc:1009:replace_memory$9142).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8851 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8844, Q = $auto$memory_bram.cc:1009:replace_memory$8848).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7964 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7957, Q = $auto$memory_bram.cc:1009:replace_memory$7961).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8669 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8662, Q = $auto$memory_bram.cc:1009:replace_memory$8666).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7977 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7970, Q = $auto$memory_bram.cc:1009:replace_memory$7974).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9637 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9630, Q = $auto$memory_bram.cc:1009:replace_memory$9634).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$7990 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7983, Q = $auto$memory_bram.cc:1009:replace_memory$7987).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9663 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9656, Q = $auto$memory_bram.cc:1009:replace_memory$9660).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9158 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9151, Q = $auto$memory_bram.cc:1009:replace_memory$9155).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8003 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$7996, Q = $auto$memory_bram.cc:1009:replace_memory$8000).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8016 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8009, Q = $auto$memory_bram.cc:1009:replace_memory$8013).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8682 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8675, Q = $auto$memory_bram.cc:1009:replace_memory$8679).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9728 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9721, Q = $auto$memory_bram.cc:1009:replace_memory$9725).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8029 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8022, Q = $auto$memory_bram.cc:1009:replace_memory$8026).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8042 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8035, Q = $auto$memory_bram.cc:1009:replace_memory$8039).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9171 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9164, Q = $auto$memory_bram.cc:1009:replace_memory$9168).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9361 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9354, Q = $auto$memory_bram.cc:1009:replace_memory$9358).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8055 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8048, Q = $auto$memory_bram.cc:1009:replace_memory$8052).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9551 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9544, Q = $auto$memory_bram.cc:1009:replace_memory$9548).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8695 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8688, Q = $auto$memory_bram.cc:1009:replace_memory$8692).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8068 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8061, Q = $auto$memory_bram.cc:1009:replace_memory$8065).
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Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8081 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8074, Q = $auto$memory_bram.cc:1009:replace_memory$8078).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9184 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9177, Q = $auto$memory_bram.cc:1009:replace_memory$9181).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8094 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8087, Q = $auto$memory_bram.cc:1009:replace_memory$8091).
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|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9767 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9760, Q = $auto$memory_bram.cc:1009:replace_memory$9764).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8107 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8100, Q = $auto$memory_bram.cc:1009:replace_memory$8104).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8864 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8857, Q = $auto$memory_bram.cc:1009:replace_memory$8861).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8120 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8113, Q = $auto$memory_bram.cc:1009:replace_memory$8117).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8708 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8701, Q = $auto$memory_bram.cc:1009:replace_memory$8705).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8141 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8134, Q = $auto$memory_bram.cc:1009:replace_memory$8138).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8154 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8147, Q = $auto$memory_bram.cc:1009:replace_memory$8151).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8167 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8160, Q = $auto$memory_bram.cc:1009:replace_memory$8164).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8180 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8173, Q = $auto$memory_bram.cc:1009:replace_memory$8177).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8721 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8714, Q = $auto$memory_bram.cc:1009:replace_memory$8718).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9205 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9198, Q = $auto$memory_bram.cc:1009:replace_memory$9202).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8193 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8186, Q = $auto$memory_bram.cc:1009:replace_memory$8190).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9374 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9367, Q = $auto$memory_bram.cc:1009:replace_memory$9371).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8206 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8199, Q = $auto$memory_bram.cc:1009:replace_memory$8203).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9421 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9414, Q = $auto$memory_bram.cc:1009:replace_memory$9418).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8219 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8212, Q = $auto$memory_bram.cc:1009:replace_memory$8216).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9564 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9557, Q = $auto$memory_bram.cc:1009:replace_memory$9561).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8734 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8727, Q = $auto$memory_bram.cc:1009:replace_memory$8731).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8232 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8225, Q = $auto$memory_bram.cc:1009:replace_memory$8229).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9218 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9211, Q = $auto$memory_bram.cc:1009:replace_memory$9215).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8245 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8238, Q = $auto$memory_bram.cc:1009:replace_memory$8242).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8258 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8251, Q = $auto$memory_bram.cc:1009:replace_memory$8255).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9741 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9734, Q = $auto$memory_bram.cc:1009:replace_memory$9738).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8271 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8264, Q = $auto$memory_bram.cc:1009:replace_memory$8268).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8747 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8740, Q = $auto$memory_bram.cc:1009:replace_memory$8744).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9231 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9224, Q = $auto$memory_bram.cc:1009:replace_memory$9228).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9650 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9643, Q = $auto$memory_bram.cc:1009:replace_memory$9647).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8284 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8277, Q = $auto$memory_bram.cc:1009:replace_memory$8281).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8877 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8870, Q = $auto$memory_bram.cc:1009:replace_memory$8874).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8297 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8290, Q = $auto$memory_bram.cc:1009:replace_memory$8294).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8310 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8303, Q = $auto$memory_bram.cc:1009:replace_memory$8307).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8760 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8753, Q = $auto$memory_bram.cc:1009:replace_memory$8757).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8323 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8316, Q = $auto$memory_bram.cc:1009:replace_memory$8320).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9244 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9237, Q = $auto$memory_bram.cc:1009:replace_memory$9241).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9387 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9380, Q = $auto$memory_bram.cc:1009:replace_memory$9384).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9780 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9773, Q = $auto$memory_bram.cc:1009:replace_memory$9777).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8336 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8329, Q = $auto$memory_bram.cc:1009:replace_memory$8333).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9577 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9570, Q = $auto$memory_bram.cc:1009:replace_memory$9574).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8349 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8342, Q = $auto$memory_bram.cc:1009:replace_memory$8346).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8773 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8766, Q = $auto$memory_bram.cc:1009:replace_memory$8770).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8362 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8355, Q = $auto$memory_bram.cc:1009:replace_memory$8359).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9257 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9250, Q = $auto$memory_bram.cc:1009:replace_memory$9254).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8375 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8368, Q = $auto$memory_bram.cc:1009:replace_memory$8372).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8388 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8381, Q = $auto$memory_bram.cc:1009:replace_memory$8385).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8401 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8394, Q = $auto$memory_bram.cc:1009:replace_memory$8398).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8786 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8779, Q = $auto$memory_bram.cc:1009:replace_memory$8783).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9270 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9263, Q = $auto$memory_bram.cc:1009:replace_memory$9267).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8414 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8407, Q = $auto$memory_bram.cc:1009:replace_memory$8411).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9590 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9583, Q = $auto$memory_bram.cc:1009:replace_memory$9587).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8427 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8420, Q = $auto$memory_bram.cc:1009:replace_memory$8424).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9819 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9812, Q = $auto$memory_bram.cc:1009:replace_memory$9816).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8890 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8883, Q = $auto$memory_bram.cc:1009:replace_memory$8887).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8440 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8433, Q = $auto$memory_bram.cc:1009:replace_memory$8437).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8799 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8792, Q = $auto$memory_bram.cc:1009:replace_memory$8796).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$8453 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$8446, Q = $auto$memory_bram.cc:1009:replace_memory$8450).
|
|
Adding EN signal on $auto$memory_bram.cc:1012:replace_memory$9283 ($dff) from module PQVexRiscvUlx3s (D = $auto$rtlil.cc:2159:Eq$9276, Q = $auto$memory_bram.cc:1009:replace_memory$9280).
|
|
|
|
2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 259 unused cells and 3336 unused wires.
|
|
<suppressed ~260 debug messages>
|
|
|
|
2.30.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.30.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.30.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~372 debug messages>
|
|
Removed a total of 124 cells.
|
|
|
|
2.30.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$opt_dff.cc:702:run$6618 ($sdff) from module PQVexRiscvUlx3s (D = \myMem_1_.aesCore.engine.mixColumn_cntColumn [1:0], Q = \myMem_1_.aesCore.engine.mixColumn_cntColumn [1:0]).
|
|
Handling D = Q on $auto$opt_dff.cc:764:run$10952 ($sdffe) from module PQVexRiscvUlx3s (conecting SRST instead).
|
|
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$10952 ($sdffe) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$10952 ($sdffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1 unused cells and 125 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.30.10. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
2.30.11. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~65 debug messages>
|
|
|
|
2.30.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
2.30.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 53 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.30.15. Finished fast OPT passes.
|
|
|
|
2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory \myMem_1_.aesCore.engine.sBoxMem in module \PQVexRiscvUlx3s:
|
|
created 256 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 255 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \myMem_1_.aesCore.engine.sBoxMemInv in module \PQVexRiscvUlx3s:
|
|
created 256 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 255 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \myMem_1_.aesCore.keySchedule.rconMem in module \PQVexRiscvUlx3s:
|
|
created 11 $dff cells and 0 static cells of width 8.
|
|
Extracted addr FF from read port 0 of PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.rconMem: myMem_1_.aesCore.keySchedule.rconMem$rdreg[0]
|
|
read interface: 1 $dff and 15 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \myMem_1_.aesCore.keySchedule.sBoxMem in module \PQVexRiscvUlx3s:
|
|
created 256 $dff cells and 0 static cells of width 8.
|
|
Extracted addr FF from read port 0 of PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem: myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[0]
|
|
Extracted addr FF from read port 1 of PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem: myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[1]
|
|
Extracted addr FF from read port 2 of PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem: myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[2]
|
|
Extracted addr FF from read port 3 of PQVexRiscvUlx3s.myMem_1_.aesCore.keySchedule.sBoxMem: myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[3]
|
|
read interface: 4 $dff and 1020 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
|
|
2.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~11 debug messages>
|
|
|
|
2.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~30 debug messages>
|
|
Removed a total of 10 cells.
|
|
|
|
2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 2/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 3/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 5/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 6/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 7/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 9/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 10/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 11/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 13/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 14/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 15/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5220.
|
|
dead port 2/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 3/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 4/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 6/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 7/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 8/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 10/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 11/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 12/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 14/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 15/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5237.
|
|
dead port 1/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 3/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 4/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 5/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 7/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 8/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 9/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 11/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 12/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 13/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 15/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5254.
|
|
dead port 1/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 2/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 4/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 5/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 6/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 8/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 9/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 10/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 12/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 13/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
dead port 14/16 on $pmux $flatten\myMem_1_.\aesCore.\engine.$procmux$5271.
|
|
Removed 45 multiplexer ports.
|
|
<suppressed ~480 debug messages>
|
|
|
|
2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3254:
|
|
Old ports: A=4'0000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 3'011 }, Y=\core_cpu._zz_130_ [3:0]
|
|
New ports: A=2'00, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3] 1'1 }, Y={ \core_cpu._zz_130_ [3] \core_cpu._zz_130_ [0] }
|
|
New connections: \core_cpu._zz_130_ [2:1] = { 1'0 \core_cpu._zz_130_ [0] }
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3385:
|
|
Old ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [30:25] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [30:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31:20] }, Y=\core_cpu.execute_BranchPlugin_branch_src2 [19:0]
|
|
New ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [24:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [24:20] }, Y={ \core_cpu.execute_BranchPlugin_branch_src2 [19:11] \core_cpu.execute_BranchPlugin_branch_src2 [4:0] }
|
|
New connections: \core_cpu.execute_BranchPlugin_branch_src2 [10:5] = \core_cpu.decode_to_execute_INSTRUCTION [30:25]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3636:
|
|
Old ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_69_ [7:0] \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated
|
|
New ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated [31:8]
|
|
New connections: \core_cpu.writeBack_DBusSimplePlugin_rspFormated [7:0] = \core_cpu._zz_69_ [7:0]
|
|
Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3653:
|
|
Old ports: A=\core_cpu.decode_to_execute_RS2, B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:0] }, Y=\_zz_20_
|
|
New ports: A=\core_cpu.decode_to_execute_RS2 [31:8], B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:8] }, Y=\_zz_20_ [31:8]
|
|
New connections: \_zz_20_ [7:0] = \core_cpu.decode_to_execute_RS2 [7:0]
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3707:
|
|
Old ports: A=0, B={ \core_cpu.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=30'000000000000000000000000000000, B=\core_cpu.CsrPlugin_mtvec_base, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10030$1591:
|
|
Old ports: A=4'0001, B=4'1001, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10030$1591_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10030$1591_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10030$1591_Y [2:0] = 3'001
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10033$1592:
|
|
Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$6964 [1:0]
|
|
New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$6964 [0]
|
|
New connections: $auto$wreduce.cc:454:run$6964 [1] = $auto$wreduce.cc:454:run$6964 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595:
|
|
Old ports: A=4'0110, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y [3] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y [1] }
|
|
New connections: { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y [2] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y [0] } = { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10042$1595_Y [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10048$1597:
|
|
Old ports: A=4'0100, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10048$1597_Y
|
|
New ports: A=2'01, B=2'10, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10048$1597_Y [3:2]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10048$1597_Y [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10054$1599:
|
|
Old ports: A=4'1010, B=4'0010, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10054$1599_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10054$1599_Y [3]
|
|
New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10054$1599_Y [2:0] = 3'010
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10057$1600:
|
|
Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$6967 [2:0]
|
|
New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$6967 [2] $auto$wreduce.cc:454:run$6967 [0] }
|
|
New connections: $auto$wreduce.cc:454:run$6967 [1] = $auto$wreduce.cc:454:run$6967 [0]
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10063$1602:
|
|
Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:454:run$6968 [1:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$6968 [1]
|
|
New connections: $auto$wreduce.cc:454:run$6968 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:10069$1604:
|
|
Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:454:run$6970 [2:0]
|
|
New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$6970 [2]
|
|
New connections: $auto$wreduce.cc:454:run$6970 [1:0] = 2'11
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$4974:
|
|
Old ports: A=3'100, B=3'010, Y=$flatten\myMem_1_.\aesCore.\engine.$12\sm_stateNext[2:0]
|
|
New ports: A=2'10, B=2'01, Y=$flatten\myMem_1_.\aesCore.\engine.$12\sm_stateNext[2:0] [2:1]
|
|
New connections: $flatten\myMem_1_.\aesCore.\engine.$12\sm_stateNext[2:0] [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$4990:
|
|
Old ports: A=3'101, B=3'010, Y=$flatten\myMem_1_.\aesCore.\engine.$11\sm_stateNext[2:0]
|
|
New ports: A=2'01, B=2'10, Y=$flatten\myMem_1_.\aesCore.\engine.$11\sm_stateNext[2:0] [1:0]
|
|
New connections: $flatten\myMem_1_.\aesCore.\engine.$11\sm_stateNext[2:0] [2] = $flatten\myMem_1_.\aesCore.\engine.$11\sm_stateNext[2:0] [0]
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$5008:
|
|
Old ports: A=3'010, B=3'100, Y=$flatten\myMem_1_.\aesCore.\engine.$8\sm_stateNext[2:0]
|
|
New ports: A=2'01, B=2'10, Y=$flatten\myMem_1_.\aesCore.\engine.$8\sm_stateNext[2:0] [2:1]
|
|
New connections: $flatten\myMem_1_.\aesCore.\engine.$8\sm_stateNext[2:0] [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$5028:
|
|
Old ports: A=3'101, B=3'001, Y=$flatten\myMem_1_.\aesCore.\engine.$7\sm_stateNext[2:0]
|
|
New ports: A=1'1, B=1'0, Y=$flatten\myMem_1_.\aesCore.\engine.$7\sm_stateNext[2:0] [2]
|
|
New connections: $flatten\myMem_1_.\aesCore.\engine.$7\sm_stateNext[2:0] [1:0] = 2'01
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$5062:
|
|
Old ports: A=2'11, B=2'01, Y=$auto$wreduce.cc:454:run$6972 [1:0]
|
|
New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$6972 [1]
|
|
New connections: $auto$wreduce.cc:454:run$6972 [0] = 1'1
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$ternary$PQVexRiscvUlx3s.v:4688$657:
|
|
Old ports: A=4'1010, B=4'0000, Y=$flatten\myMem_1_.\aesCore.\engine.$procmux$4288_Y
|
|
New ports: A=1'1, B=1'0, Y=$flatten\myMem_1_.\aesCore.\engine.$procmux$4288_Y [1]
|
|
New connections: { $flatten\myMem_1_.\aesCore.\engine.$procmux$4288_Y [3:2] $flatten\myMem_1_.\aesCore.\engine.$procmux$4288_Y [0] } = { $flatten\myMem_1_.\aesCore.\engine.$procmux$4288_Y [1] 2'00 }
|
|
Consolidated identical input bits for $pmux cell $procmux$2205:
|
|
Old ports: A=4'1111, B=8'00010011, Y=\_zz_22_
|
|
New ports: A=2'11, B=4'0001, Y=\_zz_22_ [2:1]
|
|
New connections: { \_zz_22_ [3] \_zz_22_ [0] } = { \_zz_22_ [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $ternary$PQVexRiscvUlx3s.v:12517$1900:
|
|
Old ports: A={ \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \_zz_7_ [31:2] 2'00 }, Y=$ternary$PQVexRiscvUlx3s.v:12517$1900_Y
|
|
New ports: A=\core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2], B=\_zz_7_ [31:2], Y=$ternary$PQVexRiscvUlx3s.v:12517$1900_Y [31:2]
|
|
New connections: $ternary$PQVexRiscvUlx3s.v:12517$1900_Y [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3699:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B={ \core_cpu.CsrPlugin_mepc [31:2] 2'00 }, Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0]
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=\core_cpu.CsrPlugin_mepc [31:2], Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2]
|
|
New connections: $flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\myMem_1_.\aesCore.\engine.$procmux$5046:
|
|
Old ports: A=$flatten\myMem_1_.\aesCore.\engine.$7\sm_stateNext[2:0], B=3'100, Y=$flatten\myMem_1_.\aesCore.\engine.$6\sm_stateNext[2:0]
|
|
New ports: A={ $flatten\myMem_1_.\aesCore.\engine.$7\sm_stateNext[2:0] [2] 1'1 }, B=2'10, Y={ $flatten\myMem_1_.\aesCore.\engine.$6\sm_stateNext[2:0] [2] $flatten\myMem_1_.\aesCore.\engine.$6\sm_stateNext[2:0] [0] }
|
|
New connections: $flatten\myMem_1_.\aesCore.\engine.$6\sm_stateNext[2:0] [1] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3704:
|
|
Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0], Y=\core_cpu.CsrPlugin_jumpInterface_payload
|
|
New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\core_cpu.CsrPlugin_jumpInterface_payload [31:2]
|
|
New connections: \core_cpu.CsrPlugin_jumpInterface_payload [1:0] = 2'00
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:8120$1149:
|
|
Old ports: A={ \core_cpu.execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\core_cpu.CsrPlugin_jumpInterface_payload, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload
|
|
New ports: A=\core_cpu.execute_to_memory_BRANCH_CALC [31:1], B={ \core_cpu.CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1]
|
|
New connections: \core_cpu.IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3680:
|
|
Old ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154_Y [31:2] 2'00 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload, Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] }
|
|
New ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:8137$1154_Y [31:2] 1'0 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1] }
|
|
New connections: $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 26 changes.
|
|
|
|
2.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
2.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[0]$10956 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[1]$10958 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[2]$10960 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[3]$10962 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[4]$10964 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[5]$10966 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[6]$10968 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[7]$10970 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[8]$10972 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[9]$10974 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[10]$10976 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[11]$10978 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[12]$10980 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[13]$10982 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[14]$10984 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[15]$10986 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[16]$10988 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[17]$10990 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[18]$10992 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[19]$10994 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[20]$10996 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[21]$10998 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[22]$11000 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[23]$11002 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[24]$11004 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[25]$11006 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[26]$11008 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[27]$11010 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[28]$11012 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[29]$11014 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[30]$11016 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[31]$11018 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[32]$11020 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[33]$11022 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[34]$11024 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[35]$11026 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[36]$11028 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[37]$11030 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[38]$11032 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[39]$11034 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[40]$11036 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[41]$11038 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[42]$11040 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[43]$11042 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[44]$11044 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[45]$11046 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[46]$11048 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[47]$11050 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[48]$11052 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[49]$11054 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[50]$11056 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[51]$11058 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[52]$11060 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[53]$11062 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[54]$11064 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[55]$11066 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[56]$11068 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[57]$11070 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[58]$11072 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[59]$11074 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[60]$11076 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[61]$11078 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[62]$11080 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[63]$11082 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[64]$11084 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[65]$11086 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[66]$11088 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[67]$11090 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[68]$11092 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[69]$11094 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[70]$11096 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[71]$11098 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[72]$11100 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[73]$11102 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[74]$11104 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[75]$11106 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[76]$11108 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[77]$11110 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[78]$11112 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[79]$11114 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[80]$11116 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[81]$11118 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[82]$11120 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[83]$11122 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[84]$11124 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[85]$11126 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[86]$11128 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[87]$11130 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[88]$11132 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[89]$11134 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[90]$11136 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[91]$11138 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[92]$11140 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[93]$11142 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[94]$11144 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[95]$11146 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[96]$11148 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[97]$11150 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[98]$11152 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[99]$11154 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[100]$11156 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[101]$11158 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[102]$11160 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[103]$11162 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[104]$11164 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[105]$11166 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[106]$11168 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[107]$11170 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[108]$11172 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[109]$11174 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[110]$11176 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[111]$11178 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[112]$11180 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[113]$11182 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[114]$11184 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[115]$11186 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[116]$11188 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[117]$11190 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[118]$11192 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[119]$11194 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[120]$11196 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[121]$11198 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[122]$11200 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[123]$11202 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[124]$11204 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[125]$11206 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[126]$11208 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[127]$11210 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[128]$11212 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[129]$11214 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[130]$11216 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[131]$11218 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[132]$11220 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[133]$11222 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[134]$11224 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[135]$11226 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[136]$11228 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[137]$11230 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[138]$11232 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[139]$11234 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[140]$11236 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[141]$11238 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[142]$11240 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[143]$11242 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[144]$11244 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[145]$11246 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[146]$11248 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[147]$11250 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[148]$11252 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[149]$11254 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[150]$11256 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[151]$11258 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[152]$11260 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[153]$11262 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[154]$11264 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[155]$11266 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[156]$11268 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[157]$11270 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[158]$11272 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[159]$11274 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[160]$11276 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[161]$11278 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[162]$11280 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[163]$11282 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[164]$11284 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[165]$11286 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[166]$11288 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[167]$11290 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[168]$11292 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[169]$11294 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[170]$11296 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[171]$11298 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[172]$11300 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[173]$11302 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[174]$11304 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[175]$11306 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[176]$11308 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[177]$11310 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[178]$11312 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[179]$11314 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[180]$11316 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[181]$11318 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[182]$11320 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[183]$11322 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[184]$11324 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[185]$11326 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[186]$11328 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[187]$11330 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[188]$11332 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[189]$11334 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[190]$11336 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[191]$11338 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[192]$11340 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[193]$11342 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[194]$11344 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[195]$11346 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[196]$11348 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[197]$11350 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[198]$11352 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[199]$11354 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[200]$11356 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[201]$11358 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[202]$11360 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[203]$11362 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[204]$11364 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[205]$11366 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[206]$11368 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[207]$11370 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[208]$11372 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[209]$11374 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[210]$11376 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[211]$11378 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[212]$11380 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[213]$11382 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[214]$11384 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[215]$11386 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[216]$11388 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[217]$11390 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[218]$11392 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[219]$11394 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[220]$11396 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[221]$11398 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[222]$11400 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[223]$11402 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[224]$11404 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[225]$11406 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[226]$11408 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[227]$11410 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[228]$11412 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[229]$11414 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[230]$11416 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[231]$11418 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[232]$11420 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[233]$11422 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[234]$11424 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[235]$11426 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[236]$11428 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[237]$11430 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[238]$11432 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[239]$11434 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[240]$11436 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[241]$11438 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[242]$11440 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[243]$11442 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[244]$11444 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[245]$11446 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[246]$11448 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[247]$11450 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[248]$11452 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[249]$11454 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[250]$11456 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[251]$11458 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[252]$11460 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[253]$11462 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[254]$11464 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMem[255]$11466 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[0]$12233 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[1]$12235 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[2]$12237 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[3]$12239 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[4]$12241 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[5]$12243 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[6]$12245 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[7]$12247 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[8]$12249 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[9]$12251 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[10]$12253 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[11]$12255 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[12]$12257 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[13]$12259 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[14]$12261 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[15]$12263 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[16]$12265 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[17]$12267 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[18]$12269 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[19]$12271 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[20]$12273 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[21]$12275 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[22]$12277 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[23]$12279 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[24]$12281 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[25]$12283 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[26]$12285 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[27]$12287 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[28]$12289 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[29]$12291 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[30]$12293 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[31]$12295 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[32]$12297 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[33]$12299 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[34]$12301 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[35]$12303 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[36]$12305 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[37]$12307 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[38]$12309 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[39]$12311 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[40]$12313 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[41]$12315 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[42]$12317 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[43]$12319 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[44]$12321 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[45]$12323 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[46]$12325 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[47]$12327 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[48]$12329 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[49]$12331 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[50]$12333 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[51]$12335 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[52]$12337 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[53]$12339 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[54]$12341 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[55]$12343 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[56]$12345 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[57]$12347 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[58]$12349 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[59]$12351 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[60]$12353 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[61]$12355 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[62]$12357 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[63]$12359 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[64]$12361 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[65]$12363 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[66]$12365 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[67]$12367 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[68]$12369 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[69]$12371 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[70]$12373 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[71]$12375 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[72]$12377 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[73]$12379 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[74]$12381 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[75]$12383 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[76]$12385 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[77]$12387 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[78]$12389 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[79]$12391 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[80]$12393 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[81]$12395 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[82]$12397 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[83]$12399 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[84]$12401 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[85]$12403 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[86]$12405 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[87]$12407 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[88]$12409 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[89]$12411 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[90]$12413 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[91]$12415 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[92]$12417 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[93]$12419 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[94]$12421 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[95]$12423 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[96]$12425 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[97]$12427 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[98]$12429 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[99]$12431 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[100]$12433 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[101]$12435 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[102]$12437 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[103]$12439 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[104]$12441 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[105]$12443 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[106]$12445 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[107]$12447 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[108]$12449 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[109]$12451 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[110]$12453 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[111]$12455 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[112]$12457 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[113]$12459 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[114]$12461 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[115]$12463 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[116]$12465 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[117]$12467 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[118]$12469 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[119]$12471 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[120]$12473 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[121]$12475 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[122]$12477 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[123]$12479 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[124]$12481 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[125]$12483 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[126]$12485 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[127]$12487 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[128]$12489 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[129]$12491 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[130]$12493 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[131]$12495 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[132]$12497 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[133]$12499 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[134]$12501 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[135]$12503 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[136]$12505 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[137]$12507 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[138]$12509 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[139]$12511 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[140]$12513 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[141]$12515 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[142]$12517 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[143]$12519 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[144]$12521 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[145]$12523 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[146]$12525 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[147]$12527 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[148]$12529 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[149]$12531 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[150]$12533 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[151]$12535 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[152]$12537 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[153]$12539 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[154]$12541 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[155]$12543 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[156]$12545 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[157]$12547 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[158]$12549 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[159]$12551 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[160]$12553 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[161]$12555 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[162]$12557 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[163]$12559 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[164]$12561 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[165]$12563 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[166]$12565 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[167]$12567 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[168]$12569 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[169]$12571 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[170]$12573 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[171]$12575 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[172]$12577 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[173]$12579 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[174]$12581 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[175]$12583 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[176]$12585 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[177]$12587 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[178]$12589 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[179]$12591 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[180]$12593 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[181]$12595 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[182]$12597 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[183]$12599 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[184]$12601 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[185]$12603 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[186]$12605 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[187]$12607 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[188]$12609 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[189]$12611 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[190]$12613 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[191]$12615 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[192]$12617 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[193]$12619 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[194]$12621 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[195]$12623 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[196]$12625 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[197]$12627 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[198]$12629 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[199]$12631 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[200]$12633 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[201]$12635 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[202]$12637 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[203]$12639 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[204]$12641 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[205]$12643 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[206]$12645 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[207]$12647 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[208]$12649 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[209]$12651 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[210]$12653 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[211]$12655 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[212]$12657 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[213]$12659 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[214]$12661 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[215]$12663 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[216]$12665 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[217]$12667 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[218]$12669 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[219]$12671 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[220]$12673 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[221]$12675 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[222]$12677 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[223]$12679 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[224]$12681 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[225]$12683 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[226]$12685 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[227]$12687 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[228]$12689 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[229]$12691 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[230]$12693 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[231]$12695 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[232]$12697 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[233]$12699 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[234]$12701 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[235]$12703 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[236]$12705 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[237]$12707 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[238]$12709 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[239]$12711 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[240]$12713 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[241]$12715 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[242]$12717 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[243]$12719 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[244]$12721 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[245]$12723 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[246]$12725 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[247]$12727 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[248]$12729 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[249]$12731 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[250]$12733 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[251]$12735 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[252]$12737 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[253]$12739 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[254]$12741 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.engine.sBoxMemInv[255]$12743 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[0]$13510 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[1]$13512 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[2]$13514 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[3]$13516 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[4]$13518 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[5]$13520 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[6]$13522 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[7]$13524 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[8]$13526 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[9]$13528 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.rconMem[10]$13530 ($dff) from module PQVexRiscvUlx3s.
|
|
Removing always-active EN on myMem_1_.aesCore.keySchedule.rconMem$rdreg[0] ($dffe) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[0]$13577 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[1]$13579 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[2]$13581 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[3]$13583 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[4]$13585 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[5]$13587 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[6]$13589 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[7]$13591 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[8]$13593 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[9]$13595 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[10]$13597 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[11]$13599 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[12]$13601 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[13]$13603 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[14]$13605 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[15]$13607 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[16]$13609 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[17]$13611 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[18]$13613 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[19]$13615 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[20]$13617 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[21]$13619 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[22]$13621 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[23]$13623 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[24]$13625 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[25]$13627 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[26]$13629 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[27]$13631 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[28]$13633 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[29]$13635 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[30]$13637 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[31]$13639 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[32]$13641 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[33]$13643 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[34]$13645 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[35]$13647 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[36]$13649 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[37]$13651 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[38]$13653 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[39]$13655 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[40]$13657 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[41]$13659 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[42]$13661 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[43]$13663 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[44]$13665 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[45]$13667 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[46]$13669 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[47]$13671 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[48]$13673 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[49]$13675 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[50]$13677 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[51]$13679 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[52]$13681 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[53]$13683 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[54]$13685 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[55]$13687 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[56]$13689 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[57]$13691 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[58]$13693 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[59]$13695 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[60]$13697 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[61]$13699 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[62]$13701 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[63]$13703 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[64]$13705 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[65]$13707 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[66]$13709 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[67]$13711 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[68]$13713 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[69]$13715 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[70]$13717 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[71]$13719 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[72]$13721 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[73]$13723 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[74]$13725 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[75]$13727 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[76]$13729 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[77]$13731 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[78]$13733 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[79]$13735 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[80]$13737 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[81]$13739 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[82]$13741 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[83]$13743 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[84]$13745 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[85]$13747 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[86]$13749 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[87]$13751 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[88]$13753 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[89]$13755 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[90]$13757 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[91]$13759 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[92]$13761 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[93]$13763 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[94]$13765 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[95]$13767 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[96]$13769 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[97]$13771 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[98]$13773 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[99]$13775 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[100]$13777 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[101]$13779 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[102]$13781 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[103]$13783 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[104]$13785 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[105]$13787 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[106]$13789 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[107]$13791 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[108]$13793 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[109]$13795 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[110]$13797 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[111]$13799 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[112]$13801 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[113]$13803 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[114]$13805 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[115]$13807 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[116]$13809 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[117]$13811 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[118]$13813 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[119]$13815 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[120]$13817 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[121]$13819 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[122]$13821 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[123]$13823 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[124]$13825 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[125]$13827 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[126]$13829 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[127]$13831 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[128]$13833 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[129]$13835 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[130]$13837 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[131]$13839 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[132]$13841 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[133]$13843 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[134]$13845 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[135]$13847 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[136]$13849 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[137]$13851 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[138]$13853 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[139]$13855 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[140]$13857 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[141]$13859 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[142]$13861 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[143]$13863 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[144]$13865 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[145]$13867 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[146]$13869 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[147]$13871 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[148]$13873 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[149]$13875 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[150]$13877 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[151]$13879 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[152]$13881 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[153]$13883 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[154]$13885 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[155]$13887 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[156]$13889 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[157]$13891 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[158]$13893 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[159]$13895 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[160]$13897 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[161]$13899 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[162]$13901 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[163]$13903 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[164]$13905 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[165]$13907 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[166]$13909 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[167]$13911 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[168]$13913 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[169]$13915 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[170]$13917 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[171]$13919 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[172]$13921 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[173]$13923 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[174]$13925 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[175]$13927 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[176]$13929 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[177]$13931 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[178]$13933 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[179]$13935 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[180]$13937 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[181]$13939 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[182]$13941 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[183]$13943 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[184]$13945 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[185]$13947 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[186]$13949 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[187]$13951 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[188]$13953 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[189]$13955 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[190]$13957 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[191]$13959 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[192]$13961 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[193]$13963 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[194]$13965 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[195]$13967 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[196]$13969 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[197]$13971 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[198]$13973 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[199]$13975 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[200]$13977 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[201]$13979 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[202]$13981 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[203]$13983 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[204]$13985 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[205]$13987 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[206]$13989 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[207]$13991 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[208]$13993 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[209]$13995 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[210]$13997 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[211]$13999 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[212]$14001 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[213]$14003 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[214]$14005 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[215]$14007 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[216]$14009 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[217]$14011 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[218]$14013 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[219]$14015 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[220]$14017 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[221]$14019 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[222]$14021 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[223]$14023 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[224]$14025 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[225]$14027 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[226]$14029 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[227]$14031 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[228]$14033 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[229]$14035 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[230]$14037 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[231]$14039 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[232]$14041 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[233]$14043 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[234]$14045 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[235]$14047 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[236]$14049 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[237]$14051 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[238]$14053 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[239]$14055 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[240]$14057 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[241]$14059 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[242]$14061 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[243]$14063 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[244]$14065 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[245]$14067 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[246]$14069 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[247]$14071 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[248]$14073 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[249]$14075 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[250]$14077 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[251]$14079 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[252]$14081 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[253]$14083 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 1-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[254]$14085 ($dff) from module PQVexRiscvUlx3s.
|
|
Handling const CLK on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s (removing D path).
|
|
Setting constant 0-bit at position 0 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 1 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 2 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 3 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 1-bit at position 4 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 5 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 6 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Setting constant 0-bit at position 7 on $memory\myMem_1_.aesCore.keySchedule.sBoxMem[255]$14087 ($dff) from module PQVexRiscvUlx3s.
|
|
Removing always-active EN on myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[0] ($dffe) from module PQVexRiscvUlx3s.
|
|
Removing always-active EN on myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[1] ($dffe) from module PQVexRiscvUlx3s.
|
|
Removing always-active EN on myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[2] ($dffe) from module PQVexRiscvUlx3s.
|
|
Removing always-active EN on myMem_1_.aesCore.keySchedule.sBoxMem$rdreg[3] ($dffe) from module PQVexRiscvUlx3s.
|
|
|
|
2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 2351 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~5 debug messages>
|
|
|
|
2.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~480 debug messages>
|
|
|
|
2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][0]$11849:
|
|
Old ports: A=8'01100011, B=8'01111100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] } = { 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][100]$12149:
|
|
Old ports: A=8'11101000, B=8'11011101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [4:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][101]$12152:
|
|
Old ports: A=8'01110100, B=8'00011111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [4:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][102]$12155:
|
|
Old ports: A=8'01001011, B=8'10111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][103]$12158:
|
|
Old ports: A=8'10001011, B=8'10001010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$b$11812
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$b$11812 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$b$11812 [7:1] = 7'1000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][104]$12161:
|
|
Old ports: A=8'01110000, B=8'00111110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [0] } = { 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][105]$12164:
|
|
Old ports: A=8'10110101, B=8'01100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][106]$12167:
|
|
Old ports: A=8'01001000, B=8'00000011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [3] 3'000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][107]$12170:
|
|
Old ports: A=8'11110110, B=8'00001110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][108]$12173:
|
|
Old ports: A=8'01100001, B=8'00110101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [1:0] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][109]$12176:
|
|
Old ports: A=8'01010111, B=8'10111001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][10]$11879:
|
|
Old ports: A=8'11111010, B=8'01011001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [1] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][110]$12179:
|
|
Old ports: A=8'10000110, B=8'11000001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [7:2] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [0] 3'000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][111]$12182:
|
|
Old ports: A=8'00011101, B=8'10011110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824 [1] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][112]$12185:
|
|
Old ports: A=8'11100001, B=8'11111000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [2:1] } = { 3'111 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [3] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][113]$12188:
|
|
Old ports: A=8'10011000, B=8'00010001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [3] 5'00100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][114]$12191:
|
|
Old ports: A=8'01101001, B=8'11011001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [3:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [4] 5'11001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][115]$12194:
|
|
Old ports: A=8'10001110, B=8'10010100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [0] } = { 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][116]$12197:
|
|
Old ports: A=8'10011011, B=8'00011110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][117]$12200:
|
|
Old ports: A=8'10000111, B=8'11101001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][118]$12203:
|
|
Old ports: A=8'11001110, B=8'01010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [1] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][119]$12206:
|
|
Old ports: A=8'00101000, B=8'11011111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][11]$11882:
|
|
Old ports: A=8'01000111, B=8'11110000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][120]$12209:
|
|
Old ports: A=8'10001100, B=8'10100001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [1] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][121]$12212:
|
|
Old ports: A=8'10001001, B=8'00001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [1:0] } = 6'000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][122]$12215:
|
|
Old ports: A=8'10111111, B=8'11100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [5:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][123]$12218:
|
|
Old ports: A=8'01000010, B=8'01101000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [0] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][124]$12221:
|
|
Old ports: A=8'01000001, B=8'10011001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][125]$12224:
|
|
Old ports: A=8'00101101, B=8'00001111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [0] } = 6'000111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][126]$12227:
|
|
Old ports: A=8'10110000, B=8'01010100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [2] 4'1000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][127]$12230:
|
|
Old ports: A=8'10111011, B=8'00010110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][12]$11885:
|
|
Old ports: A=8'10101101, B=8'11010100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][13]$11888:
|
|
Old ports: A=8'10100010, B=8'10101111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [7:1] = { 4'1010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][14]$11891:
|
|
Old ports: A=8'10011100, B=8'10100100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [2:0] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][15]$11894:
|
|
Old ports: A=8'01110010, B=8'11000000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][16]$11897:
|
|
Old ports: A=8'10110111, B=8'11111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][17]$11900:
|
|
Old ports: A=8'10010011, B=8'00100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][18]$11903:
|
|
Old ports: A=8'00110110, B=8'00111111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685 [7:1] = { 4'0011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][19]$11906:
|
|
Old ports: A=8'11110111, B=8'11001100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][1]$11852:
|
|
Old ports: A=8'01110111, B=8'01111011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659 [1:0] } = 6'011111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][20]$11909:
|
|
Old ports: A=8'00110100, B=8'10100101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [0] 5'01010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][21]$11912:
|
|
Old ports: A=8'11100101, B=8'11110001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [1:0] } = 6'111001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][22]$11915:
|
|
Old ports: A=8'01110001, B=8'11011000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][23]$11918:
|
|
Old ports: A=8'00110001, B=8'00010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [1:0] } = 6'001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][24]$11921:
|
|
Old ports: A=8'00000100, B=8'11000111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [7:1] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0] 4'0001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][25]$11924:
|
|
Old ports: A=8'00100011, B=8'11000011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695 [4:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695 [6] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][26]$11927:
|
|
Old ports: A=8'00011000, B=8'10010110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [1] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][27]$11930:
|
|
Old ports: A=8'00000101, B=8'10011010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][28]$11933:
|
|
Old ports: A=8'00000111, B=8'00010010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [3:1] } = { 4'0000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][29]$11936:
|
|
Old ports: A=8'10000000, B=8'11100010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [1] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][2]$11855:
|
|
Old ports: A=8'11110010, B=8'01101011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [4] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][30]$11939:
|
|
Old ports: A=8'11101011, B=8'00100111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][31]$11942:
|
|
Old ports: A=8'10110010, B=8'01110101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [1:0] 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][32]$11945:
|
|
Old ports: A=8'00001001, B=8'10000011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [1] 5'00001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][33]$11948:
|
|
Old ports: A=8'00101100, B=8'00011010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [0] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [2:1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][34]$11951:
|
|
Old ports: A=8'00011011, B=8'01101110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][35]$11954:
|
|
Old ports: A=8'01011010, B=8'10100000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][36]$11957:
|
|
Old ports: A=8'01010010, B=8'00111011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [5:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][37]$11960:
|
|
Old ports: A=8'11010110, B=8'10110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][38]$11963:
|
|
Old ports: A=8'00101001, B=8'11100011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][39]$11966:
|
|
Old ports: A=8'00101111, B=8'10000100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [6:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][3]$11858:
|
|
Old ports: A=8'01101111, B=8'11000101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][40]$11969:
|
|
Old ports: A=8'01010011, B=8'11010001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [0] } = 6'101001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][41]$11972:
|
|
Old ports: A=8'00000000, B=8'11101101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [7:1] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][42]$11975:
|
|
Old ports: A=8'00100000, B=8'11111100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][43]$11978:
|
|
Old ports: A=8'10110001, B=8'01011011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][44]$11981:
|
|
Old ports: A=8'01101010, B=8'11001011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [0] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][45]$11984:
|
|
Old ports: A=8'10111110, B=8'00111001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1] 4'0111 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][46]$11987:
|
|
Old ports: A=8'01001010, B=8'01001100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727 [0] } = 6'010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][47]$11990:
|
|
Old ports: A=8'01011000, B=8'11001111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] 3'101 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][48]$11993:
|
|
Old ports: A=8'11010000, B=8'11101111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [3:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][49]$11996:
|
|
Old ports: A=8'10101010, B=8'11111011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [7:1] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][4]$11861:
|
|
Old ports: A=8'00110000, B=8'00000001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [3:1] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [4] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][50]$11999:
|
|
Old ports: A=8'01000011, B=8'01001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [0] } = { 4'0100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][51]$12002:
|
|
Old ports: A=8'00110011, B=8'10000101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][52]$12005:
|
|
Old ports: A=8'01000101, B=8'11111001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][53]$12008:
|
|
Old ports: A=8'00000010, B=8'01111111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [7:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][54]$12011:
|
|
Old ports: A=8'01010000, B=8'00111100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][55]$12014:
|
|
Old ports: A=8'10011111, B=8'10101000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [4:1] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][56]$12017:
|
|
Old ports: A=8'01010001, B=8'10100011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][57]$12020:
|
|
Old ports: A=8'01000000, B=8'10001111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [5:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][58]$12023:
|
|
Old ports: A=8'10010010, B=8'10011101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [7:2] = { 4'1001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][59]$12026:
|
|
Old ports: A=8'00111000, B=8'11110101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][5]$11864:
|
|
Old ports: A=8'01100111, B=8'00101011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665 [2] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][60]$12029:
|
|
Old ports: A=8'10111100, B=8'10110110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [0] } = 6'101110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][61]$12032:
|
|
Old ports: A=8'11011010, B=8'00100001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][62]$12035:
|
|
Old ports: A=8'00010000, B=8'11111111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [7:1] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][63]$12038:
|
|
Old ports: A=8'11110011, B=8'11010010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [7:1] = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [0] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][64]$12041:
|
|
Old ports: A=8'11001101, B=8'00001100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [7:1] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [0] 5'00110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][65]$12044:
|
|
Old ports: A=8'00010011, B=8'11101100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][66]$12047:
|
|
Old ports: A=8'01011111, B=8'10010111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [6:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [3] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][67]$12050:
|
|
Old ports: A=8'01000100, B=8'00010111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [5:1] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][68]$12053:
|
|
Old ports: A=8'11000100, B=8'10100111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [5:1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][69]$12056:
|
|
Old ports: A=8'01111110, B=8'00111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761 [1] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][6]$11867:
|
|
Old ports: A=8'11111110, B=8'11010111, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][70]$12059:
|
|
Old ports: A=8'01100100, B=8'01011101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][71]$12062:
|
|
Old ports: A=8'00011001, B=8'01110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][72]$12065:
|
|
Old ports: A=8'01100000, B=8'10000001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [5] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][73]$12068:
|
|
Old ports: A=8'01001111, B=8'11011100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [4] 4'1011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][74]$12071:
|
|
Old ports: A=8'00100010, B=8'00101010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769 [2:0] } = 7'0010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][75]$12074:
|
|
Old ports: A=8'10010000, B=8'10001000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770 [2:0] } = 6'100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][76]$12077:
|
|
Old ports: A=8'01000110, B=8'11101110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [3] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][77]$12080:
|
|
Old ports: A=8'10111000, B=8'00010100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][78]$12083:
|
|
Old ports: A=8'11011110, B=8'01011110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$a$11775
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$a$11775 [7]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$a$11775 [6:0] = 7'1011110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][79]$12086:
|
|
Old ports: A=8'00001011, B=8'11011011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [3:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [4] 5'01011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][7]$11870:
|
|
Old ports: A=8'10101011, B=8'01110110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][80]$12089:
|
|
Old ports: A=8'11100000, B=8'00110010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][81]$12092:
|
|
Old ports: A=8'00111010, B=8'00001010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [3:0] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [4] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][82]$12095:
|
|
Old ports: A=8'01001001, B=8'00000110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][83]$12098:
|
|
Old ports: A=8'00100100, B=8'01011100, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [2:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][84]$12101:
|
|
Old ports: A=8'11000010, B=8'11010011, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784 [7:1] = { 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784 [0] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][85]$12104:
|
|
Old ports: A=8'10101100, B=8'01100010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [2:1] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][86]$12107:
|
|
Old ports: A=8'10010001, B=8'10010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787 [1:0] } = 7'1001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][87]$12110:
|
|
Old ports: A=8'11100100, B=8'01111001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [2] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][88]$12113:
|
|
Old ports: A=8'11100111, B=8'11001000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][89]$12116:
|
|
Old ports: A=8'00110111, B=8'01101101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][8]$11873:
|
|
Old ports: A=8'11001010, B=8'10000010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670 [3] 5'00010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][90]$12119:
|
|
Old ports: A=8'10001101, B=8'11010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][91]$12122:
|
|
Old ports: A=8'01001110, B=8'10101001, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1:0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][92]$12125:
|
|
Old ports: A=8'01101100, B=8'01010110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [0] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][93]$12128:
|
|
Old ports: A=8'11110100, B=8'11101010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [0] } = { 3'111 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [2:1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][94]$12131:
|
|
Old ports: A=8'01100101, B=8'01111010, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$a$11799
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$a$11799 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$a$11799 [7:2] = { 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$a$11799 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$a$11799 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][95]$12134:
|
|
Old ports: A=8'10101110, B=8'00001000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [1] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][47]$b$11800 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][96]$12137:
|
|
Old ports: A=8'10111010, B=8'01111000, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [1] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][97]$12140:
|
|
Old ports: A=8'00100101, B=8'00101110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803 [7:2] = { 4'0010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][98]$12143:
|
|
Old ports: A=8'00011100, B=8'10100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][99]$12146:
|
|
Old ports: A=8'10110100, B=8'11000110, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [4] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][7][9]$11876:
|
|
Old ports: A=8'11001001, B=8'01111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][0]$13126:
|
|
Old ports: A=8'01010010, B=8'00001001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1:0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][100]$13426:
|
|
Old ports: A=8'10110001, B=8'00010010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][101]$13429:
|
|
Old ports: A=8'00010000, B=8'01011001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [7:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [0] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][102]$13432:
|
|
Old ports: A=8'00100111, B=8'10000000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [6:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][103]$13435:
|
|
Old ports: A=8'11101100, B=8'01011111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][104]$13438:
|
|
Old ports: A=8'01100000, B=8'01010001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [0] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][105]$13441:
|
|
Old ports: A=8'01111111, B=8'10101001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][106]$13444:
|
|
Old ports: A=8'00011001, B=8'10110101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][107]$13447:
|
|
Old ports: A=8'01001010, B=8'00001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [1] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][108]$13450:
|
|
Old ports: A=8'00101101, B=8'11100101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [6] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][109]$13453:
|
|
Old ports: A=8'01111010, B=8'10011111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [5] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][10]$13156:
|
|
Old ports: A=8'10011011, B=8'00101111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [2] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][110]$13456:
|
|
Old ports: A=8'10010011, B=8'11001001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][111]$13459:
|
|
Old ports: A=8'10011100, B=8'11101111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][112]$13462:
|
|
Old ports: A=8'10100000, B=8'11100000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103 [6]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103 [5:0] } = 7'1100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][113]$13465:
|
|
Old ports: A=8'00111011, B=8'01001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][114]$13468:
|
|
Old ports: A=8'10101110, B=8'00101010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [2] 6'010110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][115]$13471:
|
|
Old ports: A=8'11110101, B=8'10110000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [7:1] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [0] 3'110 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][116]$13474:
|
|
Old ports: A=8'11001000, B=8'11101011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [7:1] = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [0] 3'010 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][117]$13477:
|
|
Old ports: A=8'10111011, B=8'00111100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [0] 4'0111 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][118]$13480:
|
|
Old ports: A=8'10000011, B=8'01010011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [4] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [3:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [4] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][119]$13483:
|
|
Old ports: A=8'10011001, B=8'01100001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][11]$13159:
|
|
Old ports: A=8'11111111, B=8'10000111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][120]$13486:
|
|
Old ports: A=8'00010111, B=8'00101011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [1:0] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [3:2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][121]$13489:
|
|
Old ports: A=8'00000100, B=8'01111110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][122]$13492:
|
|
Old ports: A=8'10111010, B=8'01110111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][123]$13495:
|
|
Old ports: A=8'11010110, B=8'00100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [3:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [4] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][124]$13498:
|
|
Old ports: A=8'11100001, B=8'01101001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [6:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [2:0] } = 6'110001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][125]$13501:
|
|
Old ports: A=8'00010100, B=8'01100011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][126]$13504:
|
|
Old ports: A=8'01010101, B=8'00100001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][127]$13507:
|
|
Old ports: A=8'00001100, B=8'01111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [7:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][12]$13162:
|
|
Old ports: A=8'00110100, B=8'10001110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][13]$13165:
|
|
Old ports: A=8'01000011, B=8'01000100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [1] } = { 5'01000 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][14]$13168:
|
|
Old ports: A=8'11000100, B=8'11011110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [0] } = { 3'110 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][15]$13171:
|
|
Old ports: A=8'11101001, B=8'11001011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [0] } = 6'110101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][16]$13174:
|
|
Old ports: A=8'01010100, B=8'01111011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [1] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][17]$13177:
|
|
Old ports: A=8'10010100, B=8'00110010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [1] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][18]$13180:
|
|
Old ports: A=8'10100110, B=8'11000010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [2] 4'0010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][19]$13183:
|
|
Old ports: A=8'00100011, B=8'00111101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [0] } = { 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][1]$13129:
|
|
Old ports: A=8'01101010, B=8'11010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][20]$13186:
|
|
Old ports: A=8'11101110, B=8'01001100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$a$12965 [1] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][21]$13189:
|
|
Old ports: A=8'10010101, B=8'00001011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966 [2] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][10]$b$12966 [2:1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][22]$13192:
|
|
Old ports: A=8'01000010, B=8'11111010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][23]$13195:
|
|
Old ports: A=8'11000011, B=8'01001110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [0] 3'100 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][24]$13198:
|
|
Old ports: A=8'00001000, B=8'00101110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [0] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [1] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][25]$13201:
|
|
Old ports: A=8'10100001, B=8'01100110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [1] 3'100 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][26]$13204:
|
|
Old ports: A=8'00101000, B=8'11011001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][27]$13207:
|
|
Old ports: A=8'00100100, B=8'10110010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [1] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][28]$13210:
|
|
Old ports: A=8'01110110, B=8'01011011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [1] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][29]$13213:
|
|
Old ports: A=8'10100010, B=8'01001001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][2]$13132:
|
|
Old ports: A=8'00110000, B=8'00110110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [0] } = { 5'00110 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][30]$13216:
|
|
Old ports: A=8'01101101, B=8'10001011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [2] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][31]$13219:
|
|
Old ports: A=8'11010001, B=8'00100101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][32]$13222:
|
|
Old ports: A=8'01110010, B=8'11111000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [3] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][33]$13225:
|
|
Old ports: A=8'11110110, B=8'01100100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][34]$13228:
|
|
Old ports: A=8'10000110, B=8'01101000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][35]$13231:
|
|
Old ports: A=8'10011000, B=8'00010110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [3] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][36]$13234:
|
|
Old ports: A=8'11010100, B=8'10100100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [3:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [4] 4'0100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][37]$13237:
|
|
Old ports: A=8'01011100, B=8'11001100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [4] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [3:0] } = 6'101100
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][38]$13240:
|
|
Old ports: A=8'01011101, B=8'01100101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [2:0] } = { 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [3] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][39]$13243:
|
|
Old ports: A=8'10110110, B=8'10010010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [1:0] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [2] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][3]$13135:
|
|
Old ports: A=8'10100101, B=8'00111000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][40]$13246:
|
|
Old ports: A=8'01101100, B=8'01110000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [1:0] } = { 3'011 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][41]$13249:
|
|
Old ports: A=8'01001000, B=8'01010000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996 [2:0] } = 6'010000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][42]$13252:
|
|
Old ports: A=8'11111101, B=8'11101101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998 [3:0] } = 7'1111101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][43]$13255:
|
|
Old ports: A=8'10111001, B=8'11011010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999 [7:2] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999 [1:0] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][44]$13258:
|
|
Old ports: A=8'01011110, B=8'00010101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [1] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][45]$13261:
|
|
Old ports: A=8'01000110, B=8'01010111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002 [7:1] = { 3'010 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002 [0] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][46]$13264:
|
|
Old ports: A=8'10100111, B=8'10001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [0] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [1] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][47]$13267:
|
|
Old ports: A=8'10011101, B=8'10000100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [7:1] = { 3'100 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][48]$13270:
|
|
Old ports: A=8'10010000, B=8'11011000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [3] 5'01000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][49]$13273:
|
|
Old ports: A=8'10101011, B=8'00000000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [7:1] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][4]$13138:
|
|
Old ports: A=8'10111111, B=8'01000000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [5:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][50]$13276:
|
|
Old ports: A=8'10001100, B=8'10111100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [3:0] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [4] 4'1100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][51]$13279:
|
|
Old ports: A=8'11010011, B=8'00001010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][52]$13282:
|
|
Old ports: A=8'11110111, B=8'11100100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [7:1] = { 3'111 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][53]$13285:
|
|
Old ports: A=8'01011000, B=8'00000101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][54]$13288:
|
|
Old ports: A=8'10111000, B=8'10110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [2:1] } = { 5'10110 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][55]$13291:
|
|
Old ports: A=8'01000101, B=8'00000110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017 [0] 4'0001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][56]$13294:
|
|
Old ports: A=8'11010000, B=8'00101100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [1:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][57]$13297:
|
|
Old ports: A=8'00011110, B=8'10001111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][58]$13300:
|
|
Old ports: A=8'11001010, B=8'00111111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [5:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][59]$13303:
|
|
Old ports: A=8'00001111, B=8'00000010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [7:1] = { 4'0000 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][5]$13141:
|
|
Old ports: A=8'10100011, B=8'10011110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [1] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][60]$13306:
|
|
Old ports: A=8'11000001, B=8'10101111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][61]$13309:
|
|
Old ports: A=8'10111101, B=8'00000011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][62]$13312:
|
|
Old ports: A=8'00000001, B=8'00010011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [0] } = { 3'000 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][63]$13315:
|
|
Old ports: A=8'10001010, B=8'01101011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [6:1] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [0] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][64]$13318:
|
|
Old ports: A=8'00111010, B=8'10010001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][65]$13321:
|
|
Old ports: A=8'00010001, B=8'01000001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [4] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [3:0] } = 6'000001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][66]$13324:
|
|
Old ports: A=8'01001111, B=8'01100111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [2:0] } = 6'010111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][67]$13327:
|
|
Old ports: A=8'11011100, B=8'11101010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [0] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [2] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][68]$13330:
|
|
Old ports: A=8'10010111, B=8'11110010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [4:1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [5] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][69]$13333:
|
|
Old ports: A=8'11001111, B=8'11001110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$b$13038
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$b$13038 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$b$13038 [7:1] = 7'1100111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][6]$13144:
|
|
Old ports: A=8'10000001, B=8'11110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][70]$13336:
|
|
Old ports: A=8'11110000, B=8'10110100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [1:0] } = 6'111000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][71]$13339:
|
|
Old ports: A=8'11100110, B=8'01110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [2] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][72]$13342:
|
|
Old ports: A=8'10010110, B=8'10101100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [0] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][73]$13345:
|
|
Old ports: A=8'01110100, B=8'00100010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][74]$13348:
|
|
Old ports: A=8'11100111, B=8'10101101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [1] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][75]$13351:
|
|
Old ports: A=8'00110101, B=8'10000101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [4] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [3:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][76]$13354:
|
|
Old ports: A=8'11100010, B=8'11111001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [7:2] = { 3'111 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][77]$13357:
|
|
Old ports: A=8'00110111, B=8'11101000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][78]$13360:
|
|
Old ports: A=8'00011100, B=8'01110101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][79]$13363:
|
|
Old ports: A=8'11011111, B=8'01101110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [4:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][7]$13147:
|
|
Old ports: A=8'11010111, B=8'11111011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [1:0] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][80]$13366:
|
|
Old ports: A=8'01000111, B=8'11110001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][81]$13369:
|
|
Old ports: A=8'00011010, B=8'01110001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [7:2] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][82]$13372:
|
|
Old ports: A=8'00011101, B=8'00101001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [1:0] } = { 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][83]$13375:
|
|
Old ports: A=8'11000101, B=8'10001001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [2] 4'0001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][84]$13378:
|
|
Old ports: A=8'01101111, B=8'10110111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [2:0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [4:3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][85]$13381:
|
|
Old ports: A=8'01100010, B=8'00001110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [2] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][86]$13384:
|
|
Old ports: A=8'10101010, B=8'00011000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [1] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][87]$13387:
|
|
Old ports: A=8'10111110, B=8'00011011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [2] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][88]$13390:
|
|
Old ports: A=8'11111100, B=8'01010110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][89]$13393:
|
|
Old ports: A=8'00111110, B=8'01001011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][8]$13150:
|
|
Old ports: A=8'01111100, B=8'11100011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][90]$13396:
|
|
Old ports: A=8'11000110, B=8'11010010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [1:0] } = 6'110010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][91]$13399:
|
|
Old ports: A=8'01111001, B=8'00100000, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [7:1] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][92]$13402:
|
|
Old ports: A=8'10011010, B=8'11011011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073 [0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073 [7:1] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073 [0] 5'01101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][93]$13405:
|
|
Old ports: A=8'11000000, B=8'11111110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [0] } = { 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][94]$13408:
|
|
Old ports: A=8'01111000, B=8'11001101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [3:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][95]$13411:
|
|
Old ports: A=8'01011010, B=8'11110100, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][96]$13414:
|
|
Old ports: A=8'00011111, B=8'11011101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [6] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][97]$13417:
|
|
Old ports: A=8'10101000, B=8'00110011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [3] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][98]$13420:
|
|
Old ports: A=8'10001000, B=8'00000111, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [3] 3'000 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][99]$13423:
|
|
Old ports: A=8'11000111, B=8'00110001, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][7][9]$13153:
|
|
Old ports: A=8'00111001, B=8'10000010, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [7:2] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][0]$13553:
|
|
Old ports: A=8'10001101, B=8'00000001, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [7:3] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [2] 3'000 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [2] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][1]$13556:
|
|
Old ports: A=8'00000010, B=8'00000100, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543 [7:3] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543 [0] } = 6'000000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][2]$13559:
|
|
Old ports: A=8'00001000, B=8'00010000, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545 [7:5] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545 [2:0] } = 6'000000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][3]$13562:
|
|
Old ports: A=8'00100000, B=8'01000000, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546 [7] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546 [4:0] } = 6'000000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][4]$13565:
|
|
Old ports: A=8'10000000, B=8'00011011, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [7] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [6:1] = { 2'00 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][3][5]$13568:
|
|
Old ports: A=8'00110110, B=8'xxxxxxxx, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549
|
|
New ports: A=2'10, B=2'xx, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1:0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][0]$14470:
|
|
Old ports: A=8'01100011, B=8'01111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][100]$14770:
|
|
Old ports: A=8'11101000, B=8'11011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [4:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][101]$14773:
|
|
Old ports: A=8'01110100, B=8'00011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [4:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][102]$14776:
|
|
Old ports: A=8'01001011, B=8'10111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][103]$14779:
|
|
Old ports: A=8'10001011, B=8'10001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$b$14433
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$b$14433 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$b$14433 [7:1] = 7'1000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][104]$14782:
|
|
Old ports: A=8'01110000, B=8'00111110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [0] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][105]$14785:
|
|
Old ports: A=8'10110101, B=8'01100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][106]$14788:
|
|
Old ports: A=8'01001000, B=8'00000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [3] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][107]$14791:
|
|
Old ports: A=8'11110110, B=8'00001110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][108]$14794:
|
|
Old ports: A=8'01100001, B=8'00110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [1:0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][109]$14797:
|
|
Old ports: A=8'01010111, B=8'10111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][10]$14500:
|
|
Old ports: A=8'11111010, B=8'01011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [1] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][110]$14800:
|
|
Old ports: A=8'10000110, B=8'11000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [7:2] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [0] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][111]$14803:
|
|
Old ports: A=8'00011101, B=8'10011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445 [1] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][112]$14806:
|
|
Old ports: A=8'11100001, B=8'11111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [2:1] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [3] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][113]$14809:
|
|
Old ports: A=8'10011000, B=8'00010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [3] 5'00100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][114]$14812:
|
|
Old ports: A=8'01101001, B=8'11011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [4] 5'11001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][115]$14815:
|
|
Old ports: A=8'10001110, B=8'10010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [0] } = { 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][116]$14818:
|
|
Old ports: A=8'10011011, B=8'00011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][117]$14821:
|
|
Old ports: A=8'10000111, B=8'11101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][118]$14824:
|
|
Old ports: A=8'11001110, B=8'01010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][119]$14827:
|
|
Old ports: A=8'00101000, B=8'11011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][11]$14503:
|
|
Old ports: A=8'01000111, B=8'11110000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][120]$14830:
|
|
Old ports: A=8'10001100, B=8'10100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][121]$14833:
|
|
Old ports: A=8'10001001, B=8'00001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [1:0] } = 6'000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][122]$14836:
|
|
Old ports: A=8'10111111, B=8'11100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [5:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][123]$14839:
|
|
Old ports: A=8'01000010, B=8'01101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][124]$14842:
|
|
Old ports: A=8'01000001, B=8'10011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][125]$14845:
|
|
Old ports: A=8'00101101, B=8'00001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [0] } = 6'000111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][126]$14848:
|
|
Old ports: A=8'10110000, B=8'01010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [2] 4'1000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][127]$14851:
|
|
Old ports: A=8'10111011, B=8'00010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][12]$14506:
|
|
Old ports: A=8'10101101, B=8'11010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][13]$14509:
|
|
Old ports: A=8'10100010, B=8'10101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [7:1] = { 4'1010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][14]$14512:
|
|
Old ports: A=8'10011100, B=8'10100100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [2:0] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][15]$14515:
|
|
Old ports: A=8'01110010, B=8'11000000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][16]$14518:
|
|
Old ports: A=8'10110111, B=8'11111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][17]$14521:
|
|
Old ports: A=8'10010011, B=8'00100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][18]$14524:
|
|
Old ports: A=8'00110110, B=8'00111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306 [7:1] = { 4'0011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][19]$14527:
|
|
Old ports: A=8'11110111, B=8'11001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][1]$14473:
|
|
Old ports: A=8'01110111, B=8'01111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280 [1:0] } = 6'011111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][20]$14530:
|
|
Old ports: A=8'00110100, B=8'10100101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [0] 5'01010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][21]$14533:
|
|
Old ports: A=8'11100101, B=8'11110001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [1:0] } = 6'111001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][22]$14536:
|
|
Old ports: A=8'01110001, B=8'11011000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][23]$14539:
|
|
Old ports: A=8'00110001, B=8'00010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [1:0] } = 6'001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][24]$14542:
|
|
Old ports: A=8'00000100, B=8'11000111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0] 4'0001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][25]$14545:
|
|
Old ports: A=8'00100011, B=8'11000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316 [4:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316 [6] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][26]$14548:
|
|
Old ports: A=8'00011000, B=8'10010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [1] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][27]$14551:
|
|
Old ports: A=8'00000101, B=8'10011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][28]$14554:
|
|
Old ports: A=8'00000111, B=8'00010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [3:1] } = { 4'0000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][29]$14557:
|
|
Old ports: A=8'10000000, B=8'11100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [1] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][2]$14476:
|
|
Old ports: A=8'11110010, B=8'01101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][30]$14560:
|
|
Old ports: A=8'11101011, B=8'00100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][31]$14563:
|
|
Old ports: A=8'10110010, B=8'01110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [1:0] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][32]$14566:
|
|
Old ports: A=8'00001001, B=8'10000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [1] 5'00001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][33]$14569:
|
|
Old ports: A=8'00101100, B=8'00011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [2:1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][34]$14572:
|
|
Old ports: A=8'00011011, B=8'01101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][35]$14575:
|
|
Old ports: A=8'01011010, B=8'10100000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][36]$14578:
|
|
Old ports: A=8'01010010, B=8'00111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [5:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][37]$14581:
|
|
Old ports: A=8'11010110, B=8'10110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][38]$14584:
|
|
Old ports: A=8'00101001, B=8'11100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][39]$14587:
|
|
Old ports: A=8'00101111, B=8'10000100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [6:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][3]$14479:
|
|
Old ports: A=8'01101111, B=8'11000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][40]$14590:
|
|
Old ports: A=8'01010011, B=8'11010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [0] } = 6'101001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][41]$14593:
|
|
Old ports: A=8'00000000, B=8'11101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][42]$14596:
|
|
Old ports: A=8'00100000, B=8'11111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][43]$14599:
|
|
Old ports: A=8'10110001, B=8'01011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][44]$14602:
|
|
Old ports: A=8'01101010, B=8'11001011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [0] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][45]$14605:
|
|
Old ports: A=8'10111110, B=8'00111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1] 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][46]$14608:
|
|
Old ports: A=8'01001010, B=8'01001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348 [0] } = 6'010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][47]$14611:
|
|
Old ports: A=8'01011000, B=8'11001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] 3'101 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][48]$14614:
|
|
Old ports: A=8'11010000, B=8'11101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [3:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][49]$14617:
|
|
Old ports: A=8'10101010, B=8'11111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [7:1] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][4]$14482:
|
|
Old ports: A=8'00110000, B=8'00000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [3:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [4] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][50]$14620:
|
|
Old ports: A=8'01000011, B=8'01001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [0] } = { 4'0100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][51]$14623:
|
|
Old ports: A=8'00110011, B=8'10000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][52]$14626:
|
|
Old ports: A=8'01000101, B=8'11111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][53]$14629:
|
|
Old ports: A=8'00000010, B=8'01111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [7:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][54]$14632:
|
|
Old ports: A=8'01010000, B=8'00111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][55]$14635:
|
|
Old ports: A=8'10011111, B=8'10101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [4:1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][56]$14638:
|
|
Old ports: A=8'01010001, B=8'10100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][57]$14641:
|
|
Old ports: A=8'01000000, B=8'10001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [5:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][58]$14644:
|
|
Old ports: A=8'10010010, B=8'10011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [7:2] = { 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][59]$14647:
|
|
Old ports: A=8'00111000, B=8'11110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][5]$14485:
|
|
Old ports: A=8'01100111, B=8'00101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286 [2] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][60]$14650:
|
|
Old ports: A=8'10111100, B=8'10110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [0] } = 6'101110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][61]$14653:
|
|
Old ports: A=8'11011010, B=8'00100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][62]$14656:
|
|
Old ports: A=8'00010000, B=8'11111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][63]$14659:
|
|
Old ports: A=8'11110011, B=8'11010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373 [7:1] = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373 [0] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][64]$14662:
|
|
Old ports: A=8'11001101, B=8'00001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [0] 5'00110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][65]$14665:
|
|
Old ports: A=8'00010011, B=8'11101100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][66]$14668:
|
|
Old ports: A=8'01011111, B=8'10010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [3] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][67]$14671:
|
|
Old ports: A=8'01000100, B=8'00010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [5:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][68]$14674:
|
|
Old ports: A=8'11000100, B=8'10100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [5:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][69]$14677:
|
|
Old ports: A=8'01111110, B=8'00111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382 [1] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][6]$14488:
|
|
Old ports: A=8'11111110, B=8'11010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][70]$14680:
|
|
Old ports: A=8'01100100, B=8'01011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][71]$14683:
|
|
Old ports: A=8'00011001, B=8'01110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][72]$14686:
|
|
Old ports: A=8'01100000, B=8'10000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [5] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][73]$14689:
|
|
Old ports: A=8'01001111, B=8'11011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [4] 4'1011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][74]$14692:
|
|
Old ports: A=8'00100010, B=8'00101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390 [2:0] } = 7'0010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][75]$14695:
|
|
Old ports: A=8'10010000, B=8'10001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391 [2:0] } = 6'100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][76]$14698:
|
|
Old ports: A=8'01000110, B=8'11101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [3] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][77]$14701:
|
|
Old ports: A=8'10111000, B=8'00010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][78]$14704:
|
|
Old ports: A=8'11011110, B=8'01011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$a$14396
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$a$14396 [7]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$a$14396 [6:0] = 7'1011110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][79]$14707:
|
|
Old ports: A=8'00001011, B=8'11011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [4] 5'01011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][7]$14491:
|
|
Old ports: A=8'10101011, B=8'01110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][80]$14710:
|
|
Old ports: A=8'11100000, B=8'00110010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][81]$14713:
|
|
Old ports: A=8'00111010, B=8'00001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [3:0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [4] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][82]$14716:
|
|
Old ports: A=8'01001001, B=8'00000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][83]$14719:
|
|
Old ports: A=8'00100100, B=8'01011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [2:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][84]$14722:
|
|
Old ports: A=8'11000010, B=8'11010011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405 [7:1] = { 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405 [0] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][85]$14725:
|
|
Old ports: A=8'10101100, B=8'01100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [2:1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][86]$14728:
|
|
Old ports: A=8'10010001, B=8'10010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408 [1:0] } = 7'1001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][87]$14731:
|
|
Old ports: A=8'11100100, B=8'01111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [2] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][88]$14734:
|
|
Old ports: A=8'11100111, B=8'11001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][89]$14737:
|
|
Old ports: A=8'00110111, B=8'01101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][8]$14494:
|
|
Old ports: A=8'11001010, B=8'10000010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291 [3] 5'00010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][90]$14740:
|
|
Old ports: A=8'10001101, B=8'11010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][91]$14743:
|
|
Old ports: A=8'01001110, B=8'10101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][92]$14746:
|
|
Old ports: A=8'01101100, B=8'01010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][93]$14749:
|
|
Old ports: A=8'11110100, B=8'11101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [0] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [2:1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][94]$14752:
|
|
Old ports: A=8'01100101, B=8'01111010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$a$14420
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$a$14420 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$a$14420 [7:2] = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$a$14420 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$a$14420 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][95]$14755:
|
|
Old ports: A=8'10101110, B=8'00001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [1] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][47]$b$14421 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][96]$14758:
|
|
Old ports: A=8'10111010, B=8'01111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [1] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][97]$14761:
|
|
Old ports: A=8'00100101, B=8'00101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424 [7:2] = { 4'0010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][98]$14764:
|
|
Old ports: A=8'00011100, B=8'10100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][99]$14767:
|
|
Old ports: A=8'10110100, B=8'11000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [4] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][7][9]$14497:
|
|
Old ports: A=8'11001001, B=8'01111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][0]$15235:
|
|
Old ports: A=8'01100011, B=8'01111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][100]$15535:
|
|
Old ports: A=8'11101000, B=8'11011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [4:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][101]$15538:
|
|
Old ports: A=8'01110100, B=8'00011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [4:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][102]$15541:
|
|
Old ports: A=8'01001011, B=8'10111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][103]$15544:
|
|
Old ports: A=8'10001011, B=8'10001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$b$15198
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$b$15198 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$b$15198 [7:1] = 7'1000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][104]$15547:
|
|
Old ports: A=8'01110000, B=8'00111110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [0] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][105]$15550:
|
|
Old ports: A=8'10110101, B=8'01100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][106]$15553:
|
|
Old ports: A=8'01001000, B=8'00000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [3] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][107]$15556:
|
|
Old ports: A=8'11110110, B=8'00001110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][108]$15559:
|
|
Old ports: A=8'01100001, B=8'00110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [1:0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][109]$15562:
|
|
Old ports: A=8'01010111, B=8'10111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][10]$15265:
|
|
Old ports: A=8'11111010, B=8'01011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [1] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][110]$15565:
|
|
Old ports: A=8'10000110, B=8'11000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [7:2] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [0] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][111]$15568:
|
|
Old ports: A=8'00011101, B=8'10011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210 [1] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][112]$15571:
|
|
Old ports: A=8'11100001, B=8'11111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [2:1] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [3] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][113]$15574:
|
|
Old ports: A=8'10011000, B=8'00010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [3] 5'00100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][114]$15577:
|
|
Old ports: A=8'01101001, B=8'11011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [4] 5'11001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][115]$15580:
|
|
Old ports: A=8'10001110, B=8'10010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [0] } = { 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][116]$15583:
|
|
Old ports: A=8'10011011, B=8'00011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][117]$15586:
|
|
Old ports: A=8'10000111, B=8'11101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][118]$15589:
|
|
Old ports: A=8'11001110, B=8'01010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][119]$15592:
|
|
Old ports: A=8'00101000, B=8'11011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][11]$15268:
|
|
Old ports: A=8'01000111, B=8'11110000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][120]$15595:
|
|
Old ports: A=8'10001100, B=8'10100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][121]$15598:
|
|
Old ports: A=8'10001001, B=8'00001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [1:0] } = 6'000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][122]$15601:
|
|
Old ports: A=8'10111111, B=8'11100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [5:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][123]$15604:
|
|
Old ports: A=8'01000010, B=8'01101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][124]$15607:
|
|
Old ports: A=8'01000001, B=8'10011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][125]$15610:
|
|
Old ports: A=8'00101101, B=8'00001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [0] } = 6'000111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][126]$15613:
|
|
Old ports: A=8'10110000, B=8'01010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [2] 4'1000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][127]$15616:
|
|
Old ports: A=8'10111011, B=8'00010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][12]$15271:
|
|
Old ports: A=8'10101101, B=8'11010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][13]$15274:
|
|
Old ports: A=8'10100010, B=8'10101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [7:1] = { 4'1010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][14]$15277:
|
|
Old ports: A=8'10011100, B=8'10100100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [2:0] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][15]$15280:
|
|
Old ports: A=8'01110010, B=8'11000000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][16]$15283:
|
|
Old ports: A=8'10110111, B=8'11111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][17]$15286:
|
|
Old ports: A=8'10010011, B=8'00100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][18]$15289:
|
|
Old ports: A=8'00110110, B=8'00111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071 [7:1] = { 4'0011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][19]$15292:
|
|
Old ports: A=8'11110111, B=8'11001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][1]$15238:
|
|
Old ports: A=8'01110111, B=8'01111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045 [1:0] } = 6'011111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][20]$15295:
|
|
Old ports: A=8'00110100, B=8'10100101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [0] 5'01010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][21]$15298:
|
|
Old ports: A=8'11100101, B=8'11110001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [1:0] } = 6'111001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][22]$15301:
|
|
Old ports: A=8'01110001, B=8'11011000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][23]$15304:
|
|
Old ports: A=8'00110001, B=8'00010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [1:0] } = 6'001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][24]$15307:
|
|
Old ports: A=8'00000100, B=8'11000111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0] 4'0001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][25]$15310:
|
|
Old ports: A=8'00100011, B=8'11000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081 [4:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081 [6] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][26]$15313:
|
|
Old ports: A=8'00011000, B=8'10010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [1] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][27]$15316:
|
|
Old ports: A=8'00000101, B=8'10011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][28]$15319:
|
|
Old ports: A=8'00000111, B=8'00010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [3:1] } = { 4'0000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][29]$15322:
|
|
Old ports: A=8'10000000, B=8'11100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [1] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][2]$15241:
|
|
Old ports: A=8'11110010, B=8'01101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][30]$15325:
|
|
Old ports: A=8'11101011, B=8'00100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][31]$15328:
|
|
Old ports: A=8'10110010, B=8'01110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [1:0] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][32]$15331:
|
|
Old ports: A=8'00001001, B=8'10000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [1] 5'00001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][33]$15334:
|
|
Old ports: A=8'00101100, B=8'00011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [2:1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][34]$15337:
|
|
Old ports: A=8'00011011, B=8'01101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][35]$15340:
|
|
Old ports: A=8'01011010, B=8'10100000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][36]$15343:
|
|
Old ports: A=8'01010010, B=8'00111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [5:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][37]$15346:
|
|
Old ports: A=8'11010110, B=8'10110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][38]$15349:
|
|
Old ports: A=8'00101001, B=8'11100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][39]$15352:
|
|
Old ports: A=8'00101111, B=8'10000100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [6:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][3]$15244:
|
|
Old ports: A=8'01101111, B=8'11000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][40]$15355:
|
|
Old ports: A=8'01010011, B=8'11010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [0] } = 6'101001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][41]$15358:
|
|
Old ports: A=8'00000000, B=8'11101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][42]$15361:
|
|
Old ports: A=8'00100000, B=8'11111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][43]$15364:
|
|
Old ports: A=8'10110001, B=8'01011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][44]$15367:
|
|
Old ports: A=8'01101010, B=8'11001011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [0] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][45]$15370:
|
|
Old ports: A=8'10111110, B=8'00111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1] 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][46]$15373:
|
|
Old ports: A=8'01001010, B=8'01001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113 [0] } = 6'010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][47]$15376:
|
|
Old ports: A=8'01011000, B=8'11001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] 3'101 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][48]$15379:
|
|
Old ports: A=8'11010000, B=8'11101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [3:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][49]$15382:
|
|
Old ports: A=8'10101010, B=8'11111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [7:1] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][4]$15247:
|
|
Old ports: A=8'00110000, B=8'00000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [3:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [4] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][50]$15385:
|
|
Old ports: A=8'01000011, B=8'01001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [0] } = { 4'0100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][51]$15388:
|
|
Old ports: A=8'00110011, B=8'10000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][52]$15391:
|
|
Old ports: A=8'01000101, B=8'11111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][53]$15394:
|
|
Old ports: A=8'00000010, B=8'01111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [7:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][54]$15397:
|
|
Old ports: A=8'01010000, B=8'00111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][55]$15400:
|
|
Old ports: A=8'10011111, B=8'10101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [4:1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][56]$15403:
|
|
Old ports: A=8'01010001, B=8'10100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][57]$15406:
|
|
Old ports: A=8'01000000, B=8'10001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [5:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][58]$15409:
|
|
Old ports: A=8'10010010, B=8'10011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [7:2] = { 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][59]$15412:
|
|
Old ports: A=8'00111000, B=8'11110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][5]$15250:
|
|
Old ports: A=8'01100111, B=8'00101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051 [2] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][60]$15415:
|
|
Old ports: A=8'10111100, B=8'10110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [0] } = 6'101110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][61]$15418:
|
|
Old ports: A=8'11011010, B=8'00100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][62]$15421:
|
|
Old ports: A=8'00010000, B=8'11111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][63]$15424:
|
|
Old ports: A=8'11110011, B=8'11010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138 [7:1] = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138 [0] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][64]$15427:
|
|
Old ports: A=8'11001101, B=8'00001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [0] 5'00110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][65]$15430:
|
|
Old ports: A=8'00010011, B=8'11101100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][66]$15433:
|
|
Old ports: A=8'01011111, B=8'10010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [3] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][67]$15436:
|
|
Old ports: A=8'01000100, B=8'00010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [5:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][68]$15439:
|
|
Old ports: A=8'11000100, B=8'10100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [5:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][69]$15442:
|
|
Old ports: A=8'01111110, B=8'00111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147 [1] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][6]$15253:
|
|
Old ports: A=8'11111110, B=8'11010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][70]$15445:
|
|
Old ports: A=8'01100100, B=8'01011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][71]$15448:
|
|
Old ports: A=8'00011001, B=8'01110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][72]$15451:
|
|
Old ports: A=8'01100000, B=8'10000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [5] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][73]$15454:
|
|
Old ports: A=8'01001111, B=8'11011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [4] 4'1011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][74]$15457:
|
|
Old ports: A=8'00100010, B=8'00101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155 [2:0] } = 7'0010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][75]$15460:
|
|
Old ports: A=8'10010000, B=8'10001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156 [2:0] } = 6'100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][76]$15463:
|
|
Old ports: A=8'01000110, B=8'11101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [3] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][77]$15466:
|
|
Old ports: A=8'10111000, B=8'00010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][78]$15469:
|
|
Old ports: A=8'11011110, B=8'01011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$a$15161
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$a$15161 [7]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$a$15161 [6:0] = 7'1011110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][79]$15472:
|
|
Old ports: A=8'00001011, B=8'11011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [4] 5'01011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][7]$15256:
|
|
Old ports: A=8'10101011, B=8'01110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][80]$15475:
|
|
Old ports: A=8'11100000, B=8'00110010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][81]$15478:
|
|
Old ports: A=8'00111010, B=8'00001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [3:0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [4] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][82]$15481:
|
|
Old ports: A=8'01001001, B=8'00000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][83]$15484:
|
|
Old ports: A=8'00100100, B=8'01011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [2:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][84]$15487:
|
|
Old ports: A=8'11000010, B=8'11010011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170 [7:1] = { 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170 [0] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][85]$15490:
|
|
Old ports: A=8'10101100, B=8'01100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [2:1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][86]$15493:
|
|
Old ports: A=8'10010001, B=8'10010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173 [1:0] } = 7'1001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][87]$15496:
|
|
Old ports: A=8'11100100, B=8'01111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [2] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][88]$15499:
|
|
Old ports: A=8'11100111, B=8'11001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][89]$15502:
|
|
Old ports: A=8'00110111, B=8'01101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][8]$15259:
|
|
Old ports: A=8'11001010, B=8'10000010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056 [3] 5'00010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][90]$15505:
|
|
Old ports: A=8'10001101, B=8'11010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][91]$15508:
|
|
Old ports: A=8'01001110, B=8'10101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][92]$15511:
|
|
Old ports: A=8'01101100, B=8'01010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][93]$15514:
|
|
Old ports: A=8'11110100, B=8'11101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [0] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [2:1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][94]$15517:
|
|
Old ports: A=8'01100101, B=8'01111010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$a$15185
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$a$15185 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$a$15185 [7:2] = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$a$15185 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$a$15185 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][95]$15520:
|
|
Old ports: A=8'10101110, B=8'00001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [1] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][47]$b$15186 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][96]$15523:
|
|
Old ports: A=8'10111010, B=8'01111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [1] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][97]$15526:
|
|
Old ports: A=8'00100101, B=8'00101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189 [7:2] = { 4'0010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][98]$15529:
|
|
Old ports: A=8'00011100, B=8'10100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][99]$15532:
|
|
Old ports: A=8'10110100, B=8'11000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [4] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][7][9]$15262:
|
|
Old ports: A=8'11001001, B=8'01111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][0]$16000:
|
|
Old ports: A=8'01100011, B=8'01111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][100]$16300:
|
|
Old ports: A=8'11101000, B=8'11011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [4:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][101]$16303:
|
|
Old ports: A=8'01110100, B=8'00011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [4:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][102]$16306:
|
|
Old ports: A=8'01001011, B=8'10111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][103]$16309:
|
|
Old ports: A=8'10001011, B=8'10001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$b$15963
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$b$15963 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$b$15963 [7:1] = 7'1000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][104]$16312:
|
|
Old ports: A=8'01110000, B=8'00111110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [0] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][105]$16315:
|
|
Old ports: A=8'10110101, B=8'01100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][106]$16318:
|
|
Old ports: A=8'01001000, B=8'00000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [3] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][107]$16321:
|
|
Old ports: A=8'11110110, B=8'00001110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][108]$16324:
|
|
Old ports: A=8'01100001, B=8'00110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [1:0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][109]$16327:
|
|
Old ports: A=8'01010111, B=8'10111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][10]$16030:
|
|
Old ports: A=8'11111010, B=8'01011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [1] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][110]$16330:
|
|
Old ports: A=8'10000110, B=8'11000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [7:2] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [0] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][111]$16333:
|
|
Old ports: A=8'00011101, B=8'10011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975 [1] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][112]$16336:
|
|
Old ports: A=8'11100001, B=8'11111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [2:1] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [3] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][113]$16339:
|
|
Old ports: A=8'10011000, B=8'00010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [3] 5'00100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][114]$16342:
|
|
Old ports: A=8'01101001, B=8'11011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [4] 5'11001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][115]$16345:
|
|
Old ports: A=8'10001110, B=8'10010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [0] } = { 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][116]$16348:
|
|
Old ports: A=8'10011011, B=8'00011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][117]$16351:
|
|
Old ports: A=8'10000111, B=8'11101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][118]$16354:
|
|
Old ports: A=8'11001110, B=8'01010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][119]$16357:
|
|
Old ports: A=8'00101000, B=8'11011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][11]$16033:
|
|
Old ports: A=8'01000111, B=8'11110000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][120]$16360:
|
|
Old ports: A=8'10001100, B=8'10100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][121]$16363:
|
|
Old ports: A=8'10001001, B=8'00001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [1:0] } = 6'000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][122]$16366:
|
|
Old ports: A=8'10111111, B=8'11100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [5:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][123]$16369:
|
|
Old ports: A=8'01000010, B=8'01101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][124]$16372:
|
|
Old ports: A=8'01000001, B=8'10011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][125]$16375:
|
|
Old ports: A=8'00101101, B=8'00001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [0] } = 6'000111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][126]$16378:
|
|
Old ports: A=8'10110000, B=8'01010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [2] 4'1000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][127]$16381:
|
|
Old ports: A=8'10111011, B=8'00010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][12]$16036:
|
|
Old ports: A=8'10101101, B=8'11010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][13]$16039:
|
|
Old ports: A=8'10100010, B=8'10101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [7:1] = { 4'1010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][14]$16042:
|
|
Old ports: A=8'10011100, B=8'10100100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [2:0] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][15]$16045:
|
|
Old ports: A=8'01110010, B=8'11000000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][16]$16048:
|
|
Old ports: A=8'10110111, B=8'11111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][17]$16051:
|
|
Old ports: A=8'10010011, B=8'00100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][18]$16054:
|
|
Old ports: A=8'00110110, B=8'00111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836 [7:1] = { 4'0011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][19]$16057:
|
|
Old ports: A=8'11110111, B=8'11001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][1]$16003:
|
|
Old ports: A=8'01110111, B=8'01111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810 [1:0] } = 6'011111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][20]$16060:
|
|
Old ports: A=8'00110100, B=8'10100101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [0] 5'01010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][21]$16063:
|
|
Old ports: A=8'11100101, B=8'11110001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [1:0] } = 6'111001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][22]$16066:
|
|
Old ports: A=8'01110001, B=8'11011000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][23]$16069:
|
|
Old ports: A=8'00110001, B=8'00010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [1:0] } = 6'001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][24]$16072:
|
|
Old ports: A=8'00000100, B=8'11000111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0] 4'0001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][25]$16075:
|
|
Old ports: A=8'00100011, B=8'11000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846 [4:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846 [6] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][26]$16078:
|
|
Old ports: A=8'00011000, B=8'10010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [1] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][27]$16081:
|
|
Old ports: A=8'00000101, B=8'10011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][28]$16084:
|
|
Old ports: A=8'00000111, B=8'00010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [3:1] } = { 4'0000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][29]$16087:
|
|
Old ports: A=8'10000000, B=8'11100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [1] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][2]$16006:
|
|
Old ports: A=8'11110010, B=8'01101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][30]$16090:
|
|
Old ports: A=8'11101011, B=8'00100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][31]$16093:
|
|
Old ports: A=8'10110010, B=8'01110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [1:0] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][32]$16096:
|
|
Old ports: A=8'00001001, B=8'10000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [1] 5'00001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][33]$16099:
|
|
Old ports: A=8'00101100, B=8'00011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [2:1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][34]$16102:
|
|
Old ports: A=8'00011011, B=8'01101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][35]$16105:
|
|
Old ports: A=8'01011010, B=8'10100000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][36]$16108:
|
|
Old ports: A=8'01010010, B=8'00111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [5:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][37]$16111:
|
|
Old ports: A=8'11010110, B=8'10110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][38]$16114:
|
|
Old ports: A=8'00101001, B=8'11100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][39]$16117:
|
|
Old ports: A=8'00101111, B=8'10000100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [6:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][3]$16009:
|
|
Old ports: A=8'01101111, B=8'11000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][40]$16120:
|
|
Old ports: A=8'01010011, B=8'11010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [0] } = 6'101001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][41]$16123:
|
|
Old ports: A=8'00000000, B=8'11101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][42]$16126:
|
|
Old ports: A=8'00100000, B=8'11111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][43]$16129:
|
|
Old ports: A=8'10110001, B=8'01011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][44]$16132:
|
|
Old ports: A=8'01101010, B=8'11001011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [0] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][45]$16135:
|
|
Old ports: A=8'10111110, B=8'00111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1] 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][46]$16138:
|
|
Old ports: A=8'01001010, B=8'01001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878 [0] } = 6'010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][47]$16141:
|
|
Old ports: A=8'01011000, B=8'11001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] 3'101 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][48]$16144:
|
|
Old ports: A=8'11010000, B=8'11101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [3:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][49]$16147:
|
|
Old ports: A=8'10101010, B=8'11111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [7:1] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][4]$16012:
|
|
Old ports: A=8'00110000, B=8'00000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [3:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [4] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][50]$16150:
|
|
Old ports: A=8'01000011, B=8'01001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [0] } = { 4'0100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][51]$16153:
|
|
Old ports: A=8'00110011, B=8'10000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][52]$16156:
|
|
Old ports: A=8'01000101, B=8'11111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][53]$16159:
|
|
Old ports: A=8'00000010, B=8'01111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [7:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][54]$16162:
|
|
Old ports: A=8'01010000, B=8'00111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][55]$16165:
|
|
Old ports: A=8'10011111, B=8'10101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [4:1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][56]$16168:
|
|
Old ports: A=8'01010001, B=8'10100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][57]$16171:
|
|
Old ports: A=8'01000000, B=8'10001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [5:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][58]$16174:
|
|
Old ports: A=8'10010010, B=8'10011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [7:2] = { 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][59]$16177:
|
|
Old ports: A=8'00111000, B=8'11110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][5]$16015:
|
|
Old ports: A=8'01100111, B=8'00101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816 [2] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][60]$16180:
|
|
Old ports: A=8'10111100, B=8'10110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [0] } = 6'101110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][61]$16183:
|
|
Old ports: A=8'11011010, B=8'00100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][62]$16186:
|
|
Old ports: A=8'00010000, B=8'11111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][63]$16189:
|
|
Old ports: A=8'11110011, B=8'11010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903 [7:1] = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903 [0] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][64]$16192:
|
|
Old ports: A=8'11001101, B=8'00001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [0] 5'00110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][65]$16195:
|
|
Old ports: A=8'00010011, B=8'11101100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][66]$16198:
|
|
Old ports: A=8'01011111, B=8'10010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [3] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][67]$16201:
|
|
Old ports: A=8'01000100, B=8'00010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [5:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][68]$16204:
|
|
Old ports: A=8'11000100, B=8'10100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [5:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][69]$16207:
|
|
Old ports: A=8'01111110, B=8'00111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912 [1] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][6]$16018:
|
|
Old ports: A=8'11111110, B=8'11010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][70]$16210:
|
|
Old ports: A=8'01100100, B=8'01011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][71]$16213:
|
|
Old ports: A=8'00011001, B=8'01110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][72]$16216:
|
|
Old ports: A=8'01100000, B=8'10000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [5] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][73]$16219:
|
|
Old ports: A=8'01001111, B=8'11011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [4] 4'1011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][74]$16222:
|
|
Old ports: A=8'00100010, B=8'00101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920 [2:0] } = 7'0010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][75]$16225:
|
|
Old ports: A=8'10010000, B=8'10001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921 [2:0] } = 6'100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][76]$16228:
|
|
Old ports: A=8'01000110, B=8'11101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [3] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][77]$16231:
|
|
Old ports: A=8'10111000, B=8'00010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][78]$16234:
|
|
Old ports: A=8'11011110, B=8'01011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$a$15926
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$a$15926 [7]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$a$15926 [6:0] = 7'1011110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][79]$16237:
|
|
Old ports: A=8'00001011, B=8'11011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [4] 5'01011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][7]$16021:
|
|
Old ports: A=8'10101011, B=8'01110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][80]$16240:
|
|
Old ports: A=8'11100000, B=8'00110010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][81]$16243:
|
|
Old ports: A=8'00111010, B=8'00001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [3:0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [4] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][82]$16246:
|
|
Old ports: A=8'01001001, B=8'00000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][83]$16249:
|
|
Old ports: A=8'00100100, B=8'01011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [2:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][84]$16252:
|
|
Old ports: A=8'11000010, B=8'11010011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935 [7:1] = { 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935 [0] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][85]$16255:
|
|
Old ports: A=8'10101100, B=8'01100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [2:1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][86]$16258:
|
|
Old ports: A=8'10010001, B=8'10010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938 [1:0] } = 7'1001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][87]$16261:
|
|
Old ports: A=8'11100100, B=8'01111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [2] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][88]$16264:
|
|
Old ports: A=8'11100111, B=8'11001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][89]$16267:
|
|
Old ports: A=8'00110111, B=8'01101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][8]$16024:
|
|
Old ports: A=8'11001010, B=8'10000010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821 [3] 5'00010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][90]$16270:
|
|
Old ports: A=8'10001101, B=8'11010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][91]$16273:
|
|
Old ports: A=8'01001110, B=8'10101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][92]$16276:
|
|
Old ports: A=8'01101100, B=8'01010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][93]$16279:
|
|
Old ports: A=8'11110100, B=8'11101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [0] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [2:1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][94]$16282:
|
|
Old ports: A=8'01100101, B=8'01111010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$a$15950
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$a$15950 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$a$15950 [7:2] = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$a$15950 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$a$15950 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][95]$16285:
|
|
Old ports: A=8'10101110, B=8'00001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [1] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][47]$b$15951 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][96]$16288:
|
|
Old ports: A=8'10111010, B=8'01111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [1] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][97]$16291:
|
|
Old ports: A=8'00100101, B=8'00101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954 [7:2] = { 4'0010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][98]$16294:
|
|
Old ports: A=8'00011100, B=8'10100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][99]$16297:
|
|
Old ports: A=8'10110100, B=8'11000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [4] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][7][9]$16027:
|
|
Old ports: A=8'11001001, B=8'01111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [2] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][0]$16765:
|
|
Old ports: A=8'01100011, B=8'01111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][100]$17065:
|
|
Old ports: A=8'11101000, B=8'11011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [4:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][101]$17068:
|
|
Old ports: A=8'01110100, B=8'00011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [4:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][102]$17071:
|
|
Old ports: A=8'01001011, B=8'10111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][103]$17074:
|
|
Old ports: A=8'10001011, B=8'10001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$b$16728
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$b$16728 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$b$16728 [7:1] = 7'1000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][104]$17077:
|
|
Old ports: A=8'01110000, B=8'00111110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [0] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][105]$17080:
|
|
Old ports: A=8'10110101, B=8'01100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][106]$17083:
|
|
Old ports: A=8'01001000, B=8'00000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [3] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][107]$17086:
|
|
Old ports: A=8'11110110, B=8'00001110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][108]$17089:
|
|
Old ports: A=8'01100001, B=8'00110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [1:0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [2] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][109]$17092:
|
|
Old ports: A=8'01010111, B=8'10111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][10]$16795:
|
|
Old ports: A=8'11111010, B=8'01011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [1] 3'110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][110]$17095:
|
|
Old ports: A=8'10000110, B=8'11000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [7:2] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [0] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][111]$17098:
|
|
Old ports: A=8'00011101, B=8'10011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740 [1] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][112]$17101:
|
|
Old ports: A=8'11100001, B=8'11111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [2:1] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [3] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][113]$17104:
|
|
Old ports: A=8'10011000, B=8'00010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [3] 5'00100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][114]$17107:
|
|
Old ports: A=8'01101001, B=8'11011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [5:4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [4] 5'11001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][115]$17110:
|
|
Old ports: A=8'10001110, B=8'10010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [0] } = { 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][116]$17113:
|
|
Old ports: A=8'10011011, B=8'00011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [0] 5'00111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][117]$17116:
|
|
Old ports: A=8'10000111, B=8'11101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][118]$17119:
|
|
Old ports: A=8'11001110, B=8'01010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][119]$17122:
|
|
Old ports: A=8'00101000, B=8'11011111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][11]$16798:
|
|
Old ports: A=8'01000111, B=8'11110000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][120]$17125:
|
|
Old ports: A=8'10001100, B=8'10100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][121]$17128:
|
|
Old ports: A=8'10001001, B=8'00001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [1:0] } = 6'000101
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][122]$17131:
|
|
Old ports: A=8'10111111, B=8'11100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [5:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][123]$17134:
|
|
Old ports: A=8'01000010, B=8'01101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][124]$17137:
|
|
Old ports: A=8'01000001, B=8'10011001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [3] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][125]$17140:
|
|
Old ports: A=8'00101101, B=8'00001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [0] } = 6'000111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][126]$17143:
|
|
Old ports: A=8'10110000, B=8'01010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [2] 4'1000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][127]$17146:
|
|
Old ports: A=8'10111011, B=8'00010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][12]$16801:
|
|
Old ports: A=8'10101101, B=8'11010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [3:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][13]$16804:
|
|
Old ports: A=8'10100010, B=8'10101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [7:1] = { 4'1010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][14]$16807:
|
|
Old ports: A=8'10011100, B=8'10100100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [2:0] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][15]$16810:
|
|
Old ports: A=8'01110010, B=8'11000000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][16]$16813:
|
|
Old ports: A=8'10110111, B=8'11111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [3] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][17]$16816:
|
|
Old ports: A=8'10010011, B=8'00100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][18]$16819:
|
|
Old ports: A=8'00110110, B=8'00111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601 [7:1] = { 4'0011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][19]$16822:
|
|
Old ports: A=8'11110111, B=8'11001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][1]$16768:
|
|
Old ports: A=8'01110111, B=8'01111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575 [1:0] } = 6'011111
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][20]$16825:
|
|
Old ports: A=8'00110100, B=8'10100101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [0] 5'01010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][21]$16828:
|
|
Old ports: A=8'11100101, B=8'11110001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [1:0] } = 6'111001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][22]$16831:
|
|
Old ports: A=8'01110001, B=8'11011000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][23]$16834:
|
|
Old ports: A=8'00110001, B=8'00010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [1:0] } = 6'001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][24]$16837:
|
|
Old ports: A=8'00000100, B=8'11000111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0] 4'0001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][25]$16840:
|
|
Old ports: A=8'00100011, B=8'11000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611 [6:5]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611 [4:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611 [6] 5'00011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][26]$16843:
|
|
Old ports: A=8'00011000, B=8'10010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [1] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][27]$16846:
|
|
Old ports: A=8'00000101, B=8'10011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][28]$16849:
|
|
Old ports: A=8'00000111, B=8'00010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [3:1] } = { 4'0000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][29]$16852:
|
|
Old ports: A=8'10000000, B=8'11100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [1] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][2]$16771:
|
|
Old ports: A=8'11110010, B=8'01101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][30]$16855:
|
|
Old ports: A=8'11101011, B=8'00100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][31]$16858:
|
|
Old ports: A=8'10110010, B=8'01110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [1:0] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][32]$16861:
|
|
Old ports: A=8'00001001, B=8'10000011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [1] 5'00001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][33]$16864:
|
|
Old ports: A=8'00101100, B=8'00011010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [2:1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][34]$16867:
|
|
Old ports: A=8'00011011, B=8'01101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][35]$16870:
|
|
Old ports: A=8'01011010, B=8'10100000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][36]$16873:
|
|
Old ports: A=8'01010010, B=8'00111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [5:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][37]$16876:
|
|
Old ports: A=8'11010110, B=8'10110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][38]$16879:
|
|
Old ports: A=8'00101001, B=8'11100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][39]$16882:
|
|
Old ports: A=8'00101111, B=8'10000100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [6:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][3]$16774:
|
|
Old ports: A=8'01101111, B=8'11000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][40]$16885:
|
|
Old ports: A=8'01010011, B=8'11010001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [6:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [0] } = 6'101001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][41]$16888:
|
|
Old ports: A=8'00000000, B=8'11101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][42]$16891:
|
|
Old ports: A=8'00100000, B=8'11111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][43]$16894:
|
|
Old ports: A=8'10110001, B=8'01011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][44]$16897:
|
|
Old ports: A=8'01101010, B=8'11001011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [0] 5'10101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][45]$16900:
|
|
Old ports: A=8'10111110, B=8'00111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1] 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][46]$16903:
|
|
Old ports: A=8'01001010, B=8'01001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643 [0] } = 6'010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][47]$16906:
|
|
Old ports: A=8'01011000, B=8'11001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] 3'101 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][48]$16909:
|
|
Old ports: A=8'11010000, B=8'11101111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [3:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][49]$16912:
|
|
Old ports: A=8'10101010, B=8'11111011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [7:1] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][4]$16777:
|
|
Old ports: A=8'00110000, B=8'00000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [3:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [4] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][50]$16915:
|
|
Old ports: A=8'01000011, B=8'01001101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [0] } = { 4'0100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][51]$16918:
|
|
Old ports: A=8'00110011, B=8'10000101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][52]$16921:
|
|
Old ports: A=8'01000101, B=8'11111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][53]$16924:
|
|
Old ports: A=8'00000010, B=8'01111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [7:1] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][54]$16927:
|
|
Old ports: A=8'01010000, B=8'00111100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][55]$16930:
|
|
Old ports: A=8'10011111, B=8'10101000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [4:1] } = { 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][56]$16933:
|
|
Old ports: A=8'01010001, B=8'10100011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [1] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][57]$16936:
|
|
Old ports: A=8'01000000, B=8'10001111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [5:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][58]$16939:
|
|
Old ports: A=8'10010010, B=8'10011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [7:2] = { 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][59]$16942:
|
|
Old ports: A=8'00111000, B=8'11110101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][5]$16780:
|
|
Old ports: A=8'01100111, B=8'00101011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581 [1:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581 [2] 4'1011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][60]$16945:
|
|
Old ports: A=8'10111100, B=8'10110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [0] } = 6'101110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][61]$16948:
|
|
Old ports: A=8'11011010, B=8'00100001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][62]$16951:
|
|
Old ports: A=8'00010000, B=8'11111111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][63]$16954:
|
|
Old ports: A=8'11110011, B=8'11010010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668 [7:1] = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668 [0] 4'1001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][64]$16957:
|
|
Old ports: A=8'11001101, B=8'00001100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [7:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [0] 5'00110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][65]$16960:
|
|
Old ports: A=8'00010011, B=8'11101100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][66]$16963:
|
|
Old ports: A=8'01011111, B=8'10010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [3] 5'01111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][67]$16966:
|
|
Old ports: A=8'01000100, B=8'00010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [5:1] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][68]$16969:
|
|
Old ports: A=8'11000100, B=8'10100111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [5:1] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][69]$16972:
|
|
Old ports: A=8'01111110, B=8'00111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677 [1] 4'1111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][6]$16783:
|
|
Old ports: A=8'11111110, B=8'11010111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [3] 3'111 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][70]$16975:
|
|
Old ports: A=8'01100100, B=8'01011101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [4:1] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [0] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][71]$16978:
|
|
Old ports: A=8'00011001, B=8'01110011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][72]$16981:
|
|
Old ports: A=8'01100000, B=8'10000001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [4:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [5] 4'0000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][73]$16984:
|
|
Old ports: A=8'01001111, B=8'11011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [3:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [4] 4'1011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][74]$16987:
|
|
Old ports: A=8'00100010, B=8'00101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685 [2:0] } = 7'0010010
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][75]$16990:
|
|
Old ports: A=8'10010000, B=8'10001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686 [2:0] } = 6'100000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][76]$16993:
|
|
Old ports: A=8'01000110, B=8'11101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [2:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [3] 4'0110 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][77]$16996:
|
|
Old ports: A=8'10111000, B=8'00010100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [3:2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [1:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][78]$16999:
|
|
Old ports: A=8'11011110, B=8'01011110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$a$16691
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$a$16691 [7]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$a$16691 [6:0] = 7'1011110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][79]$17002:
|
|
Old ports: A=8'00001011, B=8'11011011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [3:0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [4] 5'01011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][7]$16786:
|
|
Old ports: A=8'10101011, B=8'01110110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][80]$17005:
|
|
Old ports: A=8'11100000, B=8'00110010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [1] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][81]$17008:
|
|
Old ports: A=8'00111010, B=8'00001010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [4]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [3:0] } = { 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [4] 4'1010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][82]$17011:
|
|
Old ports: A=8'01001001, B=8'00000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [7:2] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [0] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][83]$17014:
|
|
Old ports: A=8'00100100, B=8'01011100, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [2:0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [3] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][84]$17017:
|
|
Old ports: A=8'11000010, B=8'11010011, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700 [0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700 [7:1] = { 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700 [0] 3'001 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][85]$17020:
|
|
Old ports: A=8'10101100, B=8'01100010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [2:1] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [2] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][86]$17023:
|
|
Old ports: A=8'10010001, B=8'10010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703
|
|
New ports: A=1'0, B=1'1, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703 [2]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703 [1:0] } = 7'1001001
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][87]$17026:
|
|
Old ports: A=8'11100100, B=8'01111001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [2] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][88]$17029:
|
|
Old ports: A=8'11100111, B=8'11001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [2:1] } = { 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][89]$17032:
|
|
Old ports: A=8'00110111, B=8'01101101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][8]$16789:
|
|
Old ports: A=8'11001010, B=8'10000010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586 [3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586 [3] 5'00010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][90]$17035:
|
|
Old ports: A=8'10001101, B=8'11010101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [4:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [2:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [4] 4'0101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][91]$17038:
|
|
Old ports: A=8'01001110, B=8'10101001, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [7:2] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][92]$17041:
|
|
Old ports: A=8'01101100, B=8'01010110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [0] } = { 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [1] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][93]$17044:
|
|
Old ports: A=8'11110100, B=8'11101010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713
|
|
New ports: A=2'10, B=2'01, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [2:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [0] } = { 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [2:1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][94]$17047:
|
|
Old ports: A=8'01100101, B=8'01111010, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$a$16715
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$a$16715 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$a$16715 [7:2] = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$a$16715 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$a$16715 [1:0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][95]$17050:
|
|
Old ports: A=8'10101110, B=8'00001000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716
|
|
New ports: A=1'1, B=1'0, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [1] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][47]$b$16716 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][96]$17053:
|
|
Old ports: A=8'10111010, B=8'01111000, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718
|
|
New ports: A=2'01, B=2'10, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [5:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [1] 5'11100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][97]$17056:
|
|
Old ports: A=8'00100101, B=8'00101110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719
|
|
New ports: A=2'01, B=2'10, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719 [1:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719 [7:2] = { 4'0010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][98]$17059:
|
|
Old ports: A=8'00011100, B=8'10100110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][99]$17062:
|
|
Old ports: A=8'10110100, B=8'11000110, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [4] 3'010 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][7][9]$16792:
|
|
Old ports: A=8'11001001, B=8'01111101, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587
|
|
New ports: A=2'10, B=2'01, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [2] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [1:0] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [2] 3'101 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$11657:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$b$11659 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [1] } = { 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$11687:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$b$11689 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$11690:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$a$11691 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][11]$b$11692 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$11693:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$a$11694 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][12]$b$11695 [6:5] 2'01 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [6] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$a$11580 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$11696:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$b$11581
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$a$11697 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][13]$b$11698 [1:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$b$11581 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$b$11581 [7:5] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][6]$b$11581 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$11699:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$a$11700 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][14]$b$11701 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [3:2] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$a$11583 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$11702:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$a$11703 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [1:0] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$b$11704 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$11705:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$a$11706 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$b$11707 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [6:5] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$11708:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$a$11709 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$b$11710 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [3] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$11711:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$a$11712 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$b$11713 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$11714:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$a$11715 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][19]$b$11716 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [5:4] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$11660:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$a$11661 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][1]$b$11662 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [6:5] = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$11717:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [7] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$a$11718 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][20]$b$11719 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$a$11592 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$11720:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$b$11593
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$a$11721 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][21]$b$11722 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$b$11593 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$b$11593 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$b$11593 [6] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][10]$b$11593 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$11723:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [5] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$a$11724 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$b$11725 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$11726:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$a$11727 [2:1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][23]$b$11728 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$11729:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$a$11730 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][24]$b$11731 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [3] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$a$11598 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$11732:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$a$11733 [2:1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$b$11734 [2:1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$11735:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$a$11736 [3:2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][26]$b$11737 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [6:4] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$a$11601 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$11738:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$b$11602
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$a$11739 [2] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][27]$b$11740 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$b$11602 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$b$11602 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$b$11602 [1] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][13]$b$11602 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$11741:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$a$11742 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [6] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$b$11743 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [6:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$11744:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$a$11745 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$b$11746 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [2] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$11663:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [4] 3'000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$a$11664 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][2]$b$11665 [3:2] 2'11 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565 [7:6] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$11747:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$a$11748 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$b$11749 [1:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [7] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$11750:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$a$11751 [0] }, B={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608 [2:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608 [7:3] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608 [1:0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$b$11608 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$11753:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [0] 3'010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$a$11754 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][32]$b$11755 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [4:3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$11756:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$a$11757 [3] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [6] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][33]$b$11758 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$11759:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$a$11760 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761 [1] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$b$11761 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$11762:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [0] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$a$11763 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][35]$b$11764 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614 [4] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$b$11614 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$11765:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$a$11616
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [5] 3'000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$a$11766 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [4] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][36]$b$11767 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$a$11616 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$a$11616 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$a$11616 [3] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$a$11616 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$11768:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$a$11769 [3] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][37]$b$11770 [4:3] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [0] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][18]$b$11617 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$11771:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$a$11772 [3] 2'11 }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][38]$b$11773 [3:2] 1'0 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [4:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$a$11619 [3] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$11774:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$a$11775, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$a$11775 [7] 3'110 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][39]$b$11776 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][19]$b$11620 [4] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$11666:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$a$11667 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][3]$b$11668 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$11777:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$a$11778 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][40]$b$11779 [4] 2'11 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$a$11622 [6] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$11780:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$b$11623
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$a$11781 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][41]$b$11782 [3] 3'100 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$b$11623 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$b$11623 [7:6] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][20]$b$11623 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$11783:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625
|
|
New ports: A={ 4'1001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$a$11784 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][42]$b$11785 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [4:3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$11786:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$a$11787 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][43]$b$11788 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$11789:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$a$11790 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$b$11791 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$11792:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$b$11629
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$a$11793 [4:3] 3'101 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1:0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][45]$b$11794 [1:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$b$11629 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$b$11629 [7] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$b$11629 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$11795:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$a$11796 [1] }, B={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$b$11797 [2:1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$11801:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$a$11634
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [6] 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$a$11802 [1] 1'0 }, B={ 3'000 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][48]$b$11803 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$a$11634 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$a$11634 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$a$11634 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$11804:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$a$11805 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$b$11806 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$11669:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$a$11670 [3] 3'010 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][4]$b$11671 [2] 2'01 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568 [6:4] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$a$11568 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$11807:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$a$11808 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$b$11809 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$11810:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$b$11812, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$a$11811 [2:1] 1'1 }, B={ 4'1001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][51]$b$11812 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [5:3] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$11813:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$a$11814 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [1:0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][52]$b$11815 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640 [5] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$a$11640 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$11816:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$a$11817 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$b$11818 [4:3] 3'110 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [5] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$11819:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$a$11643
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$a$11820 [2] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][54]$b$11821 [1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$a$11643 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$a$11643 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$a$11643 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$a$11643 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$11822:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$b$11644
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$a$11823 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824 [1] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][55]$b$11824 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$b$11644 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$b$11644 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$b$11644 [5:4] = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][27]$b$11644 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$11825:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$a$11826 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [3] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][56]$b$11827 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$a$11646 [5] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$11828:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$b$11647
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$a$11829 [5:4] 4'1001 }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][57]$b$11830 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$b$11647 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$b$11647 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$b$11647 [6] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][28]$b$11647 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$11831:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$a$11649
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$a$11832 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][58]$b$11833 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$a$11649 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$a$11649 [7:6] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$a$11649 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$a$11649 [5] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$11834:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$a$11835 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$b$11836 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [4] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$11672:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$b$11569
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [1] 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$a$11673 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][5]$b$11674 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$b$11569 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$b$11569 [7:6] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][2]$b$11569 [5] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$11837:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$a$11838 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [7] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][60]$b$11839 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$a$11652 [1] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$11840:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$a$11841 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][61]$b$11842 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [4] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][30]$b$11653 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$11843:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$a$11655
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [6] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$a$11844 [3] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [5] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][62]$b$11845 [1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$a$11655 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$a$11655 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$a$11655 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$a$11655 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$11846:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$a$11847 [2] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][63]$b$11848 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [4:3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][31]$b$11656 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$11675:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [4] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$a$11676 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][6]$b$11677 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [3] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$a$11571 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$11678:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$a$11679 [3] 2'10 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$b$11680 [1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$11681:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$a$11682 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][8]$b$11683 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574 [7:4] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$a$11574 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$11684:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$a$11685 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][9]$b$11686 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][4]$b$11575 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$12934:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1:0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$a$12935 [1:0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$b$12936 [1:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [7] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$12967:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$a$12968 [3] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][11]$b$12969 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][5]$b$12855 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$12970:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$a$12971 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [1] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][12]$b$12972 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$a$12857 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$12973:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] 3'100 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$a$12974 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$b$12975 [2:1] 1'0 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [7:6] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$12976:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$a$12977 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$b$12978 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [3] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$12979:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [2] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$a$12980 [2:1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$b$12981 [2] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$12982:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$a$12983 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][16]$b$12984 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [0] } = 3'110
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$12985:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$a$12986 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [3] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][17]$b$12987 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$12988:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$a$12989 [5:4] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [7] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$b$12990 [4] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [7:3]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [2:0] = 3'100
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$12991:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$b$12867
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$a$12992 [3] 3'101 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [2] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][19]$b$12993 [2] 2'10 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$b$12867 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$b$12867 [7:6] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$b$12867 [1:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$12937:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$b$12840
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$a$12938 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][1]$b$12939 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$b$12840 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$b$12840 [7:5] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$b$12840 [0] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$12994:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$a$12995 [2] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$b$12996 [4:3] 1'0 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [5:2]
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [1:0] } = 4'0100
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$12997:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$a$12998 [4] 3'101 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999 [1] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][21]$b$12999 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [3] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$b$12870 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$13000:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$a$13001 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][22]$b$13002 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [2] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [1] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$13003:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$a$13004 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][23]$b$13005 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [2] } = { 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$13006:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$a$13007 [3] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][24]$b$13008 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$a$12875 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$13009:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$b$12876
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$a$13010 [4] 4'1100 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [3] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][25]$b$13011 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$b$12876 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$b$12876 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$b$12876 [6] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][12]$b$12876 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$13012:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$a$13013 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][26]$b$13014 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878 [7] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878 [5]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$13015:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$a$13016 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017 [0] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][27]$b$13017 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [5] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$13018:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$a$13019 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [4] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$b$13020 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [3] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$13021:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$a$13022 [0] }, B={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][29]$b$13023 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [2:1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$b$12882 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$12940:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$a$12941 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$b$12942 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [5:3] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [1:0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$13024:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [6] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$a$13025 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$b$13026 [2:1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [2:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$13027:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$a$13028 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [0] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][31]$b$13029 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$b$12885 [5] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$13030:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$a$13031 [1:0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][32]$b$13032 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [3:2] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$a$12887 [1] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$13033:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$b$12888
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$a$13034 [3] 3'111 }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][33]$b$13035 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$b$12888 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$b$12888 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][16]$b$12888 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$13036:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$b$13038, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$a$12890
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [5] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$a$13037 [0] }, B={ 5'10011 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][34]$b$13038 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$a$12890 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$a$12890 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$a$12890 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$a$12890 [1] } = 2'11
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$13039:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$a$13040 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][35]$b$13041 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][17]$b$12891 [3] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$13042:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$a$12893
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$a$13043 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][36]$b$13044 [2:1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$a$12893 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$a$12893 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$13045:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$a$13046 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][37]$b$13047 [4] 2'00 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][18]$b$12894 [1] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$13048:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$a$13049 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][38]$b$13050 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [5:4] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$a$12896 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$13051:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$b$12897
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$a$13052 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][39]$b$13053 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$b$12897 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$b$12897 [1:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][19]$b$12897 [2] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$12943:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$a$12944 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][3]$b$12945 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [3:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [0] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$b$12843 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$13054:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$a$12899
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$a$13055 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][40]$b$13056 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$a$12899 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$a$12899 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$a$12899 [6] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$a$12899 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$13057:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$a$13058 [2] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [2] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$b$13059 [3:2] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900 [7:2]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900 [1:0] = 2'01
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$13060:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$a$13061 [4:3] 2'11 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][42]$b$13062 [2] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902 [6:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$a$12902 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$13063:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$a$13064 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][43]$b$13065 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][21]$b$12903 [5] 2'01 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$13066:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$a$13067 [1] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$b$13068 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [4] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$13069:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$a$13070 [2] 2'10 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][45]$b$13071 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906 [6:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906 [3] } = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$b$12906 [1:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$13072:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073 [0] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$a$13073 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][46]$b$13074 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [5:3] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$a$12908 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$13075:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$b$12909
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$a$13076 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][47]$b$13077 [2:1] 1'0 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$b$12909 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$b$12909 [7:6] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][23]$b$12909 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$13078:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$a$12911
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [6] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$a$13079 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [3] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][48]$b$13080 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$a$12911 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$a$12911 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$a$12911 [4] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$a$12911 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$13081:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [3] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$a$13082 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][49]$b$13083 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][24]$b$12912 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$12946:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$a$12947 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][4]$b$12948 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [4] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$a$12845 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$13084:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$a$13085 [1:0] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][50]$b$13086 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$13087:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$a$13088 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][51]$b$13089 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$13090:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$a$12917
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$a$13091 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][52]$b$13092 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$a$12917 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$a$12917 [1:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$a$12917 [2] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$a$12917 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$13093:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$a$13094 [3:2] 2'01 }, B={ 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$b$13095 [1:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [7:6] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$13096:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$a$13097 [3] 2'01 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [5] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][54]$b$13098 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [2] } = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$a$12920 [1:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$13099:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$b$12921
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$a$13100 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [4] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][55]$b$13101 [0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$b$12921 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][27]$b$12921 [7] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$13102:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$a$12923
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$a$13103 [6] 4'1000 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][56]$b$13104 [2:1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$a$12923 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$a$12923 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$a$12923 [4:3] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$a$12923 [1:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$13105:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$a$13106 [2] 2'10 }, B={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [0] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$b$13107 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [0] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$13108:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [0] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$a$13109 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [0] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][58]$b$13110 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [1] } = { 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$a$12926 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$13111:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$b$12927
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$a$13112 [4] 2'01 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][59]$b$13113 [3] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$b$12927 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$b$12927 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$b$12927 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][29]$b$12927 [0] } = 2'01
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$12949:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$b$12846
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$a$12950 [2] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][5]$b$12951 [3] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$b$12846 [7:2]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][2]$b$12846 [1:0] = 2'11
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$13114:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$a$13115 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][60]$b$13116 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929 [5] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$a$12929 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$13117:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$b$12930
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$a$13118 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][61]$b$13119 [5:4] 3'010 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$b$12930 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$b$12930 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][30]$b$12930 [1] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$13120:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$a$13121 [3] 3'001 }, B={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][62]$b$13122 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [6:4] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$a$12932 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$13123:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$a$13124 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][63]$b$13125 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933 [1] } = { 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][31]$b$12933 [4] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$12952:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$a$12953 [1] 1'0 }, B={ 3'100 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][6]$b$12954 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [5] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$a$12848 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$12955:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$b$12849
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$a$12956 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [5] 3'010 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][7]$b$12957 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$b$12849 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][3]$b$12849 [7:6] = 2'11
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$12958:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$a$12959 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$b$12960 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [5:3] = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$12961:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$b$12852
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$a$12962 [2] 2'10 }, B={ 3'001 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][9]$b$12963 [2:1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$b$12852 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$b$12852 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$b$12852 [4] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$b$12852 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$13541:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542, B=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$a$13536
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [2] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$a$13542 [2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][0]$b$13543 [2:1] 1'0 }, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$a$13536 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$a$13536 [7:4] = { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$a$13536 [3] 3'000 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$13544:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545, B=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$b$13537
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$a$13545 [4:3] }, B={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][1]$b$13546 [6:5] 2'00 }, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$b$13537 [6:3]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$b$13537 [7] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][0]$b$13537 [2:0] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$13547:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548, B=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [7] 2'00 $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$a$13548 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [0] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][2][2]$b$13549 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [7:6] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [5:3] = $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [2:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$14278:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$b$14280 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$14308:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$b$14310 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$14311:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$a$14312 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][11]$b$14313 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$14314:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$a$14315 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][12]$b$14316 [6:5] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$a$14201 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$14317:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$b$14202
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$a$14318 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][13]$b$14319 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$b$14202 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$b$14202 [7:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][6]$b$14202 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$14320:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$a$14321 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][14]$b$14322 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [3:2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$a$14204 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$14323:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$a$14324 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [1:0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$b$14325 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$14326:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$a$14327 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$b$14328 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [6:5] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$14329:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$a$14330 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$b$14331 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$14332:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$a$14333 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$b$14334 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$14335:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$a$14336 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][19]$b$14337 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$14281:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$a$14282 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][1]$b$14283 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [6:5] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$14338:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$a$14339 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][20]$b$14340 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$a$14213 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$14341:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$b$14214
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$a$14342 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][21]$b$14343 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$b$14214 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$b$14214 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$b$14214 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][10]$b$14214 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$14344:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [5] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$a$14345 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$b$14346 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$14347:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$a$14348 [2:1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][23]$b$14349 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$14350:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$a$14351 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][24]$b$14352 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$a$14219 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$14353:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$a$14354 [2:1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$b$14355 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$14356:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$a$14357 [3:2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][26]$b$14358 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$a$14222 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$14359:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$b$14223
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$a$14360 [2] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][27]$b$14361 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$b$14223 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$b$14223 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$b$14223 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][13]$b$14223 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$14362:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$a$14363 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$b$14364 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$14365:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$a$14366 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$b$14367 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [2] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$14284:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [4] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$a$14285 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][2]$b$14286 [3:2] 2'11 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$14368:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$a$14369 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$b$14370 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$14371:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$a$14372 [0] }, B={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][31]$b$14373 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229 [2:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229 [7:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229 [1:0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$b$14229 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$14374:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [0] 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$a$14375 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][32]$b$14376 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$14377:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$a$14378 [3] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][33]$b$14379 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$14380:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$a$14381 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382 [1] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$b$14382 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$14383:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$a$14384 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][35]$b$14385 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235 [4] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$b$14235 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$14386:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$a$14237
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [5] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$a$14387 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][36]$b$14388 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$a$14237 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$a$14237 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$a$14237 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$a$14237 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$14389:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$a$14390 [3] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][37]$b$14391 [4:3] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][18]$b$14238 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$14392:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$a$14393 [3] 2'11 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][38]$b$14394 [3:2] 1'0 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [4:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$a$14240 [3] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$14395:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$a$14396, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$a$14396 [7] 3'110 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][39]$b$14397 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][19]$b$14241 [4] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$14287:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$a$14288 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][3]$b$14289 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$14398:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$a$14399 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][40]$b$14400 [4] 2'11 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$a$14243 [6] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$14401:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$b$14244
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$a$14402 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][41]$b$14403 [3] 3'100 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$b$14244 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$b$14244 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][20]$b$14244 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$14404:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246
|
|
New ports: A={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$a$14405 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][42]$b$14406 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$14407:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$a$14408 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][43]$b$14409 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$14410:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$a$14411 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$b$14412 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$14413:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$b$14250
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$a$14414 [4:3] 3'101 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][45]$b$14415 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$b$14250 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$b$14250 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$b$14250 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$14416:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$a$14417 [1] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$b$14418 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$14422:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$a$14255
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [6] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$a$14423 [1] 1'0 }, B={ 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][48]$b$14424 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$a$14255 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$a$14255 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$a$14255 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$14425:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$a$14426 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$b$14427 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$14290:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$a$14291 [3] 3'010 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][4]$b$14292 [2] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$a$14189 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$14428:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$a$14429 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$b$14430 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$14431:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$b$14433, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$a$14432 [2:1] 1'1 }, B={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][51]$b$14433 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [5:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$14434:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$a$14435 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][52]$b$14436 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$a$14261 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$14437:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$a$14438 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$b$14439 [4:3] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$14440:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$a$14264
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$a$14441 [2] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][54]$b$14442 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$a$14264 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$a$14264 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$a$14264 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$a$14264 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$14443:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$b$14265
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$a$14444 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][55]$b$14445 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$b$14265 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$b$14265 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$b$14265 [5:4] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][27]$b$14265 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$14446:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$a$14447 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [3] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][56]$b$14448 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$a$14267 [5] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$14449:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$b$14268
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$a$14450 [5:4] 4'1001 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][57]$b$14451 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$b$14268 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$b$14268 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$b$14268 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][28]$b$14268 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$14452:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$a$14270
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$a$14453 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][58]$b$14454 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$a$14270 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$a$14270 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$a$14270 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$a$14270 [5] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$14455:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$a$14456 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$b$14457 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$14293:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$b$14190
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [1] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$a$14294 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][5]$b$14295 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$b$14190 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$b$14190 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][2]$b$14190 [5] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$14458:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$a$14459 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [7] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][60]$b$14460 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$a$14273 [1] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$14461:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$a$14462 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][61]$b$14463 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][30]$b$14274 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$14464:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$a$14276
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$a$14465 [3] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [5] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][62]$b$14466 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$a$14276 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$a$14276 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$a$14276 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$a$14276 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$14467:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$a$14468 [2] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][63]$b$14469 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][31]$b$14277 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$14296:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$a$14297 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][6]$b$14298 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$a$14192 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$14299:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$a$14300 [3] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$b$14301 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$14302:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$a$14303 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][8]$b$14304 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195 [7:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$a$14195 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$14305:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$a$14306 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][9]$b$14307 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][4]$b$14196 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$15043:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$b$15045 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$15073:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$b$15075 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$15076:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$a$15077 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][11]$b$15078 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$15079:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$a$15080 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][12]$b$15081 [6:5] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$a$14966 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$15082:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$b$14967
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$a$15083 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][13]$b$15084 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$b$14967 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$b$14967 [7:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][6]$b$14967 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$15085:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$a$15086 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][14]$b$15087 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [3:2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$a$14969 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$15088:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$a$15089 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [1:0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$b$15090 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$15091:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$a$15092 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$b$15093 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [6:5] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$15094:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$a$15095 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$b$15096 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$15097:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$a$15098 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$b$15099 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$15100:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$a$15101 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][19]$b$15102 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$15046:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$a$15047 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][1]$b$15048 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [6:5] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$15103:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$a$15104 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][20]$b$15105 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$a$14978 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$15106:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$b$14979
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$a$15107 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][21]$b$15108 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$b$14979 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$b$14979 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$b$14979 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][10]$b$14979 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$15109:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [5] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$a$15110 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$b$15111 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$15112:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$a$15113 [2:1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][23]$b$15114 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$15115:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$a$15116 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][24]$b$15117 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$a$14984 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$15118:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$a$15119 [2:1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$b$15120 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$15121:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$a$15122 [3:2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][26]$b$15123 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$a$14987 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$15124:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$b$14988
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$a$15125 [2] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][27]$b$15126 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$b$14988 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$b$14988 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$b$14988 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][13]$b$14988 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$15127:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$a$15128 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$b$15129 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$15130:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$a$15131 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$b$15132 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [2] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$15049:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [4] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$a$15050 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][2]$b$15051 [3:2] 2'11 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$15133:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$a$15134 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$b$15135 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$15136:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$a$15137 [0] }, B={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][31]$b$15138 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994 [2:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994 [7:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994 [1:0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$b$14994 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$15139:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [0] 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$a$15140 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][32]$b$15141 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$15142:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$a$15143 [3] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][33]$b$15144 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$15145:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$a$15146 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147 [1] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$b$15147 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$15148:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$a$15149 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][35]$b$15150 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000 [4] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$b$15000 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$15151:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$a$15002
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [5] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$a$15152 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][36]$b$15153 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$a$15002 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$a$15002 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$a$15002 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$a$15002 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$15154:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$a$15155 [3] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][37]$b$15156 [4:3] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][18]$b$15003 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$15157:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$a$15158 [3] 2'11 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][38]$b$15159 [3:2] 1'0 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [4:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$a$15005 [3] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$15160:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$a$15161, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$a$15161 [7] 3'110 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][39]$b$15162 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][19]$b$15006 [4] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$15052:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$a$15053 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][3]$b$15054 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$15163:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$a$15164 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][40]$b$15165 [4] 2'11 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$a$15008 [6] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$15166:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$b$15009
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$a$15167 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][41]$b$15168 [3] 3'100 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$b$15009 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$b$15009 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][20]$b$15009 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$15169:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011
|
|
New ports: A={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$a$15170 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][42]$b$15171 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$15172:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$a$15173 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][43]$b$15174 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$15175:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$a$15176 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$b$15177 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$15178:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$b$15015
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$a$15179 [4:3] 3'101 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][45]$b$15180 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$b$15015 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$b$15015 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$b$15015 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$15181:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$a$15182 [1] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$b$15183 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$15187:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$a$15020
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [6] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$a$15188 [1] 1'0 }, B={ 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][48]$b$15189 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$a$15020 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$a$15020 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$a$15020 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$15190:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$a$15191 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$b$15192 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$15055:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$a$15056 [3] 3'010 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][4]$b$15057 [2] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$a$14954 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$15193:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$a$15194 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$b$15195 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$15196:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$b$15198, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$a$15197 [2:1] 1'1 }, B={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][51]$b$15198 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [5:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$15199:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$a$15200 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][52]$b$15201 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$a$15026 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$15202:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$a$15203 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$b$15204 [4:3] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$15205:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$a$15029
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$a$15206 [2] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][54]$b$15207 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$a$15029 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$a$15029 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$a$15029 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$a$15029 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$15208:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$b$15030
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$a$15209 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][55]$b$15210 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$b$15030 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$b$15030 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$b$15030 [5:4] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][27]$b$15030 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$15211:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$a$15212 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [3] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][56]$b$15213 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$a$15032 [5] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$15214:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$b$15033
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$a$15215 [5:4] 4'1001 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][57]$b$15216 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$b$15033 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$b$15033 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$b$15033 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][28]$b$15033 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$15217:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$a$15035
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$a$15218 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][58]$b$15219 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$a$15035 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$a$15035 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$a$15035 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$a$15035 [5] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$15220:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$a$15221 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$b$15222 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$15058:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$b$14955
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [1] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$a$15059 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][5]$b$15060 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$b$14955 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$b$14955 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][2]$b$14955 [5] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$15223:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$a$15224 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [7] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][60]$b$15225 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$a$15038 [1] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$15226:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$a$15227 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][61]$b$15228 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][30]$b$15039 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$15229:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$a$15041
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$a$15230 [3] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [5] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][62]$b$15231 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$a$15041 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$a$15041 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$a$15041 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$a$15041 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$15232:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$a$15233 [2] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][63]$b$15234 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][31]$b$15042 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$15061:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$a$15062 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][6]$b$15063 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$a$14957 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$15064:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$a$15065 [3] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$b$15066 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$15067:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$a$15068 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][8]$b$15069 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960 [7:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$a$14960 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$15070:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$a$15071 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][9]$b$15072 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][4]$b$14961 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$15808:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$b$15810 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$15838:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$b$15840 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$15841:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$a$15842 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][11]$b$15843 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$15844:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$a$15845 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][12]$b$15846 [6:5] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$a$15731 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$15847:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$b$15732
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$a$15848 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][13]$b$15849 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$b$15732 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$b$15732 [7:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][6]$b$15732 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$15850:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$a$15851 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][14]$b$15852 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [3:2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$a$15734 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$15853:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$a$15854 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [1:0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$b$15855 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$15856:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$a$15857 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$b$15858 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [6:5] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$15859:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$a$15860 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$b$15861 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$15862:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$a$15863 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$b$15864 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$15865:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$a$15866 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][19]$b$15867 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$15811:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$a$15812 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][1]$b$15813 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [6:5] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$15868:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$a$15869 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][20]$b$15870 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$a$15743 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$15871:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$b$15744
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$a$15872 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][21]$b$15873 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$b$15744 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$b$15744 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$b$15744 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][10]$b$15744 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$15874:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [5] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$a$15875 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$b$15876 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$15877:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$a$15878 [2:1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][23]$b$15879 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$15880:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$a$15881 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][24]$b$15882 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$a$15749 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$15883:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$a$15884 [2:1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$b$15885 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$15886:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$a$15887 [3:2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][26]$b$15888 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$a$15752 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$15889:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$b$15753
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$a$15890 [2] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][27]$b$15891 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$b$15753 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$b$15753 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$b$15753 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][13]$b$15753 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$15892:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$a$15893 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$b$15894 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$15895:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$a$15896 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$b$15897 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [2] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$15814:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [4] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$a$15815 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][2]$b$15816 [3:2] 2'11 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$15898:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$a$15899 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$b$15900 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$15901:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$a$15902 [0] }, B={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][31]$b$15903 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759 [2:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759 [7:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759 [1:0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$b$15759 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$15904:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [0] 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$a$15905 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][32]$b$15906 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$15907:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$a$15908 [3] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][33]$b$15909 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$15910:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$a$15911 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912 [1] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$b$15912 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$15913:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$a$15914 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][35]$b$15915 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765 [4] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$b$15765 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$15916:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$a$15767
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [5] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$a$15917 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][36]$b$15918 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$a$15767 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$a$15767 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$a$15767 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$a$15767 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$15919:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$a$15920 [3] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][37]$b$15921 [4:3] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][18]$b$15768 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$15922:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$a$15923 [3] 2'11 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][38]$b$15924 [3:2] 1'0 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [4:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$a$15770 [3] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$15925:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$a$15926, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$a$15926 [7] 3'110 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][39]$b$15927 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][19]$b$15771 [4] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$15817:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$a$15818 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][3]$b$15819 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$15928:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$a$15929 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][40]$b$15930 [4] 2'11 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$a$15773 [6] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$15931:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$b$15774
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$a$15932 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][41]$b$15933 [3] 3'100 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$b$15774 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$b$15774 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][20]$b$15774 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$15934:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776
|
|
New ports: A={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$a$15935 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][42]$b$15936 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$15937:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$a$15938 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][43]$b$15939 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$15940:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$a$15941 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$b$15942 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$15943:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$b$15780
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$a$15944 [4:3] 3'101 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][45]$b$15945 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$b$15780 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$b$15780 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$b$15780 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$15946:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$a$15947 [1] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$b$15948 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$15952:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$a$15785
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [6] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$a$15953 [1] 1'0 }, B={ 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][48]$b$15954 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$a$15785 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$a$15785 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$a$15785 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$15955:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$a$15956 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$b$15957 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$15820:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$a$15821 [3] 3'010 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][4]$b$15822 [2] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$a$15719 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$15958:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$a$15959 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$b$15960 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$15961:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$b$15963, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$a$15962 [2:1] 1'1 }, B={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][51]$b$15963 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [5:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$15964:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$a$15965 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][52]$b$15966 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$a$15791 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$15967:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$a$15968 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$b$15969 [4:3] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$15970:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$a$15794
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$a$15971 [2] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][54]$b$15972 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$a$15794 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$a$15794 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$a$15794 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$a$15794 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$15973:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$b$15795
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$a$15974 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][55]$b$15975 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$b$15795 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$b$15795 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$b$15795 [5:4] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][27]$b$15795 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$15976:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$a$15977 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [3] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][56]$b$15978 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$a$15797 [5] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$15979:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$b$15798
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$a$15980 [5:4] 4'1001 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][57]$b$15981 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$b$15798 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$b$15798 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$b$15798 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][28]$b$15798 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$15982:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$a$15800
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$a$15983 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][58]$b$15984 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$a$15800 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$a$15800 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$a$15800 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$a$15800 [5] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$15985:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$a$15986 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$b$15987 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$15823:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$b$15720
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [1] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$a$15824 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][5]$b$15825 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$b$15720 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$b$15720 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][2]$b$15720 [5] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$15988:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$a$15989 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [7] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][60]$b$15990 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$a$15803 [1] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$15991:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$a$15992 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][61]$b$15993 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][30]$b$15804 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$15994:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$a$15806
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$a$15995 [3] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [5] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][62]$b$15996 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$a$15806 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$a$15806 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$a$15806 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$a$15806 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$15997:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$a$15998 [2] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][63]$b$15999 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][31]$b$15807 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$15826:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$a$15827 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][6]$b$15828 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$a$15722 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$15829:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$a$15830 [3] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$b$15831 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$15832:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$a$15833 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][8]$b$15834 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725 [7:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$a$15725 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$15835:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$a$15836 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][9]$b$15837 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][4]$b$15726 [1] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$16573:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$b$16575 [3:2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [1] } = { 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$16603:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$b$16605 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [0] 3'100 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$16606:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$a$16607 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][11]$b$16608 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [3] 2'10 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$16609:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$a$16610 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][12]$b$16611 [6:5] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$a$16496 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$16612:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$b$16497
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$a$16613 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][13]$b$16614 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$b$16497 [4:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$b$16497 [7:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][6]$b$16497 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$16615:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$a$16616 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][14]$b$16617 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [3:2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [5] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$a$16499 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$16618:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$a$16619 [3:2] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [1:0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$b$16620 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$16621:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$a$16622 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$b$16623 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [6:5] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$16624:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$a$16625 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$b$16626 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$16627:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$a$16628 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$b$16629 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [0] 2'11 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$16630:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$a$16631 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][19]$b$16632 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$16576:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$a$16577 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][1]$b$16578 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [6:5] = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$16633:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$a$16634 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][20]$b$16635 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$a$16508 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$16636:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$b$16509
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$a$16637 [2] 2'00 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][21]$b$16638 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$b$16509 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$b$16509 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$b$16509 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][10]$b$16509 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$16639:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [5] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$a$16640 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$b$16641 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$16642:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$a$16643 [2:1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][23]$b$16644 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [0] 3'101 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$16645:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$a$16646 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][24]$b$16647 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$a$16514 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$16648:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$a$16649 [2:1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$b$16650 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [4:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$16651:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$a$16652 [3:2] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][26]$b$16653 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$a$16517 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$16654:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$b$16518
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$a$16655 [2] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][27]$b$16656 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$b$16518 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$b$16518 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$b$16518 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][13]$b$16518 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$16657:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$a$16658 [1] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [6] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$b$16659 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [6:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$16660:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$a$16661 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$b$16662 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [2] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$16579:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [4] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$a$16580 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][2]$b$16581 [3:2] 2'11 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$16663:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$a$16664 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$b$16665 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$16666:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$a$16667 [0] }, B={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][31]$b$16668 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524 [2:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524 [7:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524 [1:0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$b$16524 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$16669:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [0] 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$a$16670 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][32]$b$16671 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$16672:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$a$16673 [3] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][33]$b$16674 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [2:1] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$16675:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$a$16676 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677 [1] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$b$16677 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$16678:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$a$16679 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][35]$b$16680 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530 [4] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$b$16530 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$16681:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$a$16532
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [5] 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$a$16682 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][36]$b$16683 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$a$16532 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$a$16532 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$a$16532 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$a$16532 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$16684:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$a$16685 [3] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][37]$b$16686 [4:3] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [0] } = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][18]$b$16533 [1] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$16687:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$a$16688 [3] 2'11 }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][38]$b$16689 [3:2] 1'0 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [4:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$a$16535 [3] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$16690:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$a$16691, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$a$16691 [7] 3'110 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][39]$b$16692 [4] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][19]$b$16536 [4] 3'011 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$16582:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$a$16583 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][3]$b$16584 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$16693:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$a$16694 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][40]$b$16695 [4] 2'11 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$a$16538 [6] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$16696:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$b$16539
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$a$16697 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][41]$b$16698 [3] 3'100 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$b$16539 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$b$16539 [7:6] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][20]$b$16539 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$16699:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541
|
|
New ports: A={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$a$16700 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][42]$b$16701 [2:1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [1:0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$16702:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$a$16703 [2] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][43]$b$16704 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [0] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$16705:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$a$16706 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$b$16707 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$16708:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$b$16545
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$a$16709 [4:3] 3'101 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][45]$b$16710 [1:0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$b$16545 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$b$16545 [7] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$b$16545 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$16711:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$a$16712 [1] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$b$16713 [2:1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$16717:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$a$16550
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [6] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$a$16718 [1] 1'0 }, B={ 3'000 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][48]$b$16719 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$a$16550 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$a$16550 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$a$16550 [5] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$16720:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$a$16721 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$b$16722 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [0] } = 2'10
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$16585:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$a$16586 [3] 3'010 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][4]$b$16587 [2] 2'01 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484 [6:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$a$16484 [2] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$16723:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$a$16724 [0] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$b$16725 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$16726:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$b$16728, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2:1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$a$16727 [2:1] 1'1 }, B={ 4'1001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][51]$b$16728 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [5:3] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [2] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$16729:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$a$16730 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [1:0] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][52]$b$16731 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$a$16556 [0] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$16732:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$a$16733 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$b$16734 [4:3] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [4:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [5] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [4] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$16735:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$a$16559
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$a$16736 [2] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][54]$b$16737 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$a$16559 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$a$16559 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$a$16559 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$a$16559 [3] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$16738:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$b$16560
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [0] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$a$16739 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740 [1] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][55]$b$16740 [1:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$b$16560 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$b$16560 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$b$16560 [5:4] = { 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][27]$b$16560 [3] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$16741:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562
|
|
New ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$a$16742 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [3] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][56]$b$16743 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [2:1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$a$16562 [5] 2'00 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$16744:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$b$16563
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$a$16745 [5:4] 4'1001 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][57]$b$16746 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$b$16563 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$b$16563 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$b$16563 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][28]$b$16563 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$16747:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$a$16565
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$a$16748 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][58]$b$16749 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$a$16565 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$a$16565 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$a$16565 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$a$16565 [5] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$16750:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [1] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$a$16751 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$b$16752 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$16588:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$b$16485
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [1] 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$a$16589 [1:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][5]$b$16590 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$b$16485 [5:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$b$16485 [7:6] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][2]$b$16485 [5] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$16753:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$a$16754 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [7] 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][60]$b$16755 [2] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$a$16568 [1] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$16756:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [0] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$a$16757 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [3] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][61]$b$16758 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [3:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [4] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][30]$b$16569 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$16759:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$a$16571
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$a$16760 [3] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [5] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][62]$b$16761 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$a$16571 [6:1]
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$a$16571 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$a$16571 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$a$16571 [4] 1'1 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$16762:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$a$16763 [2] 2'00 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][63]$b$16764 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [4:3] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][31]$b$16572 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$16591:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [4] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$a$16592 [0] }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][6]$b$16593 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [2:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [3] } = { 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$a$16487 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$16594:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$a$16595 [3] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$b$16596 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [7:1]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [0] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$16597:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$a$16598 [1] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][8]$b$16599 [0] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490 [3:0]
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490 [7:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$a$16490 [0] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$16600:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601 [0] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$a$16601 [0] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][9]$b$16602 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][4]$b$16491 [1] 1'1 }
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$11561:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$a$11514
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$b$11563 [4:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$a$11514 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$a$11514 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$a$11514 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$11594:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][5]$b$11530
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [2:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [0] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$b$11596 [2:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][5]$b$11530 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][5]$b$11530 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][5]$b$11530 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$11609:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][8]$a$11538
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$a$11610 [2:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [7:6] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [3] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][16]$b$11611 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][8]$a$11538 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][8]$a$11538 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][8]$a$11538 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][8]$a$11538 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$11564:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$b$11515
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$a$11565 [5:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [3:2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][1]$b$11566 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$b$11515 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$b$11515 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$b$11515 [6] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][0]$b$11515 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$11624:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][10]$b$11545
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$a$11625 [2:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [3:2] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][21]$b$11626 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][10]$b$11545 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][10]$b$11545 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][10]$b$11545 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][10]$b$11545 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$11636:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][12]$b$11551
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [3:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$b$11638 [2:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][12]$b$11551 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][12]$b$11551 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][12]$b$11551 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][12]$b$11551 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$11576:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][2]$b$11521
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [0] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$a$11577 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [6:5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][5]$b$11578 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][2]$b$11521 [7:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][2]$b$11521 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][2]$b$11521 [1] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$11588:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589, B=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][4]$b$11527
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [7:6] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [3:2] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [7:6] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$b$11590 [3:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][4]$b$11527 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][4]$b$11527 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][4]$b$11527 [5] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][4][4]$b$11527 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$12871:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][5]$b$12807
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$a$12872 [1:0] }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][11]$b$12873 [1:0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][5]$b$12807 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][5]$b$12807 [1:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][5]$b$12807 [2] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$12877:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][6]$b$12810
|
|
New ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$a$12878 [6:0], B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][13]$b$12879 [4:0] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][6]$b$12810 [6:0]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][6]$b$12810 [7] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][6]$b$12810 [5]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$12913:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][12]$b$12828
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [5] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [3] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$a$12914 [1:0] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [5:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [0] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][25]$b$12915 [0] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][12]$b$12828 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][12]$b$12828 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][12]$b$12828 [6] = $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][12]$b$12828 [3]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$12862:
|
|
Old ports: A=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863, B=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$a$12863 [4:1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][8]$b$12864 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803 [5:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][4][4]$a$12803 [5] 1'0 }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$13538:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539, B=8'xxxxxxxx, Y=$memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][0][0]$b$13534
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [7:6] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][1][1]$a$13539 [2:0] }, B=5'xxxxx, Y={ $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][0][0]$b$13534 [7:6] $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][0][0]$b$13534 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][0][0]$b$13534 [5:3] = $memory\myMem_1_.aesCore.keySchedule.rconMem$rdmux[0][0][0]$b$13534 [2:0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$14182:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$a$14135
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$b$14184 [4:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$a$14135 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$a$14135 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$a$14135 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$14215:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][5]$b$14151
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$b$14217 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][5]$b$14151 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][5]$b$14151 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][5]$b$14151 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$14230:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][8]$a$14159
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$a$14231 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][16]$b$14232 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][8]$a$14159 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][8]$a$14159 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][8]$a$14159 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][8]$a$14159 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$14185:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$b$14136
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$a$14186 [5:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][1]$b$14187 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$b$14136 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$b$14136 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$b$14136 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][0]$b$14136 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$14245:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][10]$b$14166
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$a$14246 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [3:2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][21]$b$14247 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][10]$b$14166 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][10]$b$14166 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][10]$b$14166 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][10]$b$14166 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$14257:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][12]$b$14172
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [3:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$b$14259 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][12]$b$14172 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][12]$b$14172 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][12]$b$14172 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][12]$b$14172 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$14197:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][2]$b$14142
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$a$14198 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [6:5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][5]$b$14199 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][2]$b$14142 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][2]$b$14142 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][2]$b$14142 [1] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$14209:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][4]$b$14148
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [7:6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$b$14211 [3:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][4]$b$14148 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][4]$b$14148 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][4]$b$14148 [5] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][4][4]$b$14148 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$14947:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$a$14900
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$b$14949 [4:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$a$14900 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$a$14900 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$a$14900 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$14980:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][5]$b$14916
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$b$14982 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][5]$b$14916 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][5]$b$14916 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][5]$b$14916 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$14995:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][8]$a$14924
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$a$14996 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][16]$b$14997 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][8]$a$14924 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][8]$a$14924 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][8]$a$14924 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][8]$a$14924 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$14950:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$b$14901
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$a$14951 [5:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][1]$b$14952 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$b$14901 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$b$14901 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$b$14901 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][0]$b$14901 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$15010:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][10]$b$14931
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$a$15011 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [3:2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][21]$b$15012 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][10]$b$14931 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][10]$b$14931 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][10]$b$14931 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][10]$b$14931 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$15022:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][12]$b$14937
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [3:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$b$15024 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][12]$b$14937 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][12]$b$14937 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][12]$b$14937 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][12]$b$14937 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$14962:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][2]$b$14907
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$a$14963 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [6:5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][5]$b$14964 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][2]$b$14907 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][2]$b$14907 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][2]$b$14907 [1] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$14974:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][4]$b$14913
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [7:6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$b$14976 [3:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][4]$b$14913 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][4]$b$14913 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][4]$b$14913 [5] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][4][4]$b$14913 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$15712:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$a$15665
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$b$15714 [4:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$a$15665 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$a$15665 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$a$15665 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$15745:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][5]$b$15681
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$b$15747 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][5]$b$15681 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][5]$b$15681 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][5]$b$15681 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$15760:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][8]$a$15689
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$a$15761 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][16]$b$15762 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][8]$a$15689 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][8]$a$15689 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][8]$a$15689 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][8]$a$15689 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$15715:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$b$15666
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$a$15716 [5:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][1]$b$15717 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$b$15666 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$b$15666 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$b$15666 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][0]$b$15666 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$15775:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][10]$b$15696
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$a$15776 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [3:2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][21]$b$15777 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][10]$b$15696 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][10]$b$15696 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][10]$b$15696 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][10]$b$15696 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$15787:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][12]$b$15702
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [3:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$b$15789 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][12]$b$15702 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][12]$b$15702 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][12]$b$15702 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][12]$b$15702 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$15727:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][2]$b$15672
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$a$15728 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [6:5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][5]$b$15729 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][2]$b$15672 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][2]$b$15672 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][2]$b$15672 [1] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$15739:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][4]$b$15678
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [7:6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$b$15741 [3:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][4]$b$15678 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][4]$b$15678 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][4]$b$15678 [5] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][4][4]$b$15678 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$16477:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$a$16430
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [4:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$b$16479 [4:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$a$16430 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$a$16430 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$a$16430 [6] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$16510:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][5]$b$16446
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [0] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$b$16512 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][5]$b$16446 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][5]$b$16446 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][5]$b$16446 [3] = 1'1
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$16525:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][8]$a$16454
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$a$16526 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [3] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][16]$b$16527 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][8]$a$16454 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][8]$a$16454 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][8]$a$16454 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][8]$a$16454 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$16480:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$b$16431
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$a$16481 [5:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][1]$b$16482 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$b$16431 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$b$16431 [5:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$b$16431 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][0]$b$16431 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$16540:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][10]$b$16461
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$a$16541 [2:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [3:2] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][21]$b$16542 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][10]$b$16461 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][10]$b$16461 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][10]$b$16461 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][10]$b$16461 [0]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$16552:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][12]$b$16467
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [3:0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$b$16554 [2:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][12]$b$16467 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][12]$b$16467 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][12]$b$16467 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][12]$b$16467 [2]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$16492:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][2]$b$16437
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [0] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$a$16493 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [6:5] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][5]$b$16494 [0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][2]$b$16437 [7:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][2]$b$16437 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][2]$b$16437 [1] = 1'0
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$16504:
|
|
Old ports: A=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505, B=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][4]$b$16443
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [7:6] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [3:2] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [0] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [7:6] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$b$16506 [3:0] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][4]$b$16443 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][4]$b$16443 [4:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][4]$b$16443 [5] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][4][4]$b$16443 [0]
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 1200 changes.
|
|
|
|
2.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~2250 debug messages>
|
|
Removed a total of 750 cells.
|
|
|
|
2.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 752 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~501 debug messages>
|
|
|
|
2.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$11657:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [4:1]
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][0]$a$11562 [3] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][15]$11702:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'11 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [4:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'11 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][7]$b$11584 [2] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][16]$11705:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$a$11586 [1] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][17]$11708:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][8]$b$11587 [5:4] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][18]$11711:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [3:2] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [5] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [3:2] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][9]$a$11589 [6:5] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][22]$11723:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [2:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 3'001 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][11]$a$11595 [0] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][25]$11732:
|
|
Old ports: A={ 3'010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [3:1] }
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][12]$b$11599 [2:1] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][28]$11741:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'01 }, B={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [5:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$a$11604 [7] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][29]$11744:
|
|
Old ports: A={ 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [2] }
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][14]$b$11605 [2] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][30]$11747:
|
|
Old ports: A={ 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [3:0] }
|
|
New ports: A={ 4'0111 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [6:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][15]$a$11607 [3] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][34]$11759:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [1:0] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [5:4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][17]$a$11613 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][44]$11789:
|
|
Old ports: A={ 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [5] }
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [5] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][22]$a$11628 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][46]$11795:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [5:1] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 }, B={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [5:2] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][23]$a$11631 [1] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][49]$11804:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][24]$b$11635 [1] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][50]$11807:
|
|
Old ports: A={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [1:0] }
|
|
New ports: A={ 3'111 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][25]$a$11637 [0] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][53]$11816:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [3:0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][26]$b$11641 [6] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][59]$11834:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [4] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [3] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [6] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][29]$b$11650 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][7]$11678:
|
|
Old ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [7:1]
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [3:1] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][5][3]$b$11572 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][0]$12934:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [6:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][0]$a$12839 [1:0] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][13]$12973:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [3:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [6] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 3'100 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [3:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [6] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][6]$b$12858 [7] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][14]$12976:
|
|
Old ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [7:4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [2:1] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [3] }
|
|
New ports: A={ 3'011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [2:1] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$a$12860 [3] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][15]$12979:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][7]$b$12861 [6] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][18]$12988:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 2'10 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [7:3]
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'0 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 3'101 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][9]$a$12866 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][20]$12994:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'0 }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [5:2]
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B=2'00, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [2] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][10]$a$12869 [4:3] = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][28]$13018:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [7:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'00 }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 4'0011 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [1:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][14]$a$12881 [4] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][2]$12940:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [5] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] 1'1 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][1]$a$12842 [5] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][30]$13024:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [1] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [5] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][15]$a$12884 [1] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][41]$13057:
|
|
Old ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900 [7:2]
|
|
New ports: A={ 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 1'1 }, B={ 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1] 2'00 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [4] }, Y=$memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900 [7:3]
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][20]$b$12900 [2] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][0]$a$11658 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][44]$13066:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [7:5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [1:0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][22]$a$12905 [5] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][53]$13093:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 2'01 }, B={ 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [4:2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'1 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'01 }, B={ 3'001 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][26]$b$12918 [2] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][57]$13105:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] 2'10 }, B={ 2'11 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [4] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [6] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] 3'010 }, B={ 3'110 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5] }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [7] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [4:3] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [6] }
|
|
New connections: $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][28]$b$12924 [2] = $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][31]$b$11752 [5]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][6][8]$12958:
|
|
Old ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 1'0 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [5] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [3] }
|
|
New ports: A={ 2'01 $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }, B={ $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] 2'00 }, Y={ $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [7:6] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [2] $memory\myMem_1_.aesCore.engine.sBoxMemInv$rdmux[0][5][4]$a$12851 [5] } = { $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [4] $memory\myMem_1_.aesCore.engine.sBoxMem$rdmux[0][6][10]$a$11688 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$14278:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [4:1]
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][0]$a$14183 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][15]$14323:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [4:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][7]$b$14205 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][16]$14326:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$a$14207 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][17]$14329:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][8]$b$14208 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][18]$14332:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [5] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [3:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][9]$a$14210 [6:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][22]$14344:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [2:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 3'001 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][11]$a$14216 [0] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][25]$14353:
|
|
Old ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [3:1] }
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][12]$b$14220 [2:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][28]$14362:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 2'01 }, B={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$a$14225 [7] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][29]$14365:
|
|
Old ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [2] }
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][14]$b$14226 [2] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][30]$14368:
|
|
Old ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [3:0] }
|
|
New ports: A={ 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][15]$a$14228 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][34]$14380:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [1:0] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][17]$a$14234 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][44]$14410:
|
|
Old ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [5] }
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [5] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][22]$a$14249 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][46]$14416:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [5:1] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [5:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][23]$a$14252 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][49]$14425:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][24]$b$14256 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][50]$14428:
|
|
Old ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [1:0] }
|
|
New ports: A={ 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][25]$a$14258 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][53]$14437:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [3:0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][26]$b$14262 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][59]$14455:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [4] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][29]$b$14271 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][10]$a$14309 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][7]$14299:
|
|
Old ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [7:1]
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [3:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][5][3]$b$14193 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[0][6][0]$a$14279 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$15043:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [4:1]
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][0]$a$14948 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][15]$15088:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [4:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][7]$b$14970 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][16]$15091:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$a$14972 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][17]$15094:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][8]$b$14973 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][18]$15097:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [5] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [3:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][9]$a$14975 [6:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][22]$15109:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [2:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 3'001 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][11]$a$14981 [0] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][25]$15118:
|
|
Old ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [3:1] }
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][12]$b$14985 [2:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][28]$15127:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 2'01 }, B={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$a$14990 [7] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][29]$15130:
|
|
Old ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [2] }
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][14]$b$14991 [2] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][30]$15133:
|
|
Old ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [3:0] }
|
|
New ports: A={ 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][15]$a$14993 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][34]$15145:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [1:0] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][17]$a$14999 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][44]$15175:
|
|
Old ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [5] }
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [5] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][22]$a$15014 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][46]$15181:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [5:1] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [5:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][23]$a$15017 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][49]$15190:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][24]$b$15021 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][50]$15193:
|
|
Old ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [1:0] }
|
|
New ports: A={ 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][25]$a$15023 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][53]$15202:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [3:0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][26]$b$15027 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][59]$15220:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [4] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][29]$b$15036 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][10]$a$15074 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][7]$15064:
|
|
Old ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [7:1]
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [3:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][5][3]$b$14958 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[1][6][0]$a$15044 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$15808:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [4:1]
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][0]$a$15713 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][15]$15853:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [4:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][7]$b$15735 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][16]$15856:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$a$15737 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][17]$15859:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][8]$b$15738 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][18]$15862:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [5] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [3:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][9]$a$15740 [6:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][22]$15874:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [2:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 3'001 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][11]$a$15746 [0] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][25]$15883:
|
|
Old ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [3:1] }
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][12]$b$15750 [2:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][28]$15892:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 2'01 }, B={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$a$15755 [7] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][29]$15895:
|
|
Old ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [2] }
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][14]$b$15756 [2] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][30]$15898:
|
|
Old ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [3:0] }
|
|
New ports: A={ 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][15]$a$15758 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][34]$15910:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [1:0] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][17]$a$15764 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][44]$15940:
|
|
Old ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [5] }
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [5] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][22]$a$15779 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][46]$15946:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [5:1] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [5:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][23]$a$15782 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][49]$15955:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][24]$b$15786 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][50]$15958:
|
|
Old ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [1:0] }
|
|
New ports: A={ 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][25]$a$15788 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][53]$15967:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [3:0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][26]$b$15792 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][59]$15985:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [4] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][29]$b$15801 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][10]$a$15839 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][7]$15829:
|
|
Old ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [7:1]
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [3:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][5][3]$b$15723 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[2][6][0]$a$15809 [1]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$16573:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'1 }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [4:1]
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][0]$a$16478 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][15]$16618:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [4:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 2'11 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [1:0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][7]$b$16500 [2] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][16]$16621:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [1:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 2'01 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$a$16502 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][17]$16624:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][8]$b$16503 [5:4] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][18]$16627:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [3:2] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [5] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 }, B={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [3:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][9]$a$16505 [6:5] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][22]$16639:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 3'001 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [2:0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 3'001 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [2:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][11]$a$16511 [0] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][25]$16648:
|
|
Old ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [3:1] }
|
|
New ports: A={ 3'010 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [3] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][12]$b$16515 [2:1] = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][28]$16657:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [6:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [0] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 2'01 }, B={ 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [5:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [0] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$a$16520 [7] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][29]$16660:
|
|
Old ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [2] }
|
|
New ports: A={ 3'100 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][14]$b$16521 [2] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][30]$16663:
|
|
Old ports: A={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [3:0] }
|
|
New ports: A={ 4'0111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [6:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [2:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][15]$a$16523 [3] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][34]$16675:
|
|
Old ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [7:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [1:0] }
|
|
New ports: A={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 3'011 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [5:4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][17]$a$16529 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][44]$16705:
|
|
Old ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [4:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [5] }
|
|
New ports: A={ 3'110 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 1'1 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [5] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][22]$a$16544 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][46]$16711:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [5:1] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 }, B={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [5:2] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][23]$a$16547 [1] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][49]$16720:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [7:3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [1] }
|
|
New ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, B={ 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [3] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][24]$b$16551 [1] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][50]$16723:
|
|
Old ports: A={ 2'11 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [1:0] }
|
|
New ports: A={ 3'111 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'0 }, B={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [7:6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [1] }
|
|
New connections: { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][25]$a$16553 [0] } = { $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][53]$16732:
|
|
Old ports: A={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [3:0] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] 3'110 }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [3:0] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][26]$b$16557 [6] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][59]$16750:
|
|
Old ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [4] }
|
|
New ports: A={ 1'0 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [3] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [6] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [7] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][29]$b$16566 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][10]$a$16604 [7]
|
|
Consolidated identical input bits for $mux cell $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][7]$16594:
|
|
Old ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, Y=$memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [7:1]
|
|
New ports: A={ 2'10 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 2'10 }, B={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [4] 1'1 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] 2'00 $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1] }, Y={ $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [7:5] $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [3:1] }
|
|
New connections: $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][5][3]$b$16488 [4] = $memory\myMem_1_.aesCore.keySchedule.sBoxMem$rdmux[3][6][0]$a$16574 [1]
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 104 changes.
|
|
|
|
2.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 10 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \PQVexRiscvUlx3s..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~501 debug messages>
|
|
|
|
2.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \PQVexRiscvUlx3s.
|
|
Performed a total of 0 changes.
|
|
|
|
2.32.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.32.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.32.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.32.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
|
|
2.32.30. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
2.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ecp5_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $adff.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $adffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc.
|
|
add { \core_cpu.execute_to_memory_MUL_HH \core_cpu.execute_to_memory_MUL_LL [31:16] } (48 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_LH (32 bits, unsigned)
|
|
add \core_cpu.execute_to_memory_MUL_HL (32 bits, unsigned)
|
|
add \core_ibus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_valid (1 bits, unsigned)
|
|
add bits \core_ibus_decoder._zz_5_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=33\B_WIDTH=32\Y_WIDTH=33 for cells of type $alu.
|
|
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
|
|
add \core_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned)
|
|
sub \core_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned)
|
|
add bits \core_cpu.IBusSimplePlugin_pending_inc (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=11 for cells of type $pmux.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
|
|
Using template $paramod$constmap:0c58e37f7f9ab9c08bb604a660a738f4cdfdf6a8$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
add \core_dbus_decoder.logic_rspPendingCounter (2 bits, unsigned)
|
|
sub \core_cpu.dBus_rsp_ready (1 bits, unsigned)
|
|
add bits \core_dbus_decoder._zz_6_ (1 bits)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=1\Y_WIDTH=20 for cells of type $alu.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
|
|
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
|
|
Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.85. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~3192 debug messages>
|
|
|
|
2.33.86. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~35 debug messages>
|
|
Removed 0 unused cells and 8 unused wires.
|
|
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=15 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
|
|
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 0 of port B: 1'0
|
|
Constant input on bit 1 of port B: 1'1
|
|
Creating constmapped module `$paramod$constmap:3f7a4e9cbeede37f035be04949449012127f0a59$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:3f7a4e9cbeede37f035be04949449012127f0a59$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~866 debug messages>
|
|
|
|
2.33.101. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:3f7a4e9cbeede37f035be04949449012127f0a59$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~123 debug messages>
|
|
Removed 0 unused cells and 11 unused wires.
|
|
Using template $paramod$constmap:3f7a4e9cbeede37f035be04949449012127f0a59$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 0 of port B: 1'1
|
|
Constant input on bit 1 of port B: 1'0
|
|
Creating constmapped module `$paramod$constmap:a86a5f1176a0afc2b40c6921ec7ea39b62b8e1c6$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.102. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:a86a5f1176a0afc2b40c6921ec7ea39b62b8e1c6$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.33.103. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:a86a5f1176a0afc2b40c6921ec7ea39b62b8e1c6$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~123 debug messages>
|
|
Removed 0 unused cells and 11 unused wires.
|
|
Using template $paramod$constmap:a86a5f1176a0afc2b40c6921ec7ea39b62b8e1c6$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 0 of port B: 1'0
|
|
Constant input on bit 1 of port B: 1'0
|
|
Creating constmapped module `$paramod$constmap:4a2746946c88d4a0e6a80ed22aef3f0805e9412f$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
|
|
2.33.104. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:4a2746946c88d4a0e6a80ed22aef3f0805e9412f$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.33.105. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:4a2746946c88d4a0e6a80ed22aef3f0805e9412f$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr.
|
|
<suppressed ~123 debug messages>
|
|
Removed 0 unused cells and 11 unused wires.
|
|
Using template $paramod$constmap:4a2746946c88d4a0e6a80ed22aef3f0805e9412f$paramod$818de01436016e448cf31b34b4efcd3e435835f9\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=6 for cells of type $pmux.
|
|
Using template $paramod\_90_pmux\WIDTH=31\S_WIDTH=4 for cells of type $pmux.
|
|
add \core_cpu.decode_to_execute_SRC1 (32 bits, signed)
|
|
add { 1'0 \core_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
|
|
add \core_cpu._zz_211_ (32 bits, signed)
|
|
packed 1 (1) bits / 1 words into adder tree
|
|
add \core_cpu.memory_to_writeBack_MUL [63:32] (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:6899$923_Y (32 bits, unsigned)
|
|
add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:6898$921_Y (32 bits, unsigned)
|
|
add 2 (32 bits, unsigned)
|
|
packed 2 (1) bits / 1 words into adder tree
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=2 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=48 for cells of type $fa.
|
|
Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=3 for cells of type $fa.
|
|
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa.
|
|
No more expansions possible.
|
|
<suppressed ~3515 debug messages>
|
|
|
|
2.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~5131 debug messages>
|
|
|
|
2.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\PQVexRiscvUlx3s'.
|
|
<suppressed ~10158 debug messages>
|
|
Removed a total of 3386 cells.
|
|
|
|
2.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 1272 unused cells and 5667 unused wires.
|
|
<suppressed ~1279 debug messages>
|
|
|
|
2.34.5. Finished fast OPT passes.
|
|
|
|
2.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
|
|
2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
2.37. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.37.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
|
|
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
|
|
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
|
|
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
|
|
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
|
|
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
|
|
Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_.
|
|
Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_.
|
|
Using template \$_DFFE_PP1N_ for cells of type $_DFFE_PP1N_.
|
|
No more expansions possible.
|
|
<suppressed ~2932 debug messages>
|
|
|
|
2.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module PQVexRiscvUlx3s.
|
|
<suppressed ~124 debug messages>
|
|
|
|
2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.40. Executing ECP5_GSR pass (implement FF init values).
|
|
Handling GSR in PQVexRiscvUlx3s.
|
|
|
|
2.41. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
2.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \PQVexRiscvUlx3s..
|
|
Removed 0 unused cells and 13478 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.44. Executing ABC pass (technology mapping using ABC).
|
|
|
|
2.44.1. Extracting gate netlist of module `\PQVexRiscvUlx3s' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 13007 gates and 15928 wires to a netlist network with 2919 inputs and 1844 outputs.
|
|
|
|
2.44.1.1. Executing ABC.
|
|
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + dress
|
|
ABC: Total number of equiv classes = 2903.
|
|
ABC: Participating nodes from both networks = 6238.
|
|
ABC: Participating nodes from the first network = 2990. ( 68.11 % of nodes)
|
|
ABC: Participating nodes from the second network = 3248. ( 73.99 % of nodes)
|
|
ABC: Node pairs (any polarity) = 2988. ( 68.06 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 2178. ( 49.61 % of names can be moved)
|
|
ABC: Total runtime = 0.77 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
2.44.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 4388
|
|
ABC RESULTS: internal signals: 11165
|
|
ABC RESULTS: input signals: 2919
|
|
ABC RESULTS: output signals: 1844
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 7543 unused wires.
|
|
|
|
2.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.45.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268435456 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65536 for cells of type $lut.
|
|
Using template $paramod$b5cd238a527d851ba52055b76f8b8313ff4d0a1d\$lut for cells of type $lut.
|
|
Using template $paramod$3e7bb24c7b3e72ddd1c4d01d6ac886c85abf5536\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
|
|
Using template $paramod$078354ad4f08d5c6e8687216ff1586f28ff6611c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
|
|
Using template $paramod$b79f112e8a2746cc0951ad54f89968c64adae83e\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111110111100001111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110111011101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011111000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=386990080 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101100111111111010000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268398592 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429409791 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429470991 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010101010011001100001111 for cells of type $lut.
|
|
Using template $paramod$09db494c5d72b218f5a005e8b0691c1ee18eb7d0\$lut for cells of type $lut.
|
|
Using template $paramod$1b969c406d47df4e06ab8cd4e7fdd82e4a6bbb68\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16728128 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16777216 for cells of type $lut.
|
|
Using template $paramod$aec6becf4c1a43314c077a93f27747e5d50f6c54\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073741824 for cells of type $lut.
|
|
Using template $paramod$04579d5a7f7d11008d5c4dab02ae6edd004a19ac\$lut for cells of type $lut.
|
|
Using template $paramod$799c3bfa21d04352c5caabfede06993d5e1b8b75\$lut for cells of type $lut.
|
|
Using template $paramod$0d7d1babf6d510c8a2ee2474890db5c70fbce42d\$lut for cells of type $lut.
|
|
Using template $paramod$6cfe34dd57659d25b9a0f81d8ede66776ee0ba49\$lut for cells of type $lut.
|
|
Using template $paramod$55728f947c7dc653c098e44a9dd26925ed137e02\$lut for cells of type $lut.
|
|
Using template $paramod$f3c0a3264f891e491a0df55d11f04c57d3073661\$lut for cells of type $lut.
|
|
Using template $paramod$57619346c001bba14f685682aaa48a843cd5a7a5\$lut for cells of type $lut.
|
|
Using template $paramod$05988f2759498dfa5196bf3aeb8993f2baaaa84d\$lut for cells of type $lut.
|
|
Using template $paramod$86c6e6c900165e983f0c6826f9b628e95bed89fb\$lut for cells of type $lut.
|
|
Using template $paramod$f76f673c170a3183505b49436550b7f2564249f5\$lut for cells of type $lut.
|
|
Using template $paramod$77d0cf87087dacef4ba73455f3ec528ae3959aa1\$lut for cells of type $lut.
|
|
Using template $paramod$ac66e8e59ea5acbe95aab01ec153734f5de54da9\$lut for cells of type $lut.
|
|
Using template $paramod$5fba6fa4affd3d8cb90b92595f737467c857f3c8\$lut for cells of type $lut.
|
|
Using template $paramod$496ef0cdc25fbde6d1104e5613085feb2dea50e9\$lut for cells of type $lut.
|
|
Using template $paramod$02a8a4fc5cfb6662357b79a7b88b86601647850b\$lut for cells of type $lut.
|
|
Using template $paramod$8f8c23ef30604e2b93bc310417e020afe264fce5\$lut for cells of type $lut.
|
|
Using template $paramod$d3854e401fe5b8b146829835823fbfb0b0c02108\$lut for cells of type $lut.
|
|
Using template $paramod$72e29779f342e56336d86b6f5134ba4c4c27af9e\$lut for cells of type $lut.
|
|
Using template $paramod$adcec54ea177b53004202833045475be191615b1\$lut for cells of type $lut.
|
|
Using template $paramod$e10ca4aca4e4c8627be5bb912095a9253494b061\$lut for cells of type $lut.
|
|
Using template $paramod$3db5222268494bd8b48f3c890a4efec82d3d6ed1\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111110100000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11100000000000001111000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod$0886e4550c3cbe336cd2a314faa74ba4ea86449c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001010001001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001111101011110000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252641501 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=218103821 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549387 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100111110101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429467376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000101010100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110010101010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011101100000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110101110001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196131771 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1911 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663244 for cells of type $lut.
|
|
Using template $paramod$0359540d1441c1182534de6006fa776a0f8fef62\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=7697919 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=14614528 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=184549376 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111110001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=15724527 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111100010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut.
|
|
Using template $paramod$cd330df79dbef1bbe5dfa5ce3cb4d5632fec36ca\$lut for cells of type $lut.
|
|
Using template $paramod$dc8c2960d49b9744c9316a10f5cda7dc93b63caf\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=285212671 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01110001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$6aea0429a561ce25f5ecbc7cb2e74bd8a5c0ee5c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=125239296 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252663091 for cells of type $lut.
|
|
Using template $paramod$f6783b5b9c23cd67232c94ac1b12661d5b0309d0\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100100010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1303511040 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1090519040 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=5570812 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101011100110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073709056 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=866840816 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=252654421 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000100010000111100001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11010000000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=47883 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000010010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=33488896 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111011000010110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=218103808 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11010000000011010000000000000000 for cells of type $lut.
|
|
Using template $paramod$c708770091716d95e2d30be87305b107dccb9e26\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65408 for cells of type $lut.
|
|
Using template $paramod$e5b1bf409dce4e2e9c1e62600594c02b17a0bf54\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=268500992 for cells of type $lut.
|
|
Using template $paramod$b1bd2a921ec0f1ea0cc7578a2bcf32d761c7f62f\$lut for cells of type $lut.
|
|
Using template $paramod$f340a7e85fbe3e11c384ecf1cd11a7f6ad674e2c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000011111110000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=267444928 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut.
|
|
Using template $paramod$8d9beb036c5aa42591e9664d67cb27d04310e132\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100011100001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100110110110010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101110111011001100000000001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1430017365 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111110000000010000000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2139062016 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111111000000000000000 for cells of type $lut.
|
|
Using template $paramod$fff544d368e9e42c06a9b5ff5ab7682052383587\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=786420 for cells of type $lut.
|
|
Using template $paramod$889794b06e51cc9abecc4e94488b543d00f7091b\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001101011100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
|
|
Using template $paramod$6ae62cb4eac748a20aae9a13eb46836a08316628\$lut for cells of type $lut.
|
|
Using template $paramod$99876b460dbe78d61ff2fb6faa5533329e246869\$lut for cells of type $lut.
|
|
Using template $paramod$25a35cb2a8b2c93dc1ca4c772dbbfc5849484db4\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100010000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=106979334 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101110001000100000111111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100110111 for cells of type $lut.
|
|
Using template $paramod$ca9a379eb1ae33c0e3c2d80b49c80b923a75705e\$lut for cells of type $lut.
|
|
Using template $paramod$24353dcdfbe77e56c0397e5497e419ffc900e922\$lut for cells of type $lut.
|
|
Using template $paramod$1662a881c746d8130727ef2507ecb359c43a1062\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001100101010101111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111010000010101100110000110011 for cells of type $lut.
|
|
Using template $paramod$6cb3f788d3021429b5df842d68d4cbfe74ae3fb7\$lut for cells of type $lut.
|
|
Using template $paramod$8a4e41c56300237865ea73c786d86ca3fb933dd7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101100010100110101001110101100 for cells of type $lut.
|
|
Using template $paramod$0d6f9ebd8a64a1e59af29a82779614c9504c7036\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10001000100010001111000000000000 for cells of type $lut.
|
|
Using template $paramod$b5ab95c3cf3da0f006ed5d00e3f8c08bc4833891\$lut for cells of type $lut.
|
|
Using template $paramod$41ff8973ed87e065a85f624ffe8652626ab31b7b\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110101111111000000101000000011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110001010011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101110001000101111000000001111 for cells of type $lut.
|
|
Using template $paramod$dfde1d1e6201b0fbf3ef72739e274442c9900199\$lut for cells of type $lut.
|
|
Using template $paramod$1891e0425043f2fe4c187b7b5e05bc7e665d7d10\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001011010 for cells of type $lut.
|
|
Using template $paramod$9da8c95982b19e30770fdf82a67b3f8e921159de\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1073790975 for cells of type $lut.
|
|
Using template $paramod$a077fa53750525334e87d31eed21aaeb8b5bd18d\$lut for cells of type $lut.
|
|
Using template $paramod$07301ce55054400015e356b420acd24ad38ded14\$lut for cells of type $lut.
|
|
Using template $paramod$d6eeb0b4b9078cc62f4bf49697f95272ee006269\$lut for cells of type $lut.
|
|
Using template $paramod$bed40aacfecdf9ef426b86892becb041d856b95a\$lut for cells of type $lut.
|
|
Using template $paramod$d59ca8da185a5df827b42108464329dbeefd6585\$lut for cells of type $lut.
|
|
Using template $paramod$79d9ad1a221993638e5bf09075913e5a51393823\$lut for cells of type $lut.
|
|
Using template $paramod$5d4d246d86304f54d047661a28a61855541a072e\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111001000001 for cells of type $lut.
|
|
Using template $paramod$c949002608ce56602c7a7306b0acd997cd6c8121\$lut for cells of type $lut.
|
|
Using template $paramod$cf4d911d39a8b6e0eae241eb397d7ec3f3de6ed2\$lut for cells of type $lut.
|
|
Using template $paramod$7a839c6f632308f4fa6ea3fd8b752e0628628f39\$lut for cells of type $lut.
|
|
Using template $paramod$5c4ac5782c7d3d56b1032afac3cd1d1a7405f092\$lut for cells of type $lut.
|
|
Using template $paramod$7fa77394849df2b01761e2a739730d37d0fb5976\$lut for cells of type $lut.
|
|
Using template $paramod$9142608426c3e39011b16e2d85e1eae1a2ef2afb\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100001110100101 for cells of type $lut.
|
|
Using template $paramod$8f4cc6182485b041670facf313b3e4758357a3c8\$lut for cells of type $lut.
|
|
Using template $paramod$f0c7dc53d888b54a463e7162f93ac81a8d654729\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001000100011111111 for cells of type $lut.
|
|
Using template $paramod$d1aecf569f2e2e3c5352ce4ef298a8f62ee8a319\$lut for cells of type $lut.
|
|
Using template $paramod$8fd70d704927e0b673d679584d9484203bb4fc6e\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut.
|
|
Using template $paramod$927f760c6d2e91800550d809246594639376b3ec\$lut for cells of type $lut.
|
|
Using template $paramod$768e2ddb14a44966ef33aeccf7f6c2ea6cf3ea3a\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065336832 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1329324815 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=389080129 for cells of type $lut.
|
|
Using template $paramod$0619cc75fc854444e0f16812f5b00e853fb03c9b\$lut for cells of type $lut.
|
|
Using template $paramod$bc410797690c04a23a02ea8f456ca7d61c806c76\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111010000010100011001111001100 for cells of type $lut.
|
|
Using template $paramod$b0965ca416b9406c1b9af2b810555634ae8d1db1\$lut for cells of type $lut.
|
|
Using template $paramod$c6c90116c41207d9baf7495a62544242e7b19984\$lut for cells of type $lut.
|
|
Using template $paramod$b44ec57c49ba85e84216d36b2b4c39c3cd60138f\$lut for cells of type $lut.
|
|
Using template $paramod$6f6e8665a48ac054c8874d4d6a50e50caf71b80b\$lut for cells of type $lut.
|
|
Using template $paramod$b28a91a874fed812c4a821744726474dd53ba5ca\$lut for cells of type $lut.
|
|
Using template $paramod$92914ec3cd47829de2d82471e2c63fc411ff7792\$lut for cells of type $lut.
|
|
Using template $paramod$d8d7cfa96b1bc05f2e142f379666235259efd06d\$lut for cells of type $lut.
|
|
Using template $paramod$f48362ad7e874b3afef549618595d81e937e3344\$lut for cells of type $lut.
|
|
Using template $paramod$b4594187670e488ddd07d53983111e5cfced2610\$lut for cells of type $lut.
|
|
Using template $paramod$d7b501fac4266bcebc02cf42618557d5245be529\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001110101100 for cells of type $lut.
|
|
Using template $paramod$743590b93ea9285c10cafe142b2e9827bd55d6f3\$lut for cells of type $lut.
|
|
Using template $paramod$0c8a5621e5f6469216aafcbdb0e9630d4c1a0602\$lut for cells of type $lut.
|
|
Using template $paramod$e2202363faf3834fe1a97d6ab5523c0c1aac41cc\$lut for cells of type $lut.
|
|
Using template $paramod$2a2f80aecf613b95f20e829b7231efc9e82ee07e\$lut for cells of type $lut.
|
|
Using template $paramod$ddce4cb9f1a7e290226824248f49c001dbcdd0ae\$lut for cells of type $lut.
|
|
Using template $paramod$52ee4816867f82a61e9da208abe6d3f45333fa34\$lut for cells of type $lut.
|
|
Using template $paramod$2f5d9ebc619723c04283bef461dd7b506ba474e1\$lut for cells of type $lut.
|
|
Using template $paramod$c0e9808355dbb28c6be87bb7e39a3997ae8290fd\$lut for cells of type $lut.
|
|
Using template $paramod$84aa9588bd0a639c3909503af9e39a521f28077e\$lut for cells of type $lut.
|
|
Using template $paramod$3e29d28bf39a8d4476c628b4112bd6760dd78d4d\$lut for cells of type $lut.
|
|
Using template $paramod$03f9c918276be99418c6dc9fd562c17ec86601f0\$lut for cells of type $lut.
|
|
Using template $paramod$171122641273354d28282a7e34bf440941d031cb\$lut for cells of type $lut.
|
|
Using template $paramod$cea49ddef82ae2eecba3aabef270be1ec1f64008\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
|
|
Using template $paramod$60d4e682375bf10ee3a94f4305cd1f90283babcb\$lut for cells of type $lut.
|
|
Using template $paramod$aac393ce857feac3263eed3e3e2f6e2a651ba571\$lut for cells of type $lut.
|
|
Using template $paramod$9996ad99fb0cbcdf8315691f425b2f4328377965\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10011011111010011111001010000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut.
|
|
Using template $paramod$930498702dea6e0679684b9263ecaae63388e4f3\$lut for cells of type $lut.
|
|
Using template $paramod$368044d11f55cf9167d696c6d0d8c04edd0bd336\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=66890325 for cells of type $lut.
|
|
Using template $paramod$95b6cfee2e6747385db671ed6f69b5bdf7a49fc3\$lut for cells of type $lut.
|
|
Using template $paramod$c9cde96730aebe7eecaec1c2e7ca79b00df8df8b\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011001111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010001111111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1145310976 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011000000111100001111 for cells of type $lut.
|
|
Using template $paramod$1da9fa5a1b1a5cce9740125e3c96ce96fd329502\$lut for cells of type $lut.
|
|
Using template $paramod$b69f4ff842b3cf09c58866d9a081de8d9a6373cf\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=201257985 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111101001111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=196148992 for cells of type $lut.
|
|
Using template $paramod$a3f23ef66a2a8dfdff2d84774f26c83035f10055\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111001100000001101111000111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=8323200 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11000000110000001101111111110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=53167 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111111111011101110111011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111111111 for cells of type $lut.
|
|
Using template $paramod$2eca855ec0d0731046ff952c185f036d695fd0c6\$lut for cells of type $lut.
|
|
Using template $paramod$e8ddc6a126c8cf995742bb8c0ecc47a58ec86d48\$lut for cells of type $lut.
|
|
Using template $paramod$f9adc9bc31233999d523b96137784c8c941eead1\$lut for cells of type $lut.
|
|
Using template $paramod$a001a7d1dd5f99ab7b738f992e42ef7d68166e3b\$lut for cells of type $lut.
|
|
Using template $paramod$c02df607f3457400eb35f205d819551617a238da\$lut for cells of type $lut.
|
|
Using template $paramod$71ef33c165e3d2c721a3d4bc1e1a14d54f3d1bab\$lut for cells of type $lut.
|
|
Using template $paramod$24c735b9df8687df362012290398915db7976d05\$lut for cells of type $lut.
|
|
Using template $paramod$3dddb077fc64077c593cd4f30ff6ada530902fa6\$lut for cells of type $lut.
|
|
Using template $paramod$a3d3d8cf95ee4eb532ddd9037decdce6e5b0d2aa\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=7 for cells of type $lut.
|
|
Using template $paramod$56f3e246421b6b29fd066d86d01fc72a1f44c94f\$lut for cells of type $lut.
|
|
Using template $paramod$6fd4e0e0ddfe8a8b547ef5986f5eef07c1b7b74e\$lut for cells of type $lut.
|
|
Using template $paramod$93a9d1979a7ea2ff4eaf6fefb75476c8fc6a480f\$lut for cells of type $lut.
|
|
Using template $paramod$adae1cbea3825d96228e06a9b6c4889d77f204e2\$lut for cells of type $lut.
|
|
Using template $paramod$4e8d32fa43c9e317ce9432698918e086731017dd\$lut for cells of type $lut.
|
|
Using template $paramod$a6caec9711d278ba5af4777790b966231ccdef2b\$lut for cells of type $lut.
|
|
Using template $paramod$f28b38385f3bc966cba0c6456db77bbb9d340f6f\$lut for cells of type $lut.
|
|
Using template $paramod$c9f216188251ef5ed51f186fe6acb26e78b25401\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10111111101111111011111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101100010100110000000000000000 for cells of type $lut.
|
|
Using template $paramod$921818c1313f25571ca5b3848dd07078772f5b69\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111100110011001111000010101010 for cells of type $lut.
|
|
Using template $paramod$25fd2f7cceca851535c96a88f892d475e97f744e\$lut for cells of type $lut.
|
|
Using template $paramod$8a7f5eaea727907ddcf16fec28e94159e449abae\$lut for cells of type $lut.
|
|
Using template $paramod$42584bac8a6ec5f5974df36f6fd7cf4b2ccc9463\$lut for cells of type $lut.
|
|
Using template $paramod$6e08d0155720e79ddc685cfa57c167e36e6c39af\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
|
|
Using template $paramod$a705c26cff0f8117ddd80f190eb6e23bb94259d7\$lut for cells of type $lut.
|
|
Using template $paramod$f4e51b2eb7f1eab8ecf5416b399f0bf4062da8f5\$lut for cells of type $lut.
|
|
Using template $paramod$bc844b0e4005fd0975fd717dc6d76e4b110d84f6\$lut for cells of type $lut.
|
|
Using template $paramod$05702fd6b706d8c052cbeb35cd4efd2c9a954ab8\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1333248160 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1142743210 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=51318778 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=251723656 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011110101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=720900 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010011111111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111111111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=286326799 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000100 for cells of type $lut.
|
|
Using template $paramod$31a944f0c6934f915f24e075bcacadd2906c8e5f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=45007 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010111100001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110100111111110000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001111111110001000 for cells of type $lut.
|
|
Using template $paramod$65cfe8894e096bb1f33ee474581ebbf4b444710f\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101110111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=64243 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001111000000000000000000 for cells of type $lut.
|
|
Using template $paramod$ee6b461b37880aa10d4c54fde73451ba7c8590fc\$lut for cells of type $lut.
|
|
Using template $paramod$c10f8ff3ce8ba61b631ac99a3bd3bf62ef5029a3\$lut for cells of type $lut.
|
|
Using template $paramod$4a6a6fc29d43c29960398be636675da17b2c0ed1\$lut for cells of type $lut.
|
|
Using template $paramod$2f6ccd9b9e6bb736fb4a553c36570702bb450376\$lut for cells of type $lut.
|
|
Using template $paramod$888e6b80cb74ea76175ff063cc146053d264ab3c\$lut for cells of type $lut.
|
|
Using template $paramod$ff06bd949c854da7028aff054e56bed683c3590b\$lut for cells of type $lut.
|
|
Using template $paramod$8126cadabd2598b1050d9797ea3af493f13f013a\$lut for cells of type $lut.
|
|
Using template $paramod$395ec95414abb406b983139ce5854c644db5b669\$lut for cells of type $lut.
|
|
Using template $paramod$1a06fe9fab606595ff975d642f8f437dab4ed6c7\$lut for cells of type $lut.
|
|
Using template $paramod$89c0955fc6da2b8a359ca6b1ab9103008801f1d8\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
|
|
Using template $paramod$fd8f640d7902a01297f0b8bfc23650b65f5a0298\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010110011010010110100110010110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10010110011010010000000000000000 for cells of type $lut.
|
|
Using template $paramod$6154d1f8c1dddcc9400894bab9d0a6a3b8c4a215\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1403781120 for cells of type $lut.
|
|
Using template $paramod$d565ce5408ca9c8f11cace3ba7e9f33ff0d1f8ec\$lut for cells of type $lut.
|
|
Using template $paramod$fe7e7e7b90d04a6286b0d69e1af839648eb00912\$lut for cells of type $lut.
|
|
Using template $paramod$61e4486437803a5993ac78ee9f2b8ef6f0b358a6\$lut for cells of type $lut.
|
|
Using template $paramod$190e39eff20cc160d0eccd3728c5f17f7d5631e3\$lut for cells of type $lut.
|
|
Using template $paramod$f31afa3899580138bc1c4b660182113ee65bc063\$lut for cells of type $lut.
|
|
Using template $paramod$a7e0523b34516014512cf9fd48cbce52978bf22b\$lut for cells of type $lut.
|
|
Using template $paramod$6aad5d0c8187dd019eb99d613aae0b3266449b1f\$lut for cells of type $lut.
|
|
Using template $paramod$3d8ee6d0e9fcb50ffc5deebd30480c6e7397cd48\$lut for cells of type $lut.
|
|
Using template $paramod$c9533b695a0196f1bb125d899e1b0da26c5bd9ed\$lut for cells of type $lut.
|
|
Using template $paramod$854c386519996963891c77aa17499de075f38165\$lut for cells of type $lut.
|
|
Using template $paramod$2c0209e3609f96efdf7b38345fe95b8727f79504\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
|
|
Using template $paramod$ed9bb6393424beab8fce4c99a5eafe5616d6b3ed\$lut for cells of type $lut.
|
|
Using template $paramod$b838e1fbeac421e52b86a245954181888c53eaac\$lut for cells of type $lut.
|
|
Using template $paramod$b9fa55e71cf33bdca67e240c3f5241354996df97\$lut for cells of type $lut.
|
|
Using template $paramod$91facb31ca137e268e05ba6630aa3a4d3b66c38b\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=895614976 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=17563655 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2093610835 for cells of type $lut.
|
|
Using template $paramod$8a48363ad210b952ac56033fc7ef7991d39738eb\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=267325199 for cells of type $lut.
|
|
Using template $paramod$9f5d12b24cc05aa570b84e5278ff36fede67bbb8\$lut for cells of type $lut.
|
|
Using template $paramod$b1c9bbe4f1afb883e21ead118b1c5c0b565a78a1\$lut for cells of type $lut.
|
|
Using template $paramod$4cf368f161a4593842c1744e1bb1ff4cd50fe9f6\$lut for cells of type $lut.
|
|
Using template $paramod$9ac623eaf0db2434992b9c997966a624b9d7d2d8\$lut for cells of type $lut.
|
|
Using template $paramod$acc3e122949110a0f81c1a3298d4ff9f9fb7f016\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1771476585 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010101010100011110011000011 for cells of type $lut.
|
|
Using template $paramod$ffd4e596ef8433ccf3139ed7af2519b2773d6e4c\$lut for cells of type $lut.
|
|
Using template $paramod$be3b92fbaf6473662b7e2c180b7f5b2a090a5713\$lut for cells of type $lut.
|
|
Using template $paramod$08ee5261f46dde6a0dbef8762ed3e93e6d50b915\$lut for cells of type $lut.
|
|
Using template $paramod$3b7f478e5833af05484a20d80659353e3f4f13f6\$lut for cells of type $lut.
|
|
Using template $paramod$8207f8b4fdb6939f4073ea47acff9d1683477cd5\$lut for cells of type $lut.
|
|
Using template $paramod$be55ccd86dd7b862b2c101ccc7d9ed168aef1a35\$lut for cells of type $lut.
|
|
Using template $paramod$f78b94d6d780695d36c4b7c0863008a8e9508948\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111110111 for cells of type $lut.
|
|
Using template $paramod$41a195bbe852dab39d4c045602050254f696e77f\$lut for cells of type $lut.
|
|
Using template $paramod$259320e5783ade2f624f61fcfc7f6f2eed2087f2\$lut for cells of type $lut.
|
|
Using template $paramod$a9f284a72f8663925909c15cbc8612122c804539\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut.
|
|
Using template $paramod$af4bc40f966c8640c092a6d0e6aee14856d1efff\$lut for cells of type $lut.
|
|
Using template $paramod$a27f8f77f706e42bb3fe6e048d3c127f5d4bfd64\$lut for cells of type $lut.
|
|
Using template $paramod$3500c6f3140cb6c6ba21b23f425acb6affa8d8b5\$lut for cells of type $lut.
|
|
Using template $paramod$a678034d6d7e0ab9a4c98e60c9db10bfdd2874b5\$lut for cells of type $lut.
|
|
Using template $paramod$5f92fec3eae70f87c615945332fa3d8e68f6d27b\$lut for cells of type $lut.
|
|
Using template $paramod$b0a1561242a95f75797cf8967242af5cdde7d789\$lut for cells of type $lut.
|
|
Using template $paramod$128ce1bde42e69d9fc86181d5712305b98d3b754\$lut for cells of type $lut.
|
|
Using template $paramod$697cade088336de622b2bfacb080c69941df9915\$lut for cells of type $lut.
|
|
Using template $paramod$16746b7694e6301220991182a502cd9dabf3986f\$lut for cells of type $lut.
|
|
Using template $paramod$e3620856c1d1920dd8e7ae9f42478d2965263a42\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1101001010110100 for cells of type $lut.
|
|
Using template $paramod$9abd567e56fa5e5fe88aefab580dea7b3d3324a7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=3\LUT=8'10100011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001100111111000011110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2147450880 for cells of type $lut.
|
|
Using template $paramod$2a62dac7826b9a08133bd47a55dc0b5e41f149a5\$lut for cells of type $lut.
|
|
Using template $paramod$375214c7b5117c5ffc692301d3bfc3adf7ba486a\$lut for cells of type $lut.
|
|
Using template $paramod$72a09b8d749e8627d6e8fbc5547cc5f74ec2593d\$lut for cells of type $lut.
|
|
Using template $paramod$1af5c0ea24225ce6dcffc794e8b0d5673421f68f\$lut for cells of type $lut.
|
|
Using template $paramod$409b8ed74f33854445ed6b5c2b48a72f3dc159d7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1429995520 for cells of type $lut.
|
|
Using template $paramod$df1da0f3a63749a6f9e12dce8610a4acc8164f58\$lut for cells of type $lut.
|
|
Using template $paramod$653318e3327f56a4a3aea39122c1cf6d44ee4386\$lut for cells of type $lut.
|
|
Using template $paramod$9db2b9661f46ae8d0b2d473ec0d7eb300a7bdeb3\$lut for cells of type $lut.
|
|
Using template $paramod$ab90fcc79e113f6d74718a25ab99bcd3157525d7\$lut for cells of type $lut.
|
|
Using template $paramod$cfb80e9a34fb01b3c4960d899e8bb2b202134726\$lut for cells of type $lut.
|
|
Using template $paramod$f9c8e905771785fc255a9da9aff45351206f2f2a\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut.
|
|
Using template $paramod$696947a51850e6da448761d781cb51c8afb3acb1\$lut for cells of type $lut.
|
|
Using template $paramod$c4e7f5f592c8f97b37a0e66a4da657af0ee79bd7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'10101100000000000000000000000000 for cells of type $lut.
|
|
Using template $paramod$4d38589dcb5b885590f773d3e7d445576f29fa42\$lut for cells of type $lut.
|
|
Using template $paramod$ad01c6040978a7c452d07401b0279ae605bd2a09\$lut for cells of type $lut.
|
|
Using template $paramod$2af785e8308f6c5846637deab87114533cbc6345\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1011010011001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000100111110 for cells of type $lut.
|
|
Using template $paramod$a010f08fbe134c701eac809861e5e996b6973bbb\$lut for cells of type $lut.
|
|
Using template $paramod$335e4c04df963ec848c2dd2f290c8db147c756d8\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1442578432 for cells of type $lut.
|
|
Using template $paramod$d851afc2046ea3939120d53e3aab229f4b815232\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=935656200 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=15400960 for cells of type $lut.
|
|
Using template $paramod$bb3ed824561ec1add9d133e0062570f0118fd3af\$lut for cells of type $lut.
|
|
Using template $paramod$f4fcf8eea0162f5705cc8fea50081c19fabf6367\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut.
|
|
Using template $paramod$b488778af0cf015ab05c570d447d568e283440a8\$lut for cells of type $lut.
|
|
Using template $paramod$47c77eec59d744922cc267b746779bccdf46b18d\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1431649475 for cells of type $lut.
|
|
Using template $paramod$1f70474143bbd1b4a62002c2db8cc95e4417ad8c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1771438080 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111111111111100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut.
|
|
Using template $paramod$97aad1a5a0aa2d0f0ed8ff4f56b95faf85a78d61\$lut for cells of type $lut.
|
|
Using template $paramod$34317ee799fbdadaf2ea1dc53fd4ed359fdc0a58\$lut for cells of type $lut.
|
|
Using template $paramod$8bfbd25654fb1fdb27f80a770d28623c7fdc56a8\$lut for cells of type $lut.
|
|
Using template $paramod$64e2b6acb4f5cfabab599bd0e63ce33f0e679092\$lut for cells of type $lut.
|
|
Using template $paramod$35aefded8406e363761c148bf1cf9a5161d2b65d\$lut for cells of type $lut.
|
|
Using template $paramod$63cd27090e8c1b75c54f6041f2cea3b6c6b8059a\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111110 for cells of type $lut.
|
|
Using template $paramod$42bb1dd7f77894e185a11ce48b5b800eddb50058\$lut for cells of type $lut.
|
|
Using template $paramod$2376329f626f38a6e0e032540740c2e7c819b03f\$lut for cells of type $lut.
|
|
Using template $paramod$511d9f735175cc3069eb15c25acb1d913ea3db04\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110011101000101111001111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1065304064 for cells of type $lut.
|
|
Using template $paramod$6952ff4f60d2b4e360117e5aabe3d6b08ec8c7b2\$lut for cells of type $lut.
|
|
Using template $paramod$c55598bd13872d35f8cb1dddd29ace06a1fe3d24\$lut for cells of type $lut.
|
|
Using template $paramod$853f55aefe739080203ca41c02ff94dc577abd60\$lut for cells of type $lut.
|
|
Using template $paramod$47e61caa98ab6aae33deef127e14c3da39a9c1a2\$lut for cells of type $lut.
|
|
Using template $paramod$63a25241f15f64943b02d792d5055a9422021e8c\$lut for cells of type $lut.
|
|
Using template $paramod$5c74f7643ff2995432d9e7b6a689973cee1cbecb\$lut for cells of type $lut.
|
|
Using template $paramod$ab02e5f223dd112be17313a06c1babed10377b57\$lut for cells of type $lut.
|
|
Using template $paramod$f9b63f3154e99a94f6faac5eda298b275b76dc72\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=47787 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=11141315 for cells of type $lut.
|
|
Using template $paramod$2fcca62ca69081b8eec3b7124713e88cb552af35\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010000001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1157681103 for cells of type $lut.
|
|
Using template $paramod$b7ba790763a4deb53235f02e5b916048718f8121\$lut for cells of type $lut.
|
|
Using template $paramod$2596ca2ecc26558a8ecbc0477ed7227e7307589c\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1438842880 for cells of type $lut.
|
|
Using template $paramod$be3215e1cb0ef188af903f37a5ffa3224149a859\$lut for cells of type $lut.
|
|
Using template $paramod$4bb9b69111b5b0679e9afe2594746e2ab94dedaa\$lut for cells of type $lut.
|
|
Using template $paramod$6d638779c06d3f808fc946c5381db422a5a3ead7\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=60350 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000000100010000000000000000 for cells of type $lut.
|
|
Using template $paramod$22296b1688431e6a90f3d66cd7290faab93ad655\$lut for cells of type $lut.
|
|
Using template $paramod$0fba062221402bc99246b4486d35fbc6f2615914\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1761607680 for cells of type $lut.
|
|
Using template $paramod$c6a01b34e90b12211337e189a592f1c7d664dcc5\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32246844 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=65528 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11101011011100001111000011100000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110101010101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=66912256 for cells of type $lut.
|
|
Using template $paramod$488828f844c7be1332a09a452d6632f1c0c81e15\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111110101111000011110011 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11110111000010001110111100010000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001010101 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11001100000011001111111100001010 for cells of type $lut.
|
|
Using template $paramod$e11faa3ca83f0aa155697f785214d8cfc10c6cb3\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111100000000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110110000000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000011101111111111110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=2004287600 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001000110000 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16774399 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=4351 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=1438908415 for cells of type $lut.
|
|
Using template $paramod$23c4939173b7566da1c4f00a09d35c4be96e54c2\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=43962 for cells of type $lut.
|
|
Using template $paramod$c2021b5d3c6f7271f87242cb8f2cf003d0fee3b6\$lut for cells of type $lut.
|
|
Using template $paramod$2070fafaffa9581a47f6012d4f212c98eb568297\$lut for cells of type $lut.
|
|
Using template $paramod$128438b62abfc6a900b56e52d9db5e09fd5fa477\$lut for cells of type $lut.
|
|
Using template $paramod$294fd398194b17f985016d7985cb2641742477b6\$lut for cells of type $lut.
|
|
Using template $paramod$9342fa897d9621b6e9f5bd6af45df92f87820e1d\$lut for cells of type $lut.
|
|
Using template $paramod$1ae012fc7f6915a4dff902aedf383d93a9f0f6ab\$lut for cells of type $lut.
|
|
Using template $paramod$fde90ad7f2dd8707f0a3e6b461e6285931970676\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=16775423 for cells of type $lut.
|
|
Using template $paramod$74cd19171c6aa659e4b5c548b8ab5cb793e01ab8\$lut for cells of type $lut.
|
|
Using template $paramod$774f9748252cf67f956015d6c70fa533709d6535\$lut for cells of type $lut.
|
|
Using template $paramod\$lut\WIDTH=5\LUT=61199 for cells of type $lut.
|
|
Using template $paramod$02c3ef43f37121a6994d7a55e24d48dea59a68f5\$lut for cells of type $lut.
|
|
Using template $paramod$10d0868bf33ed5d8c0e8cad5ce5499c25c666069\$lut for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~12087 debug messages>
|
|
|
|
2.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in PQVexRiscvUlx3s.
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51837.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51871.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut3 (4 -> 2)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut5 (4 -> 0)
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|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut6 (4 -> 2)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51971.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51982.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51982.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51993.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51993.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52026.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52026.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut4 (4 -> 2)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut5 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut6 (4 -> 2)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut7 (4 -> 2)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut4 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut5 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut6 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut7 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut2 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut3 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut6 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52081.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52097.lut2 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52097.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52098.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52107.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52114.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut2 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52132.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut1 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut2 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut3 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut5 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52131.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52129.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52133.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52142.lut1 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52144.lut2 (4 -> 3)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52144.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52149.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52167.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52179.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52188.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52212.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52212.lut3 (4 -> 1)
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|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52205.lut2 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52205.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52207.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52218.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52218.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52223.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52223.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52227.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52215.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut1 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut6 (4 -> 3)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52220.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52225.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52234.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52234.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52234.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52237.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52240.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52240.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52245.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52263.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52263.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52273.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52273.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut5 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut6 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut7 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52278.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52278.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52283.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52283.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52294.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52294.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52295.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52323.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52323.lut2 (4 -> 3)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52323.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52324.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52366.lut1 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52334.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut1 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut3 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52335.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52361.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52361.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52371.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51872.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52384.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52388.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52388.lut3 (4 -> 2)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52389.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut1 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut4 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut5 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52401.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52406.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52406.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut2 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut3 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut4 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut5 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut6 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut7 (4 -> 0)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut2 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut3 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52430.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52430.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52426.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52073.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52073.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52073.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52431.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52435.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52449.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52458.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52461.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52461.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52482.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52470.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52483.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52477.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52474.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52479.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52487.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52487.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52488.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52501.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52490.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52498.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52516.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52516.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52510.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51720.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51720.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53653.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51021.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53208.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50981.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52966.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51153.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52954.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51150.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50973.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52529.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52542.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52542.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52542.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52535.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52535.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52537.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51112.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51116.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51124.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51110.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52540.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51113.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51114.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51117.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53260.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53260.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51100.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51100.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51145.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52563.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52563.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52574.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52574.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53380.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53375.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53370.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53365.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53359.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52709.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52550.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52550.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52564.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52564.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52588.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52588.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52518.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52349.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52349.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53262.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53262.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52916.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52912.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52890.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52886.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52873.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52867.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52821.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52809.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52754.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52316.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52317.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52308.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52311.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52705.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52571.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52573.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52559.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52559.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52559.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52560.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52555.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52229.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52546.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52546.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52219.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52547.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52492.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52495.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52475.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52444.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52008.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52418.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52393.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52358.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52326.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52326.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52329.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52321.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52313.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52301.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52251.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52251.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52252.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52248.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52241.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52241.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52181.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52181.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52183.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52156.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52151.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52151.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52154.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52116.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52123.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52105.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52090.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51962.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51952.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51952.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51939.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51939.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51940.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51892.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51892.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51893.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52584.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52584.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52584.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52602.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52602.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52029.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52029.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51804.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51804.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52598.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52598.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52279.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52593.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53496.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53496.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53496.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52613.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52613.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51628.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51628.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51628.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51627.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51630.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51630.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51630.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51630.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51552.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52615.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51695.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51695.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51695.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51695.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51694.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52622.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52627.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51147.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51127.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51111.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51107.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50963.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50963.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50915.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50915.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51842.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51842.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51844.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51850.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51850.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51850.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51850.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51848.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51848.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51857.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51857.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51859.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51859.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51859.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51859.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51860.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51860.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51855.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51855.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51855.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52640.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52634.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51807.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51807.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51807.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51810.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51810.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51810.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51814.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51814.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51814.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52135.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52135.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52135.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52639.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52639.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52642.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51884.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51884.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51884.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51884.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51885.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51885.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51885.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51885.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51886.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51886.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51886.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51889.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51889.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51889.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51890.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51890.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51890.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51890.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51882.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52647.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52644.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53493.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53493.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51909.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51909.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51911.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51911.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51911.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51911.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51912.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51910.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51910.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51906.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51906.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53594.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52673.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52667.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52691.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52685.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52717.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52721.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52738.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52730.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52734.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52746.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52742.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52762.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52758.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52767.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52771.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52775.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52814.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52790.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52795.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52802.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52833.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52819.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52882.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52823.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52827.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52839.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52829.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52844.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52835.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52850.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52840.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52856.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52842.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52846.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52848.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52852.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52863.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52854.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52858.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52869.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52874.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52860.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52865.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52870.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52871.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52901.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52876.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52879.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52888.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52880.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52675.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52883.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52884.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52896.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52885.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53203.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51768.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51768.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51779.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51777.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51777.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51777.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51778.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51643.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51643.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51643.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51774.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51589.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51589.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51589.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51590.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51590.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51590.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51591.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51591.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51588.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51588.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51588.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51592.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51592.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51560.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51561.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51561.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51561.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51556.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51555.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51555.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51555.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51557.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51557.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51558.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51558.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51558.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51096.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51096.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50929.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50929.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50959.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50959.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50959.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50891.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50891.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50895.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50895.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50899.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50899.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50866.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50866.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50847.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50859.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50312.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50843.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50849.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50845.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50835.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50909.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52909.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52902.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52894.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52905.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52898.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52788.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52789.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52899.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52917.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52903.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52907.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52910.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52914.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52926.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52684.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52683.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52919.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52932.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52928.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52943.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52937.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52716.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52934.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52949.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52935.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52939.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52950.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52941.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52726.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52726.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52726.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52945.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52956.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52961.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50969.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52952.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52967.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52958.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52763.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52763.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52959.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52963.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52974.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49628.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49628.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52969.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53381.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53358.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53362.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49961.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53363.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53364.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53368.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53373.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53382.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53374.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49814.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49814.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49599.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49861.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50818.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50818.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50796.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50796.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50786.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50786.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50752.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50752.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50742.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50742.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50720.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50720.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50698.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50698.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50925.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50925.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50955.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50955.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50955.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50941.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50941.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50933.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50933.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50688.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50688.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50668.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50668.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50618.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50618.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50330.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50326.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50579.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50579.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50316.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50308.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50535.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50296.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50130.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50130.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49501.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49501.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49501.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49484.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50117.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50519.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50292.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut6 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut7 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50281.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50937.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50937.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50945.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50945.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50678.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50678.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51772.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51772.lut4 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51772.lut5 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51619.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51619.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51619.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51621.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51621.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51618.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51618.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51618.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51623.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51623.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51620.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51620.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51620.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51599.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51599.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51599.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51597.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51597.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51597.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51602.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51602.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51602.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51610.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51610.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51615.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51615.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51615.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51611.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51611.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut6 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut2 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut5 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51603.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51603.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut7 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut3 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut4 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut6 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut7 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51764.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51764.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51562.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51760.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51760.lut2 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51760.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51761.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51563.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51563.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51563.lut3 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51763.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51763.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut2 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut4 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut5 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut7 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut2 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut3 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut4 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut5 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut6 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49545.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49545.lut3 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52785.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50113.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49481.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49482.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49492.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49507.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49530.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49532.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49541.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49543.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49545.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49548.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49552.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49559.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49564.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49577.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49583.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49577.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52780.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52977.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49599.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50350.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52713.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49605.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49610.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49612.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49614.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49620.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49621.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49622.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49628.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49634.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49639.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49645.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49645.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49649.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49656.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49599.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49676.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49722.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51791.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49739.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49740.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49745.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49749.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49763.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49767.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49791.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49811.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49803.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49804.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49805.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49807.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49812.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49814.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49815.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49951.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49819.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49820.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49822.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49823.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49820.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49822.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49844.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49848.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49858.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49872.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49879.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49882.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49894.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49905.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49934.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49949.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49949.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49951.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52878.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49845.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52965.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49536.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49961.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50562.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50498.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50111.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52892.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50103.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50103.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50105.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50105.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50107.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50107.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50109.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50111.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50113.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50115.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50115.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50117.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50109.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50128.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49747.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50130.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50147.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50152.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50156.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50160.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50546.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50164.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50168.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50172.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50176.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50180.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50184.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50188.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50192.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50196.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50200.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50204.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50208.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50216.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50220.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50688.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50224.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50228.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50232.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50236.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50240.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50244.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50248.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50252.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50256.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50260.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50264.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50281.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50285.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50285.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50288.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50291.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50291.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50292.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50295.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50295.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50296.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50299.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50299.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50300.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50303.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50303.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50304.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50554.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50307.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50307.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50308.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50311.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50311.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50312.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50860.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50315.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50315.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50316.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50322.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50326.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50330.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53743.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50334.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50338.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50346.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50342.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50338.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50334.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50346.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50347.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50350.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50356.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50342.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50359.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50362.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50365.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50368.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50371.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50374.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50377.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50380.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50383.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50386.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50389.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50392.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50395.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50398.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50402.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50405.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50408.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50411.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50300.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50414.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50417.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50420.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50423.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50426.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50429.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50432.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50435.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50438.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50441.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50444.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50447.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50450.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50453.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50456.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50459.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50462.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50708.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50465.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50468.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50471.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50474.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50477.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50480.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50483.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50486.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50489.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50806.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50492.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50495.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50497.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50498.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50506.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50512.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50515.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50519.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50525.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50288.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50526.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50527.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50527.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50535.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50518.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50546.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50534.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50554.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50304.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50570.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50562.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50553.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50569.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50570.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50573.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50561.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50579.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50579.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50322.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50606.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50597.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50618.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50618.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53740.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50628.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50637.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50646.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50656.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50668.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50656.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50545.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50668.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50678.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50678.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50688.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53734.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50698.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50698.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50708.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50720.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50720.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50730.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50730.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50742.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50742.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50933.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50752.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50752.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50762.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50762.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50774.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50774.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50786.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50786.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50796.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50818.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50826.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50827.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50835.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50842.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50844.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50846.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50847.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50852.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50852.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50856.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50848.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50859.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50860.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50863.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50866.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50871.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50871.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50875.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50875.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50879.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50879.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50884.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50884.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50891.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50891.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50903.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50888.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50895.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50895.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50899.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50899.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50903.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50909.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50915.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52626.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52908.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50919.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50915.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50919.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50925.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50929.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50933.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53129.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50937.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50941.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50945.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50949.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50949.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50955.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52443.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50959.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53303.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50963.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50966.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50963.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50969.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50971.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50973.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50975.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50971.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50977.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50979.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50975.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50981.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53260.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50983.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50979.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50985.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50987.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50983.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50989.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50991.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50987.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50993.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50995.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50991.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50997.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50999.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50995.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51001.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51003.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50999.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51005.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51007.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51003.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51009.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51011.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51007.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51013.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51015.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51011.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51017.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51019.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51015.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51021.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51023.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51019.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51025.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51023.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51001.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53367.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51005.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51017.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52947.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51072.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50993.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52904.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51096.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53361.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51101.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51103.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51106.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51106.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51107.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51108.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51109.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51110.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51111.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51112.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51113.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51114.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51115.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51116.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51117.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51118.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51115.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51121.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51124.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51127.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51130.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51131.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51131.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51135.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51138.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51135.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51141.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53201.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51144.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51145.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52831.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51147.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51148.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51149.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51150.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51151.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51152.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51153.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51151.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52972.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52920.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51013.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51720.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51009.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53385.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53197.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53262.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52701.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53652.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50985.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51025.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50989.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53377.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53376.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52522.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52526.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51097.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51420.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51420.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52593.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51144.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52837.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53378.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51516.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51148.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51503.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53379.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51511.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53383.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51149.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53386.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51542.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51639.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51753.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51551.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51909.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51556.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51555.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51556.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51557.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51558.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51560.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51560.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51561.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51562.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51563.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51564.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51566.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51567.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51568.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51569.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51572.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51562.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51587.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51588.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51589.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51590.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51591.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51592.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51593.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51594.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51595.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51596.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51597.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51598.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51599.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51600.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51601.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51602.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51603.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51604.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51605.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51606.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51607.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51608.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51609.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51610.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51611.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51612.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51613.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51614.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51615.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51616.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51617.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51618.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51619.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51620.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51621.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51622.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51623.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51624.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51625.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51627.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51628.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51631.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51638.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51640.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51641.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51642.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51644.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51645.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51647.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51655.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53095.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51655.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51658.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51738.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51658.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52331.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51661.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51661.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51663.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51663.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51665.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51665.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51671.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51671.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51673.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51673.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51676.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51676.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51680.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51680.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51683.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51683.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51685.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51685.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51691.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51702.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51702.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51704.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51704.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51707.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51707.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51709.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51709.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51713.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51713.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52633.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51716.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51716.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51719.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51719.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50977.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51723.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51732.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51732.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51734.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51734.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51736.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51736.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51738.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51121.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52568.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51743.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51750.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51743.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51752.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51754.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51757.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51758.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51759.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51760.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51761.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51762.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51763.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51764.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51765.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51766.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51767.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51768.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51769.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51771.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51773.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51784.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51784.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51786.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51786.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51789.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51789.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51791.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51792.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52624.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51804.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51807.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51808.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51810.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51812.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51813.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51817.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51823.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51823.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51825.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51825.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51827.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51827.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51830.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51830.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51749.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51840.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51841.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51846.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51850.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51851.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51852.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51853.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51855.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51856.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51857.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51858.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51860.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51871.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51900.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51865.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51865.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51871.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51879.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51881.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51883.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51886.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51887.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51889.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51891.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51893.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52595.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51903.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51909.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51910.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51911.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51916.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51920.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51934.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51928.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51950.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51939.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51942.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51949.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51953.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51972.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51960.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52631.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51965.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51982.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51975.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51983.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52231.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51993.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51995.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52006.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51994.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52005.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52008.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52026.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52014.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52018.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52022.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52026.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52029.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52027.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52036.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52040.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52037.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52046.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52039.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52058.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52071.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52059.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52070.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52081.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52073.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52080.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52081.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52092.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52092.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52097.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52089.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52106.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52109.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52115.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52118.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52118.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52124.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52125.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52135.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52141.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52144.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52144.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52150.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52151.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52153.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52155.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52163.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52158.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52650.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52165.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52175.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52171.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52164.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52178.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52185.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52181.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52182.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52192.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52212.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52203.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52205.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51928.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52218.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52212.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51108.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52218.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52210.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52223.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52233.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52228.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52229.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52556.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52234.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52240.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52241.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52246.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52247.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52250.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52251.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52255.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52258.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52263.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52263.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52260.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52269.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52278.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52273.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52265.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52278.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52279.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52283.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52284.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52275.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52280.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52289.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52290.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52294.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52291.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52304.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52302.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52303.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52306.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52307.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52310.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52310.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52315.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52320.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52312.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52323.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52325.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52326.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52328.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52330.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52750.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52333.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52344.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52355.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52357.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52360.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52361.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52374.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52402.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52371.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52371.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52372.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52379.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52380.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52388.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52388.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52392.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52396.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52397.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52406.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51986.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52411.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52412.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52407.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52421.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52424.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52417.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52430.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52430.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52434.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52438.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52448.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52453.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52677.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52452.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52467.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52457.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52461.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52463.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52468.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52469.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52472.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52473.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52474.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52478.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52487.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52481.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52486.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52487.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52501.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52491.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52492.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52492.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52494.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52496.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52497.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52501.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52502.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52500.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52533.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52508.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52513.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52516.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52514.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52861.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52529.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52543.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52535.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52542.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52546.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52550.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52552.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52554.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52546.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52559.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50966.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52563.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52564.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51130.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52569.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52570.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52574.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52578.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52610.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52581.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52029.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52584.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52588.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52050.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52585.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52593.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52062.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52598.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52590.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52602.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52603.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52599.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52608.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52609.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52613.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52619.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52620.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52621.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52625.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52626.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52629.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52630.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52125.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52639.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52635.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52638.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52639.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52643.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52644.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52646.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52648.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52649.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52652.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52644.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52656.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52662.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52662.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52665.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52666.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52667.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52672.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52673.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52676.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52677.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52678.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52683.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52685.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52690.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52691.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52695.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52701.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52705.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52708.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52709.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52713.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52717.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52721.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52726.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52730.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52734.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52738.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52742.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52746.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52750.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52754.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52758.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52762.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52763.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52767.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52771.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52775.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52780.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52785.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52790.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52795.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52797.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52797.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52971.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52802.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52804.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52804.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52809.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52814.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52819.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52821.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52823.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52825.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52678.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52827.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52829.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52831.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52833.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52835.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52837.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52839.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52840.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52842.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52844.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52846.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52848.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52850.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52852.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52854.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52856.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52858.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52860.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52861.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52863.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52865.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52867.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52869.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52870.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52871.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52873.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52874.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52876.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52878.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52879.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52883.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52884.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52885.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52886.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52888.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52890.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52892.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52894.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52895.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52896.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52897.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52898.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52899.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52903.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52904.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52905.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52763.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52907.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52910.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52912.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52914.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52916.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52917.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52919.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52920.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52921.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52923.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52925.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52926.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52928.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52930.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52932.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52934.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52935.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52936.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52937.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52939.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52941.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52943.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52945.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52947.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52949.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52950.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52952.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52954.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52956.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52958.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52959.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52961.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52963.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52965.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52966.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52967.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52969.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52971.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52972.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52974.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51503.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52987.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52989.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52996.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53000.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53004.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53007.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53010.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53013.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53016.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53020.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53027.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53360.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53031.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53372.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53038.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53041.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53044.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51152.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53047.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50588.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53065.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53067.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52925.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52598.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49823.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51775.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52520.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53096.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52517.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53097.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53745.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51118.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52895.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53202.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53366.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53151.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51109.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53185.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53189.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53190.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53192.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53194.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53196.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53197.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53198.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53199.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53201.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53202.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53203.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53204.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53207.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53208.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53209.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53210.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53212.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53214.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53216.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53218.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53220.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53222.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53224.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53226.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53228.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53230.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53232.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53234.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53236.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53238.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53240.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50945.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53251.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53252.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53254.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53256.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53257.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53258.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53260.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53262.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53264.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53266.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53268.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52349.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53270.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53272.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53274.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53276.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53278.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50925.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53280.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53282.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53284.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50937.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53286.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50941.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53288.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53290.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53292.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53294.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53296.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53301.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53303.lut0 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53309.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53310.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52654.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53318.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53320.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53322.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53324.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53326.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53328.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53330.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53332.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52921.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53334.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53336.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53338.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53341.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53345.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53357.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53358.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53359.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53360.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53361.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53362.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53363.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53364.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53365.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53366.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53367.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53368.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53369.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53370.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53371.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53372.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53373.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53374.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53375.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53376.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53377.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53378.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53379.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53380.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53381.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53382.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53383.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53384.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53385.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53386.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52575.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51138.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50997.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52930.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$49961.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53357.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52897.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53371.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52695.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53369.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53161.lut1 (4 -> 2)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53151.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53384.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51939.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53494.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53496.lut0 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53493.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51770.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52936.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52825.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53207.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51755.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53198.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53209.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53196.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51688.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52354.lut1 (4 -> 0)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53592.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53594.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53620.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53620.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53625.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53625.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53652.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53653.lut0 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53592.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53678.lut1 (4 -> 3)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53678.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53747.lut1 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53692.lut0 (4 -> 1)
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53732.lut1 (4 -> 1)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$52923.lut1 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53715.lut1 (4 -> 1)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53715.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53299.lut1 (4 -> 0)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53721.lut1 (4 -> 1)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53721.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$51141.lut1 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53727.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$50929.lut1 (4 -> 1)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53732.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53734.lut0 (4 -> 3)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53737.lut1 (4 -> 1)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53737.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53692.lut1 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53740.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53743.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53745.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53747.lut0 (4 -> 3)
|
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Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53727.lut1 (4 -> 1)
|
|
Optimizing lut $abc$49472$auto$blifparse.cc:498:parse_blif$53300.lut1 (4 -> 2)
|
|
Removed 0 unused cells and 9893 unused wires.
|
|
|
|
2.47. Executing AUTONAME pass.
|
|
Renamed 425637 objects in module PQVexRiscvUlx3s (228 iterations).
|
|
<suppressed ~21724 debug messages>
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|
|
|
2.48. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
2.48.1. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
|
|
2.48.2. Analyzing design hierarchy..
|
|
Top module: \PQVexRiscvUlx3s
|
|
Removed 0 unused modules.
|
|
|
|
2.49. Printing statistics.
|
|
|
|
=== PQVexRiscvUlx3s ===
|
|
|
|
Number of wires: 10766
|
|
Number of wire bits: 39142
|
|
Number of public wires: 10766
|
|
Number of public wire bits: 39142
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 13559
|
|
CCU2C 236
|
|
DP16KD 192
|
|
L6MUX21 850
|
|
LUT4 7300
|
|
MULT18X18D 4
|
|
PFUMX 2138
|
|
TRELLIS_DPR16X4 38
|
|
TRELLIS_FF 2801
|
|
|
|
2.50. Executing CHECK pass (checking for obvious problems).
|
|
Checking module PQVexRiscvUlx3s...
|
|
Found and reported 0 problems.
|
|
|
|
2.51. Executing JSON backend.
|
|
|
|
Warnings: 1 unique messages, 2 total
|
|
End of script. Logfile hash: 9e6320c69d, CPU: user 30.00s system 0.39s, MEM: 887.88 MB peak
|
|
Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os)
|
|
Time spent: 28% 1x autoname (10 sec), 16% 1x abc (5 sec), ...
|