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@ -18,30 +18,14 @@ class MyMem() extends Component { |
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val bus = slave(Apb3(MyMem.getApb3Config)) |
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} |
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// Define a bundle "mapMem" for the state and the status |
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// case object mapMem extends Bundle { |
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// val state = Reg(Bits(128 bit)) |
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// val key = Reg(Bits(128 bit)) |
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// val status = Reg(Bits(32 bit)) |
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// } |
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// Create the AES Core from the library spinalCrypto |
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val aesCore = new AESCore_Std(128 bits) |
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// Create a BusslaveFactory on the io.bus |
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val busCtrl = Apb3SlaveFactory(io.bus) |
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// Drive the AES Core bus from the mem-mapped Vexriscv bus at |
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// the address 0x30000. See the c code struct for the layout of |
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// the memory. |
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aesCore.io.driveFrom(busCtrl,baseAddress=0x30000) |
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// Register the bundle "myReg" to the BusSlaveFactory at address 0x30000 |
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// busCtrl.readMultiWord(aesCore.io.rsp,address = 0x30000) |
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// busCtrl.writeMultiWord(aesCore.io.cmd,address = 0x30000) |
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// When state and key are loaded, the status becomes 1 |
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// and the calculation can start (state = state XOR key). |
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// After the calcualtion is finished, the status is set to 0. |
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// when (mapMem.status === 1){ |
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// mapMem.state := mapMem.state ^ mapMem.key |
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// mapMem.status := 0 |
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// } |
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} |