A VexRiscv with AES128 on the memory mapped bus. Works in simulation and on the ULX3S.
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4 years ago
  1. ThisBuild / organization := "mupq"
  2. ThisBuild / scalaVersion := "2.11.12"
  3. lazy val pqvexriscv = (project in file("."))
  4. .settings(
  5. name := "pqvexriscv",
  6. version := "0.1",
  7. libraryDependencies ++= Seq(
  8. "org.scalatest" %% "scalatest" % "3.0.5" % "test",
  9. compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % "1.4.0"),
  10. "com.github.spinalhdl" % "spinalhdl-crypto_2.11" % "latest.release"
  11. ),
  12. run / connectInput := true,
  13. outputStrategy := Some(StdoutOutput),
  14. ).dependsOn(vexRiscv)
  15. lazy val vexRiscv = RootProject(uri("git://github.com/SpinalHDL/VexRiscv#2942d0652a89646c5225bee15dd55cc3b0871766"))
  16. fork := true