From eae126e7714fa473867b7a399f0642b42fe6dda9 Mon Sep 17 00:00:00 2001 From: Thorsten Knoll Date: Wed, 27 Jan 2021 14:54:11 +0100 Subject: [PATCH] cleaned project for C in sim and ulx3s --- c_project/Makefile | 140 - .../bsp/vexriscv/Makefile | 0 c_project/{ => bsp}/vexriscv/init.c | 0 .../bsp/vexriscv/libpqvexriscvup5kbsp.a | Bin .../bsp/vexriscv/main.c | 0 .../bsp/vexriscv/murax.ld | 0 c_project/{ => bsp/vexriscv}/nonvolatile.ld | 0 .../bsp/vexriscv/pqvexriscvicoboard.ld | 0 .../bsp/vexriscv/pqvexriscvsim.ld | 0 .../bsp/vexriscv/pqvexriscvsimhuge.ld | 0 .../bsp/vexriscv/pqvexriscvup5k.ld | 0 .../bsp/vexriscv/pqvexriscvup5k_init.o | Bin .../bsp/vexriscv/pqvexriscvup5k_start.o | Bin c_project/{ => bsp}/vexriscv/start.S | 0 .../{ => bsp}/vexriscv/volatile-split.ld | 0 .../bsp/vexriscv/volatile.ld | 0 .../{ => bsp}/vexriscv/weak_under_alias.h | 0 .../compile_command.txt | 0 c_project/crt.S | 97 - c_project/crt.o | Bin 548 -> 0 bytes c_project/hal-vexriscv.o | Bin 10060 -> 0 bytes c_project/hal.o | Bin 5760 -> 0 bytes c_project/libpqvexriscvsimbsp.a | Bin 3726 -> 0 bytes .../libpqvexriscvup5kbsp.a | Bin {c_project_sim_and_ulx3s => c_project}/main.d | 0 .../main.elf | Bin 41844 -> 41872 bytes c_project/main.o | Bin 5652 -> 0 bytes c_project/memcmp.o | Bin 4984 -> 0 bytes c_project/memcpy.o | Bin 15680 -> 0 bytes c_project/memset.o | Bin 5176 -> 0 bytes c_project/pqvexriscvsim.ld | 14 - .../pqvexriscvup5k.ld | 0 c_project/printf.o | Bin 128024 -> 0 bytes c_project/vexriscv/nonvolatile.ld | 141 - c_project/vexriscv/pqvexriscvsim.ld | 14 - c_project/vexriscv/pqvexriscvsim_init.o | Bin 756 -> 0 bytes c_project/vexriscv/pqvexriscvsim_start.o | Bin 2576 -> 0 bytes c_project/vexriscv/vexriscv.mk | 45 - c_project_sim_and_ulx3s/bsp/vexriscv/init.c | 8 - .../bsp/vexriscv/nonvolatile.ld | 141 - c_project_sim_and_ulx3s/bsp/vexriscv/start.S | 156 - .../bsp/vexriscv/volatile-split.ld | 137 - .../bsp/vexriscv/weak_under_alias.h | 7 - c_project_sim_and_ulx3s/hal-vexriscv.c | 60 - c_project_sim_and_ulx3s/hal.c | 21 - c_project_sim_and_ulx3s/hal.h | 18 - c_project_sim_and_ulx3s/main.c | 29 - c_project_sim_and_ulx3s/memcmp.c | 16 - c_project_sim_and_ulx3s/memcpy.c | 61 - c_project_sim_and_ulx3s/memset.c | 64 - c_project_sim_and_ulx3s/printf.c | 987 - c_project_sim_and_ulx3s/printf.h | 121 - c_project_sim_and_ulx3s/volatile-split.ld | 137 - ulx3s/Makefile | 32 + ulx3s/PQVexRiscvUlx3s.bit | Bin 0 -> 2076077 bytes ulx3s/PQVexRiscvUlx3s.config | 145708 +++++++++ ulx3s/PQVexRiscvUlx3s.json | 241497 +++++++++++++++ ulx3s/PQVexRiscvUlx3s.v | 8225 + ulx3s/PQVexRiscvUlx3s.ys | 2 + ulx3s/PQVexRiscvUlx3s_yosys.log | 7803 + ulx3s/ulx3s_v20_constraints.lpf | 452 + vexriscv/PQVexRiscvUlx3s.v | 8225 + .../{mupq => quantumrisc}/MulPlugins.scala | 2 +- .../scala/{mupq => quantumrisc}/MyMem.scala | 2 +- .../{mupq => quantumrisc}/PQVexRiscv.scala | 2 +- .../{mupq => quantumrisc}/PQVexRiscvSim.scala | 4 +- .../scala/quantumrisc/PQVexRiscvUlx3s.scala | 98 + vexriscv/tf2323h_openocd.cfg | 19 + 68 files changed, 412066 insertions(+), 2419 deletions(-) delete mode 100644 c_project/Makefile rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/Makefile (100%) rename c_project/{ => bsp}/vexriscv/init.c (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/libpqvexriscvup5kbsp.a (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/main.c (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/murax.ld (100%) rename c_project/{ => bsp/vexriscv}/nonvolatile.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvicoboard.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvsim.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvsimhuge.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvup5k.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvup5k_init.o (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/pqvexriscvup5k_start.o (100%) rename c_project/{ => bsp}/vexriscv/start.S (100%) rename c_project/{ => bsp}/vexriscv/volatile-split.ld (100%) rename {c_project_sim_and_ulx3s => c_project}/bsp/vexriscv/volatile.ld (100%) rename c_project/{ => bsp}/vexriscv/weak_under_alias.h (100%) rename {c_project_sim_and_ulx3s => c_project}/compile_command.txt (100%) delete mode 100644 c_project/crt.S delete mode 100644 c_project/crt.o delete mode 100644 c_project/hal-vexriscv.o delete mode 100644 c_project/hal.o delete mode 100644 c_project/libpqvexriscvsimbsp.a rename {c_project_sim_and_ulx3s => c_project}/libpqvexriscvup5kbsp.a (100%) rename {c_project_sim_and_ulx3s => c_project}/main.d (100%) rename {c_project_sim_and_ulx3s => c_project}/main.elf (83%) delete mode 100644 c_project/main.o delete mode 100644 c_project/memcmp.o delete mode 100644 c_project/memcpy.o delete mode 100644 c_project/memset.o delete mode 100644 c_project/pqvexriscvsim.ld rename {c_project_sim_and_ulx3s => c_project}/pqvexriscvup5k.ld (100%) delete mode 100644 c_project/printf.o delete mode 100644 c_project/vexriscv/nonvolatile.ld delete mode 100644 c_project/vexriscv/pqvexriscvsim.ld delete mode 100644 c_project/vexriscv/pqvexriscvsim_init.o delete mode 100644 c_project/vexriscv/pqvexriscvsim_start.o delete mode 100644 c_project/vexriscv/vexriscv.mk delete mode 100644 c_project_sim_and_ulx3s/bsp/vexriscv/init.c delete mode 100644 c_project_sim_and_ulx3s/bsp/vexriscv/nonvolatile.ld delete mode 100644 c_project_sim_and_ulx3s/bsp/vexriscv/start.S delete mode 100644 c_project_sim_and_ulx3s/bsp/vexriscv/volatile-split.ld delete mode 100644 c_project_sim_and_ulx3s/bsp/vexriscv/weak_under_alias.h delete mode 100644 c_project_sim_and_ulx3s/hal-vexriscv.c delete mode 100644 c_project_sim_and_ulx3s/hal.c delete mode 100644 c_project_sim_and_ulx3s/hal.h delete mode 100644 c_project_sim_and_ulx3s/main.c delete mode 100644 c_project_sim_and_ulx3s/memcmp.c delete mode 100644 c_project_sim_and_ulx3s/memcpy.c delete mode 100644 c_project_sim_and_ulx3s/memset.c delete mode 100644 c_project_sim_and_ulx3s/printf.c delete mode 100644 c_project_sim_and_ulx3s/printf.h delete mode 100644 c_project_sim_and_ulx3s/volatile-split.ld create mode 100644 ulx3s/Makefile create mode 100644 ulx3s/PQVexRiscvUlx3s.bit create mode 100644 ulx3s/PQVexRiscvUlx3s.config create mode 100644 ulx3s/PQVexRiscvUlx3s.json create mode 100644 ulx3s/PQVexRiscvUlx3s.v create mode 100644 ulx3s/PQVexRiscvUlx3s.ys create mode 100644 ulx3s/PQVexRiscvUlx3s_yosys.log create mode 100644 ulx3s/ulx3s_v20_constraints.lpf create mode 100644 vexriscv/PQVexRiscvUlx3s.v rename vexriscv/src/main/scala/{mupq => quantumrisc}/MulPlugins.scala (99%) rename vexriscv/src/main/scala/{mupq => quantumrisc}/MyMem.scala (98%) rename vexriscv/src/main/scala/{mupq => quantumrisc}/PQVexRiscv.scala (99%) rename vexriscv/src/main/scala/{mupq => quantumrisc}/PQVexRiscvSim.scala (98%) create mode 100644 vexriscv/src/main/scala/quantumrisc/PQVexRiscvUlx3s.scala create mode 100644 vexriscv/tf2323h_openocd.cfg diff --git a/c_project/Makefile b/c_project/Makefile deleted file mode 100644 index 2ca229c..0000000 --- a/c_project/Makefile +++ /dev/null @@ -1,140 +0,0 @@ -# Color definitions ------------------------------- - -NO_COLOR="\033[0m" -RED="\033[38;5;009m" -GREEN="\033[38;5;010m" -YELLOW="\033[38;5;011m" -ORANGE="\033[38;5;214m" -LIGHTPURPLE="\033[38;5;177m" -PURPLE="\033[38;5;135m" -CYAN="\033[38;5;014m" -LIGHTBLUE="\033[38;5;39m" -BLUE="\033[38;5;75m" -DARKBLUE="\033[38;5;33m" -LIGHTGRAY="\033[38;5;252m" -DARKGRAY="\033[38;5;242m" -BRIGHTRED="\033[91m" -BOLD="\033[1m" - -# PATHS (adapt to your system)---------------------- - -PATH_RISCV=/opt/riscv/ -PATH_RISC_BIN=$(PATH_RISCV)bin/ -PATH_VERILATOR_BIN?=/usr/local/bin/verilator -PREFIX?=$(PATH_RISC_BIN)riscv64-unknown-elf - -# TOOLS -------------------------------------------- - -AR?=$(PREFIX)-ar -GCC?=$(PREFIX)-gcc -CLANG=clang -GDB?=$(PREFIX)-gdb -OBJDUMP?=$(PREFIX)-objdump -OBJCOPY?=$(PREFIX)-objcopy -RISCVPATH=$(PATH_RISCV)riscv64-unknown-elf -OPENOCD?=$(PATH_RISC_BIN)openocd -ECHO?=echo - -# GCC FLAGS --------------------------------------- - -CC=$(GCC) - -GCC_CFLAGS_COMMON := -g \ - -O3 \ - -fno-builtin-printf \ - -Wno-unused-parameter \ - -Wall -Wextra -Wredundant-decls \ - -Wshadow -Wno-unused-function \ - -fno-common \ - -I$(RISCVPATH)/include - -GCC_CFLAGS_MURAX=-fstrict-volatile-bitfields --specs=nosys.specs - -RISCV_ARCH?=rv32im -RISCV_ABI?=ilp32 -RISCV_CMODEL?=medany -RISCV_ARCHFLAGS +=-march=$(RISCV_ARCH) -RISCV_ARCHFLAGS +=-mabi=$(RISCV_ABI) -RISCV_ARCHFLAGS +=-mcmodel=$(RISCV_CMODEL) -GCC_RISCV_ARCHFLAGS=$(RISCV_ARCHFLAGS) - -CFLAGS += $(GCC_CFLAGS_COMMON) \ - $(GCC_CFLAGS_MURAX) \ - $(GCC_RISCV_ARCHFLAGS) - -# Linker flags -------------------------------------- - -PLATFORM ?= pqvexriscvsim - -LDSCRIPT = $(PLATFORM).ld -LDFLAGS = -L$(RISCVPATH)/lib/rv32imac/ilp32 -LDFLAGS += $(GCC_RISCV_ARCHFLAGS) -LDFLAGS += --specs=nosys.specs -LDFLAGS += -Wl,-T$(LDSCRIPT) -LDFLAGS += -nostartfiles -ffreestanding -Wl,--gc-sections -LDFLAGS += -L. -LDFLAGS += -Wl,--start-group -l$(PLATFORM)bsp -lc -Wl,--end-group - -# Object files -------------------------------------- - -SDK_ASM_SRCS := $(wildcard *.S) -SDK_C_SRCS := $(wildcard *.c) -SDK_C_OBJS := $(SDK_C_SRCS:.c=.o) -SDK_ASM_OBJS := $(SDK_ASM_SRCS:.S=.o) -SDK_OBJS := $(SDK_C_OBJS) $(SDK_ASM_OBJS) - -# Target all ---------------------------------------- - -.PHONY: all -all: main.hex main.bin - -# LIBWRAP - -include vexriscv/vexriscv.mk - -# Targets -------------------------------------------- - -main.bin: main - @$(ECHO) $(PURPLE)"obj "$@""$(LIGHTGRAY) - $(OBJCOPY) -O binary $< $@ - -main.hex: main - @$(ECHO) $(PURPLE)"obj "$@""$(LIGHTGRAY) - $(OBJCOPY) -O ihex $< $@ - -main: $(LIBWRAP) $(SDK_OBJS) $(LDSCRIPT) - @$(ECHO) $(LIGHTPURPLE)"building "$@""$(LIGHTGRAY) - $(GCC) $(GCC_RISCV_ARCHFLAGS) $(GCC_CFLAGS_COMMON) $(SDK_OBJS) -o $@ $(LDFLAGS) - -%.o: %.S - @$(ECHO) $(ORANGE)"building "$@" (.S)"$(LIGHTGRAY) - $(CC) $(CFLAGS) -c -o $@ $^ - -%.o: %.c - @$(ECHO) $(ORANGE)"building "$@" (.c)"$(LIGHTGRAY) - $(CC) $(CFLAGS) -c -o $@ $^ - -.PHONY: clean -clean: - @$(ECHO) $(RED)"cleaning..."$(LIGHTGRAY) - rm -f main main.bin main.hex $(SDK_OBJS) $(LIBWRAP_OBJS) $(LIBWRAP) - -help: - @$(ECHO) $(RED)"Compile & Simulate"$(LIGHTGRAY) - @$(ECHO) $(LIGHTGRAY)"1. "$(CYAN)"make"$(LIGHTGRAY) - @$(ECHO) $(LIGHTGRAY)"2. open 3 terminals"$(LIGHTGRAY) - @$(ECHO) $(LIGHTGRAY)"3. Terminal 2: "$(CYAN)"make startsim"$(LIGHTGRAY) - @$(ECHO) $(LIGHTGRAY)"4. Terminal 3: "$(CYAN)"make openocd"$(LIGHTGRAY) - @$(ECHO) $(LIGHTGRAY)"5. Terminal 1: "$(CYAN)"make flash"$(LIGHTGRAY) - -# Targets for starting simulation, openocd and gdb ---------------------------- - -# startsim: -# cd ../Building_Tools/pqriscv-vexriscv/ ; sbt "runMain mupq.PQVexRiscvSim --ram 256,128" - -# openocd: -# cd ../Building_Tools/pqriscv-vexriscv/ ; /opt/verilator/bin/openocd --file pqvexriscvsim.cfg - -#flash: -# /opt/riscv/bin/riscv64-unknown-elf-gdb -ex 'set remotetimeout 15' -ex 'target remote :3333' -ex 'load' -ex 'break main' -ex 'continue' main - diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/Makefile b/c_project/bsp/vexriscv/Makefile similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/Makefile rename to c_project/bsp/vexriscv/Makefile diff --git a/c_project/vexriscv/init.c b/c_project/bsp/vexriscv/init.c similarity index 100% rename from c_project/vexriscv/init.c rename to c_project/bsp/vexriscv/init.c diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/libpqvexriscvup5kbsp.a b/c_project/bsp/vexriscv/libpqvexriscvup5kbsp.a similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/libpqvexriscvup5kbsp.a rename to c_project/bsp/vexriscv/libpqvexriscvup5kbsp.a diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/main.c b/c_project/bsp/vexriscv/main.c similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/main.c rename to c_project/bsp/vexriscv/main.c diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/murax.ld b/c_project/bsp/vexriscv/murax.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/murax.ld rename to c_project/bsp/vexriscv/murax.ld diff --git a/c_project/nonvolatile.ld b/c_project/bsp/vexriscv/nonvolatile.ld similarity index 100% rename from c_project/nonvolatile.ld rename to c_project/bsp/vexriscv/nonvolatile.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvicoboard.ld b/c_project/bsp/vexriscv/pqvexriscvicoboard.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvicoboard.ld rename to c_project/bsp/vexriscv/pqvexriscvicoboard.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvsim.ld b/c_project/bsp/vexriscv/pqvexriscvsim.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvsim.ld rename to c_project/bsp/vexriscv/pqvexriscvsim.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvsimhuge.ld b/c_project/bsp/vexriscv/pqvexriscvsimhuge.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvsimhuge.ld rename to c_project/bsp/vexriscv/pqvexriscvsimhuge.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k.ld b/c_project/bsp/vexriscv/pqvexriscvup5k.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k.ld rename to c_project/bsp/vexriscv/pqvexriscvup5k.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k_init.o b/c_project/bsp/vexriscv/pqvexriscvup5k_init.o similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k_init.o rename to c_project/bsp/vexriscv/pqvexriscvup5k_init.o diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k_start.o b/c_project/bsp/vexriscv/pqvexriscvup5k_start.o similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/pqvexriscvup5k_start.o rename to c_project/bsp/vexriscv/pqvexriscvup5k_start.o diff --git a/c_project/vexriscv/start.S b/c_project/bsp/vexriscv/start.S similarity index 100% rename from c_project/vexriscv/start.S rename to c_project/bsp/vexriscv/start.S diff --git a/c_project/vexriscv/volatile-split.ld b/c_project/bsp/vexriscv/volatile-split.ld similarity index 100% rename from c_project/vexriscv/volatile-split.ld rename to c_project/bsp/vexriscv/volatile-split.ld diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/volatile.ld b/c_project/bsp/vexriscv/volatile.ld similarity index 100% rename from c_project_sim_and_ulx3s/bsp/vexriscv/volatile.ld rename to c_project/bsp/vexriscv/volatile.ld diff --git a/c_project/vexriscv/weak_under_alias.h b/c_project/bsp/vexriscv/weak_under_alias.h similarity index 100% rename from c_project/vexriscv/weak_under_alias.h rename to c_project/bsp/vexriscv/weak_under_alias.h diff --git a/c_project_sim_and_ulx3s/compile_command.txt b/c_project/compile_command.txt similarity index 100% rename from c_project_sim_and_ulx3s/compile_command.txt rename to c_project/compile_command.txt diff --git a/c_project/crt.S b/c_project/crt.S deleted file mode 100644 index adfc5ab..0000000 --- a/c_project/crt.S +++ /dev/null @@ -1,97 +0,0 @@ -# .global crtStart -# .global main -# .global irqCallback - -# crtStart: -# j crtInit -# nop -# nop -# nop -# nop -# nop -# nop -# nop - -# .global trap_entry -# trap_entry: -# sw x1, - 1*4(sp) -# sw x5, - 2*4(sp) -# sw x6, - 3*4(sp) -# sw x7, - 4*4(sp) -# sw x10, - 5*4(sp) -# sw x11, - 6*4(sp) -# sw x12, - 7*4(sp) -# sw x13, - 8*4(sp) -# sw x14, - 9*4(sp) -# sw x15, -10*4(sp) -# sw x16, -11*4(sp) -# sw x17, -12*4(sp) -# sw x28, -13*4(sp) -# sw x29, -14*4(sp) -# sw x30, -15*4(sp) -# sw x31, -16*4(sp) -# addi sp,sp,-16*4 -# call irqCallback -# lw x1 , 15*4(sp) -# lw x5, 14*4(sp) -# lw x6, 13*4(sp) -# lw x7, 12*4(sp) -# lw x10, 11*4(sp) -# lw x11, 10*4(sp) -# lw x12, 9*4(sp) -# lw x13, 8*4(sp) -# lw x14, 7*4(sp) -# lw x15, 6*4(sp) -# lw x16, 5*4(sp) -# lw x17, 4*4(sp) -# lw x28, 3*4(sp) -# lw x29, 2*4(sp) -# lw x30, 1*4(sp) -# lw x31, 0*4(sp) -# addi sp,sp,16*4 -# mret -# .text - - -# crtInit: -# .option push -# .option norelax -# la gp, __global_pointer$ -# .option pop -# la sp, _stack_start - -# bss_init: -# la a0, _bss_start -# la a1, _bss_end -# bss_loop: -# beq a0,a1,bss_done -# sw zero,0(a0) -# add a0,a0,4 -# j bss_loop -# bss_done: - -# ctors_init: -# la a0, _ctors_start -# addi sp,sp,-4 -# ctors_loop: -# la a1, _ctors_end -# beq a0,a1,ctors_done -# lw a3,0(a0) -# add a0,a0,4 -# sw a0,0(sp) -# jalr a3 -# lw a0,0(sp) -# j ctors_loop -# ctors_done: -# addi sp,sp,4 - - -# li a0, 0x880 //880 enable timer + external interrupts -# csrw mie,a0 -# li a0, 0x1808 //1808 enable interrupts -# csrw mstatus,a0 - -# call main -# infinitLoop: -# j infinitLoop - diff --git a/c_project/crt.o b/c_project/crt.o deleted file mode 100644 index 7838fdd6fe1d8c0448dadf211861055626f0044e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 548 zcmb<-^>JflWMqH=MuyJ}2p$8&6R3mOxB_@W1~!? z0)zNmAOY2YgJMQ8oq>UwfeA$=Gf)H>Ff*_Kxq8Kwxh087K)R#|LTA8OC8-r940C60$VOJT6v(#&DS!f)Isjv4BnSWi diff --git a/c_project/hal-vexriscv.o b/c_project/hal-vexriscv.o deleted file mode 100644 index 389a3add9feb37644dfe1fa332088de93f943619..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 10060 zcmcgyYiwM{d7a_zl9W~?mk&u)BFihTd8t(5@*&!iY|Ex7k&+tPQuUx^$LVUhydpQ+ z2fMqJCEJM~itRj{#EIiN3EZZDgC0)mw!Q7Yul9B5SFX+_)YXxr>gn%x=%;`3lb)A9((!sG{aw|c*sNae`|a14A6AN< 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(*(SORT_NONE(.init))) - } >rom - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >rom - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >rom - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >rom - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >rom - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >rom - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >rom - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >rom - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >rom - - .lalign : - { - . = ALIGN(4); - } >rom - - .dalign : - { - . = ALIGN(4); - } >ram AT>rom - - .data : - { - PROVIDE( _data = . ); - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - } >ram AT>rom - - PROVIDE( _data_lma = LOADADDR(.data) ); - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); -} - -PROVIDE(_sp = ORIGIN(ram) + LENGTH(ram)); -PROVIDE(_heap_end = ORIGIN(ram) + LENGTH(ram)); diff --git a/c_project/vexriscv/pqvexriscvsim.ld b/c_project/vexriscv/pqvexriscvsim.ld deleted file mode 100644 index 229954b..0000000 --- a/c_project/vexriscv/pqvexriscvsim.ld +++ /dev/null @@ -1,14 +0,0 @@ -OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") -OUTPUT_ARCH(riscv) - -ENTRY( _start ) - -__ram_size = 128K; - -MEMORY -{ - rom (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K - ram (wxa!ri) : ORIGIN = 0x80020000, LENGTH = 64K -} - -INCLUDE volatile-split.ld diff --git a/c_project/vexriscv/pqvexriscvsim_init.o b/c_project/vexriscv/pqvexriscvsim_init.o deleted file mode 100644 index b1eecb83048ec31f79ede087e586f4cc20576f5d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 756 zcma)3!7>9u5PfSCc}# z<~dC7Ax+~xd*eGYk+oUU9ojfA#`;&Epm6n^7buR}>;vjKUb{5b1PvfXUm&5slz^{^|N3ZWbd0>J^v@ou)wicPZh znyRTP5zDH?73C0)AUGl+q*m&6C3-J6j-VdO6>;H!fbZF!#I=y%NpI%+zIktc>^JtO z8=F^z5Ts1d?{vzDT2sl$THMuXnx0jmaes{9qfn5EeirkXI(l8FWAsONbux?K#Ul0o zd`MAMC;Q9yF}{JZ4SM|R!@u(Jy<7Lmw)8mW@$mlXI97XdNOYX(vEJWyZHCrgjMw~Z zT-s=@&ojPzI46L&<(QJ_I!W5c9J5&$;t#tzLw0SB?1g2r>m9Ni?~vW}$aZdE zKcQwy=K=Zn%($OvzxzYw)2~2TS7;^j(i>YI`Vbo>&VxUuOr_;zJYuL z`3CY0PNb}hLR9Y*Hyk>=fmNuozvK6s04K$mtmJ zVrWDcCkCG7)R?RmKbx$*kP> zl~K#xMMG2K%+s}#OUIkZRvv+CPlZS*S(8-AWhDH;NzlKKrzMT3WSq~ESi*VlS#Bws z#HIFumy;mIO6U7qc_z^rE1j1#&m}rz zrSqMxoJn-XO1FSb7GM@!={4X=daW5Ny$x)>iU!t(EB!KXg*OgktaQFZCKo%5vC=nz zD`#0HVyyHnVDoh}ur0XKw}C6qp@A`0`VMf}LIY#0^bv4*j#VPYO8*A9%-=H@W2Ju! zT((&yVyyHBz)SFH_+{MBGX6tsj8#k>y!3o5$M>$pFA8=QUYdzvd|ylaQGoHipP7we zT;ntR0$~>X4gA;GYH&Nf_KX)(ot*K(Zs2v%2Y%A;D1<@{$cgLPL0OaI_lKUt6`R8T zj(g4bcKe|GHFvxq@CV&bg8rD7{9neUg`=N*k=Alqg_O^waWdukIG%%T5k3X~uefEz zWY=wj|EwkfP9J&v4dy-YINKqf+nPqiSA}(UewUZvoQ|Q`EP!T;xl`v@PjQd=4z|iHF;o!xGgweO%u-Z@mY9&^-KWi5eB|vkeZs0 R%PSlA6ZZF^3PP{q{sDKH=}`ax diff --git a/c_project/vexriscv/vexriscv.mk b/c_project/vexriscv/vexriscv.mk deleted file mode 100644 index 6c238df..0000000 --- a/c_project/vexriscv/vexriscv.mk +++ /dev/null @@ -1,45 +0,0 @@ -PLATFORM ?= murax - -LIBWRAP_CFLAGS += -Os -Wall -Wextra -LIBWRAP_CFLAGS += $(GCC_RISCV_ARCHFLAGS) -fstrict-volatile-bitfields --specs=nosys.specs - -ifeq ($(PLATFORM),murax) -LIBWRAP_CFLAGS += -DVEXRISCV_VOLATILE -endif - -ifeq ($(PLATFORM),pqvexriscvup5k) -LIBWRAP_CFLAGS += -DVEXRISCV_VOLATILE -DVEXRISCV_RWMTVEC -endif - -ifeq ($(PLATFORM),pqvexriscvicoboard) -LIBWRAP_CFLAGS += -DVEXRISCV_VOLATILE -DVEXRISCV_RWMTVEC -endif - -ifeq ($(PLATFORM),pqvexriscvsim) -LIBWRAP_CFLAGS += -DVEXRISCV_RWMTVEC -endif - -LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST))) - -LIBWRAP_SRCS_C = init.c -LIBWRAP_SRCS_ASM = start.s - -LIBWRAP_OBJS_ = $(LIBWRAP_SRCS_C:.c=.o) $(LIBWRAP_SRCS_ASM:.s=.o) -LIBWRAP_OBJS = $(addprefix $(LIBWRAP_DIR)$(PLATFORM)_,$(LIBWRAP_OBJS_)) - -LIBWRAP = lib$(PLATFORM)bsp.a - -$(LIBWRAP): $(LIBWRAP_OBJS) - @$(ECHO) $(LIGHTBLUE)"building "$@""$(LIGHTGRAY) - $(AR) rcs $@ $^ - -$(LIBWRAP_DIR)$(PLATFORM)_%.o: $(LIBWRAP_DIR)%.c - @$(ECHO) $(DARKBLUE)" "$(LIBWRAP_DIR)" "$(LIGHTGRAY) - @$(ECHO) $(DARKBLUE)"building "$@" (.c)"$(LIGHTGRAY) - $(GCC) $(LIBWRAP_CFLAGS) -c -o $@ $< - -$(LIBWRAP_DIR)$(PLATFORM)_%.o: $(LIBWRAP_DIR)%.S - @$(ECHO) $(DARKBLUE)"building "$@" (.S)"$(LIGHTGRAY) - $(GCC) $(LIBWRAP_CFLAGS) -c -o $@ $< - - diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/init.c b/c_project_sim_and_ulx3s/bsp/vexriscv/init.c deleted file mode 100644 index 29eb940..0000000 --- a/c_project_sim_and_ulx3s/bsp/vexriscv/init.c +++ /dev/null @@ -1,8 +0,0 @@ -#include "weak_under_alias.h" - -void __weak__init() {} - -void __weak__fini() {} - -weak_under_alias(_init); -weak_under_alias(_fini); diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/nonvolatile.ld b/c_project_sim_and_ulx3s/bsp/vexriscv/nonvolatile.ld deleted file mode 100644 index 0809fad..0000000 --- a/c_project_sim_and_ulx3s/bsp/vexriscv/nonvolatile.ld +++ /dev/null @@ -1,141 +0,0 @@ -/* SECTIONS for non-volatile chip configuration, i.e. chips with flash */ - -SECTIONS -{ - .init : - { - KEEP (*(SORT_NONE(.init))) - } >rom - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >rom - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >rom - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >rom - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >rom - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >rom - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >rom - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >rom - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >rom - - .lalign : - { - . = ALIGN(4); - } >rom - - .dalign : - { - . = ALIGN(4); - } >ram AT>rom - - .data : - { - PROVIDE( _data = . ); - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - } >ram AT>rom - - PROVIDE( _data_lma = LOADADDR(.data) ); - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); -} - -PROVIDE(_sp = ORIGIN(ram) + LENGTH(ram)); -PROVIDE(_heap_end = ORIGIN(ram) + LENGTH(ram)); diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/start.S b/c_project_sim_and_ulx3s/bsp/vexriscv/start.S deleted file mode 100644 index 105b7e8..0000000 --- a/c_project_sim_and_ulx3s/bsp/vexriscv/start.S +++ /dev/null @@ -1,156 +0,0 @@ - .section .init - .global _start - .type _start,@function -_start: -#ifndef VEXRISCV_RWMTVEC - j _crtInit - nop - nop - nop - nop - nop - nop - nop - j trap_entry -_crtInit: -#endif - .cfi_startproc - .cfi_undefined ra -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la sp, _sp - -#ifndef VEXRISCV_VOLATILE - /* Load data section */ - la a0, _data_lma - la a1, _data - la a2, _edata - bgeu a1, a2, 2f -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b -2: -#endif - - /* Clear bss section */ - la a0, __bss_start - la a1, _end - bgeu a0, a1, 2f -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b -2: - - /* Call global constructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array - - auipc ra, 0 - addi sp, sp, -16 - sw ra, 8(sp) - - /* Enable Interrupts and set trap vector */ -#ifndef VEXRISCV_RWMTVEC - la a0, trap_entry - csrw mtvec, a0 -#endif - li a0, 0x880 //880 enable timer + external interrupts - csrw mie, a0 - li a0, 0x1808 //1808 enable interrupts - csrw mstatus, a0 - - /* argc = argv = 0 */ - li a0, 0 - li a1, 0 - call main - tail exit -1: - j 1b - .cfi_endproc - - .align 4 - .weak trap_entry - .global trap_entry -trap_entry: - addi sp, sp, -32*4 - - sw x1, 1*4(sp) - sw x2, 2*4(sp) - sw x3, 3*4(sp) - sw x4, 4*4(sp) - sw x5, 5*4(sp) - sw x6, 6*4(sp) - sw x7, 7*4(sp) - sw x8, 8*4(sp) - sw x9, 9*4(sp) - sw x10, 10*4(sp) - sw x11, 11*4(sp) - sw x12, 12*4(sp) - sw x13, 13*4(sp) - sw x14, 14*4(sp) - sw x15, 15*4(sp) - sw x16, 16*4(sp) - sw x17, 17*4(sp) - sw x18, 18*4(sp) - sw x19, 19*4(sp) - sw x20, 20*4(sp) - sw x21, 21*4(sp) - sw x22, 22*4(sp) - sw x23, 23*4(sp) - sw x24, 24*4(sp) - sw x25, 25*4(sp) - sw x26, 26*4(sp) - sw x27, 27*4(sp) - sw x28, 28*4(sp) - sw x29, 29*4(sp) - sw x30, 30*4(sp) - sw x31, 31*4(sp) - - call irqCallback - - lw x1, 1*4(sp) - lw x2, 2*4(sp) - lw x3, 3*4(sp) - lw x4, 4*4(sp) - lw x5, 5*4(sp) - lw x6, 6*4(sp) - lw x7, 7*4(sp) - lw x8, 8*4(sp) - lw x9, 9*4(sp) - lw x10, 10*4(sp) - lw x11, 11*4(sp) - lw x12, 12*4(sp) - lw x13, 13*4(sp) - lw x14, 14*4(sp) - lw x15, 15*4(sp) - lw x16, 16*4(sp) - lw x17, 17*4(sp) - lw x18, 18*4(sp) - lw x19, 19*4(sp) - lw x20, 20*4(sp) - lw x21, 21*4(sp) - lw x22, 22*4(sp) - lw x23, 23*4(sp) - lw x24, 24*4(sp) - lw x25, 25*4(sp) - lw x26, 26*4(sp) - lw x27, 27*4(sp) - lw x28, 28*4(sp) - lw x29, 29*4(sp) - lw x30, 30*4(sp) - lw x31, 31*4(sp) - - addi sp, sp, 32*4 - mret - - .weak irqCallback -irqCallback: -1: - j 1b diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/volatile-split.ld b/c_project_sim_and_ulx3s/bsp/vexriscv/volatile-split.ld deleted file mode 100644 index 00d8d89..0000000 --- a/c_project_sim_and_ulx3s/bsp/vexriscv/volatile-split.ld +++ /dev/null @@ -1,137 +0,0 @@ -/* SECTIONS for volatile chip configuration, i.e. chips without flash */ - -SECTIONS -{ - .init : - { - KEEP (*(SORT_NONE(.init))) - } >rom - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >rom - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >rom - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >rom - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >rom - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >rom - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >rom - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >rom - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >rom - - /* RODATA is usally in ROM, however in volatile configurations this doesn't - make a lot of sense. */ - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >ram - - .data : - { - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); -} - -PROVIDE(_sp = ORIGIN(ram) + LENGTH(ram)); -PROVIDE(_heap_end = ORIGIN(ram) + LENGTH(ram)); diff --git a/c_project_sim_and_ulx3s/bsp/vexriscv/weak_under_alias.h b/c_project_sim_and_ulx3s/bsp/vexriscv/weak_under_alias.h deleted file mode 100644 index 4de2501..0000000 --- a/c_project_sim_and_ulx3s/bsp/vexriscv/weak_under_alias.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef WEAK_UNDER_ALIAS_H -#define WEAK_UNDER_ALIAS_H - -#define weak_under_alias(name) \ - extern __typeof (__weak_##name) name __attribute__ ((weak, alias ("__weak_"#name))) - -#endif /* WEAK_UNDER_ALIAS_H */ diff --git a/c_project_sim_and_ulx3s/hal-vexriscv.c b/c_project_sim_and_ulx3s/hal-vexriscv.c deleted file mode 100644 index 29fa8e5..0000000 --- a/c_project_sim_and_ulx3s/hal-vexriscv.c +++ /dev/null @@ -1,60 +0,0 @@ -#include "hal.h" -#include - -/* Murax UART */ - -typedef struct { - volatile uint32_t DATA; - volatile uint32_t STATUS; - volatile uint32_t CLOCK_DIVIDER; - volatile uint32_t FRAME_CONFIG; -} Uart_Reg; - -enum UartParity { NONE = 0, EVEN = 1, ODD = 2 }; -enum UartStop { ONE = 0, TWO = 1 }; - -typedef struct { - uint32_t dataLength; - enum UartParity parity; - enum UartStop stop; - uint32_t clockDivider; -} Uart_Config; - -static uint32_t uart_writeAvailability(Uart_Reg* reg) -{ - return (reg->STATUS >> 16) & 0xFF; -} - -static void uart_write(Uart_Reg* reg, uint32_t data) -{ - while (uart_writeAvailability(reg) == 0) - ; - reg->DATA = data; -} - -#define UART ((Uart_Reg*)(0xF0010000)) - -void hal_send(const uint8_t* in, const size_t len) { - for (size_t i = 0; i < len; i++) { - uart_write(UART, in[i]); - } -} - -void hal_send_str(const char* in) -{ - const char* cur = in; - while(*cur) { - uart_write(UART, *cur); - cur += 1; - } -} - -__attribute__((naked)) uint64_t hal_get_time(void) -{ -#define LE "\n\t" - asm volatile (LE"csrr a1, mcycleh" - LE"csrr a0, mcycle" - LE"csrr a2, mcycleh" - LE"bne a1, a2, hal_get_time" - LE"ret"); -} diff --git a/c_project_sim_and_ulx3s/hal.c b/c_project_sim_and_ulx3s/hal.c deleted file mode 100644 index 2c43d0e..0000000 --- a/c_project_sim_and_ulx3s/hal.c +++ /dev/null @@ -1,21 +0,0 @@ -#include - -#include -#include - -#include -#undef errno -extern int errno; - -#include "hal.h" - -void _putchar(char c) { - hal_send((uint8_t*)&c, 1); -} - -void _write(int fd, const void* ptr, size_t len) { - // Don't care about the fd. Just put everything on the UART console. - (void)fd; - hal_send(ptr, len); -} - diff --git a/c_project_sim_and_ulx3s/hal.h b/c_project_sim_and_ulx3s/hal.h deleted file mode 100644 index 217bb5b..0000000 --- a/c_project_sim_and_ulx3s/hal.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef VECRISCV_HAL_H_ -#define VECRISCV_HAL_H_ - -#include -#include -#include - -#define printf printf_ - -void hal_send(const uint8_t* in, const size_t len); -void hal_send_str(const char* in); - -int printf_(const char* format, ...); - -void _putchar(char c); -void _write(int fd, const void* ptr, size_t len); - -#endif /* VECRISCV_HAL_H_ */ diff --git a/c_project_sim_and_ulx3s/main.c b/c_project_sim_and_ulx3s/main.c deleted file mode 100644 index 7783f33..0000000 --- a/c_project_sim_and_ulx3s/main.c +++ /dev/null @@ -1,29 +0,0 @@ -#include -#include "hal.h" - -// typedef struct { -// volatile uint32_t state; -// } My_Mem; - -// #define MY_MEM ((My_Mem*)(0xF0030000)) - -int main(void) -{ - printf("HELLO WORLD\n"); - - uint32_t state = 10000; - // uint32_t state_return; - - while (1) - { - printf("State in : %i\n", state); - - // MY_MEM->state = state; - // state_return = MY_MEM->state; - - state = state + 1; - - printf("State out: %i\n", state); - } - return 0; -} diff --git a/c_project_sim_and_ulx3s/memcmp.c b/c_project_sim_and_ulx3s/memcmp.c deleted file mode 100644 index 2348afe..0000000 --- a/c_project_sim_and_ulx3s/memcmp.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Public domain. */ -#include - -int -memcmp (const void *str1, const void *str2, size_t count) -{ - const unsigned char *s1 = str1; - const unsigned char *s2 = str2; - - while (count-- > 0) - { - if (*s1++ != *s2++) - return s1[-1] < s2[-1] ? -1 : 1; - } - return 0; -} diff --git a/c_project_sim_and_ulx3s/memcpy.c b/c_project_sim_and_ulx3s/memcpy.c deleted file mode 100644 index 39786ba..0000000 --- a/c_project_sim_and_ulx3s/memcpy.c +++ /dev/null @@ -1,61 +0,0 @@ -/* Public domain. */ -#include - -/* -** Copyright 2001, Travis Geiselbrecht. All rights reserved. -** Distributed under the terms of the NewOS License. -*/ -/* - * Copyright (c) 2008 Travis Geiselbrecht - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files - * (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -typedef long word; -#define lsize sizeof(word) -#define lmask (lsize - 1) -void *memcpy(void *dest, const void *src, size_t count) -{ - char *d = (char *)dest; - const char *s = (const char *)src; - int len; - if(count == 0 || dest == src) - return dest; - if(((long)d | (long)s) & lmask) { - // src and/or dest do not align on word boundary - if((((long)d ^ (long)s) & lmask) || (count < lsize)) - len = count; // copy the rest of the buffer with the byte mover - else - len = lsize - ((long)d & lmask); // move the ptrs up to a word boundary - count -= len; - for(; len > 0; len--) - *d++ = *s++; - } - for(len = count / lsize; len > 0; len--) { - *(word *)d = *(word *)s; - d += lsize; - s += lsize; - } - for(len = count & lmask; len > 0; len--) - *d++ = *s++; - return dest; -} diff --git a/c_project_sim_and_ulx3s/memset.c b/c_project_sim_and_ulx3s/memset.c deleted file mode 100644 index 86efb6d..0000000 --- a/c_project_sim_and_ulx3s/memset.c +++ /dev/null @@ -1,64 +0,0 @@ -/* -** Copyright 2005, Michael Noisternig. All rights reserved. -** Copyright 2001, Travis Geiselbrecht. All rights reserved. -** Distributed under the terms of the NewOS License. -*/ -/* - * Copyright (c) 2008 Travis Geiselbrecht - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files - * (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -// void * -// memset(void *s, int c, size_t count) -// { -// char *xs = (char *) s; -// // size_t len = (-(size_t)s) & (sizeof(size_t)-1); -// // int cc = c & 0xff; -// // if ( count > len ) { -// // count -= len; -// // cc |= cc << 8; -// // cc |= cc << 16; -// // // write to non-aligned memory byte-wise -// // for ( ; len > 0; len-- ) -// // *xs++ = c; -// // // write to aligned memory dword-wise -// // for ( len = count/sizeof(size_t); len > 0; len-- ) { -// // *((size_t *)xs) = cc; -// // xs += sizeof(size_t); -// // } -// // count &= sizeof(size_t)-1; -// // } -// // write remaining bytes -// for ( ; count > 0; count-- ) -// *xs++ = (char) c; -// return s; -// } - -void * -memset (void *dest, int val, size_t len) -{ - unsigned char *ptr = dest; - while (len-- > 0) - *ptr++ = (unsigned char) val; - return dest; -} \ No newline at end of file diff --git a/c_project_sim_and_ulx3s/printf.c b/c_project_sim_and_ulx3s/printf.c deleted file mode 100644 index 7bf7d74..0000000 --- a/c_project_sim_and_ulx3s/printf.c +++ /dev/null @@ -1,987 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. These routines are thread -// safe and reentrant! -// Use this instead of the bloated standard/newlib printf cause these use -// malloc for printf (and may not be thread safe). -// -/////////////////////////////////////////////////////////////////////////////// - -#include -#include - -#include "printf.h" - - -// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the -// printf_config.h header file -// default: undefined -#ifdef PRINTF_INCLUDE_CONFIG_H -#include "printf_config.h" -#endif - - -// 'ntoa' conversion buffer size, this must be big enough to hold one converted -// numeric number including padded zeros (dynamically created on stack) -// default: 32 byte -#ifndef PRINTF_NTOA_BUFFER_SIZE -#define PRINTF_NTOA_BUFFER_SIZE 32U -#endif - -// 'ftoa' conversion buffer size, this must be big enough to hold one converted -// float number including padded zeros (dynamically created on stack) -// default: 32 byte -#ifndef PRINTF_FTOA_BUFFER_SIZE -#define PRINTF_FTOA_BUFFER_SIZE 32U -#endif - -// support for the floating point type (%f) -// default: activated -// #ifndef PRINTF_DISABLE_SUPPORT_FLOAT -// #define PRINTF_SUPPORT_FLOAT -// #endif - -// support for exponential floating point notation (%e/%g) -// default: activated -// #ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL -// #define PRINTF_SUPPORT_EXPONENTIAL -// #endif - -// define the default floating point precision -// default: 6 digits -// #ifndef PRINTF_DEFAULT_FLOAT_PRECISION -// #define PRINTF_DEFAULT_FLOAT_PRECISION 6U -// #endif - -// define the largest float suitable to print with %f -// default: 1e9 -// #ifndef PRINTF_MAX_FLOAT -// #define PRINTF_MAX_FLOAT 1e9 -// #endif - -// support for the long long types (%llu or %p) -// default: activated -#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG -#define PRINTF_SUPPORT_LONG_LONG -#endif - -// support for the ptrdiff_t type (%t) -// ptrdiff_t is normally defined in as long or long long type -// default: activated -// #ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T -// #define PRINTF_SUPPORT_PTRDIFF_T -// #endif - -/////////////////////////////////////////////////////////////////////////////// - -// internal flag definitions -#define FLAGS_ZEROPAD (1U << 0U) -#define FLAGS_LEFT (1U << 1U) -#define FLAGS_PLUS (1U << 2U) -#define FLAGS_SPACE (1U << 3U) -#define FLAGS_HASH (1U << 4U) -#define FLAGS_UPPERCASE (1U << 5U) -#define FLAGS_CHAR (1U << 6U) -#define FLAGS_SHORT (1U << 7U) -#define FLAGS_LONG (1U << 8U) -#define FLAGS_LONG_LONG (1U << 9U) -#define FLAGS_PRECISION (1U << 10U) -#define FLAGS_ADAPT_EXP (1U << 11U) - - -// import float.h for DBL_MAX -// #if defined(PRINTF_SUPPORT_FLOAT) -// #include -// #endif - - -// output function type -typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen); - - -// wrapper (used as buffer) for output function type -typedef struct { - void (*fct)(char character, void* arg); - void* arg; -} out_fct_wrap_type; - - -// Sometimes div modulo is not available, we implement one with shift/and/or -static int divmod(int* Qptr, int* Rptr, const int N, const int D) { - if (D == 0) { - return -1; - } - - int Q = 0; - int R = 0; - for (int i = 8*sizeof(int) - 1; i >= 0; i--) { - R <<= 1; - R |= (N >> i) & 0x1; - if (R >= D) { - R -= D; - Q |= 1 << i; - } - } - *Qptr = Q; - *Rptr = R; - return 0; -} - -// Sometimes div modulo is not available, we implement one with shift/and/or -static int divmod_long_long(long long* Qptr, long long* Rptr, const long long N, const int D) { - if (D == 0) { - return -1; - } - - long long Q = 0; - long long R = 0; - for (long long i = 8*sizeof(long long) - 1; i >= 0; i--) { - R <<= 1; - R |= (N >> i) & 0x1; - if (R >= D) { - R -= D; - Q |= 1 << i; - } - } - *Qptr = Q; - *Rptr = R; - return 0; -} - - -// internal buffer output -static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen) -{ - if (idx < maxlen) { - ((char*)buffer)[idx] = character; - } -} - - -// internal null output -static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)character; (void)buffer; (void)idx; (void)maxlen; -} - - -// internal _putchar wrapper -static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)buffer; (void)idx; (void)maxlen; - if (character) { - _putchar(character); - } -} - - -// internal output function wrapper -static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)idx; (void)maxlen; - if (character) { - // buffer is the output fct pointer - ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg); - } -} - - -// internal secure strlen -// \return The length of the string (excluding the terminating 0) limited by 'maxsize' -static inline unsigned int _strnlen_s(const char* str, size_t maxsize) -{ - const char* s; - for (s = str; *s && maxsize--; ++s); - return (unsigned int)(s - str); -} - - -// internal test if char is a digit (0-9) -// \return true if char is a digit -static inline bool _is_digit(char ch) -{ - return (ch >= '0') && (ch <= '9'); -} - - -// internal ASCII string to unsigned int conversion -static unsigned int _atoi(const char** str) -{ - unsigned int i = 0U; - while (_is_digit(**str)) { - i = i * 10U + (unsigned int)(*((*str)++) - '0'); - } - return i; -} - - -// output the specified string in reverse, taking care of any zero-padding -static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags) -{ - const size_t start_idx = idx; - - // pad spaces up to given width - if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { - for (size_t i = len; i < width; i++) { - out(' ', buffer, idx++, maxlen); - } - } - - // reverse string - while (len) { - out(buf[--len], buffer, idx++, maxlen); - } - - // append pad spaces up to given width - if (flags & FLAGS_LEFT) { - while (idx - start_idx < width) { - out(' ', buffer, idx++, maxlen); - } - } - - return idx; -} - - -// internal itoa format -static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) -{ - // pad leading zeros - if (!(flags & FLAGS_LEFT)) { - if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { - width--; - } - while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - } - - // handle hash - if (flags & FLAGS_HASH) { - if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { - len--; - if (len && (base == 16U)) { - len--; - } - } - if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'x'; - } - else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'X'; - } - else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'b'; - } - if (len < PRINTF_NTOA_BUFFER_SIZE) { - buf[len++] = '0'; - } - } - - if (len < PRINTF_NTOA_BUFFER_SIZE) { - if (negative) { - buf[len++] = '-'; - } - else if (flags & FLAGS_PLUS) { - buf[len++] = '+'; // ignore the space if the '+' exists - } - else if (flags & FLAGS_SPACE) { - buf[len++] = ' '; - } - } - - return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -} - - -// internal itoa for 'long' type -static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) -{ - char buf[PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - int q, r; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - q = 0, r = 0; - len = 0; - do { - divmod(&q, &r, value, base); - const char digit = (char)(r); - // buf[idx2++] = '0' + digit; - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - value = q; - } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - // while (idx2 > 0) { - // _putchar(buf[--idx2]); - // written++; - // } - // idx++; - - - - // do { - // const char digit = (char)(value % base); - // buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - // value /= base; - // } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); -} - - -// // internal itoa for 'long long' type -#if defined(PRINTF_SUPPORT_LONG_LONG) -static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) -{ - char buf[PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - long long q, r; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - q = 0, r = 0; - len = 0; - do { - divmod_long_long(&q, &r, value, base); - const char digit = (char)(r); - // buf[idx2++] = '0' + digit; - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - value = q; - } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - - - // do { - // const char digit = (char)(value % base); - // buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - // value /= base; - // } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); -} -#endif // PRINTF_SUPPORT_LONG_LONG - - -// #if defined(PRINTF_SUPPORT_FLOAT) -// -// #if defined(PRINTF_SUPPORT_EXPONENTIAL) -// // forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT -// static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags); -// #endif -// -// -// // internal ftoa for fixed decimal floating point -// static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) -// { -// char buf[PRINTF_FTOA_BUFFER_SIZE]; -// size_t len = 0U; -// double diff = 0.0; -// -// // powers of 10 -// static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 }; -// -// // test for special values -// if (value != value) -// return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); -// if (value < -DBL_MAX) -// return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); -// if (value > DBL_MAX) -// return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags); -// -// // test for very large values -// // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad -// if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) { -// #if defined(PRINTF_SUPPORT_EXPONENTIAL) -// return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); -// #else -// return 0U; -// #endif -// } -// -// // test for negative -// bool negative = false; -// if (value < 0) { -// negative = true; -// value = 0 - value; -// } -// -// // set default precision, if not set explicitly -// if (!(flags & FLAGS_PRECISION)) { -// prec = PRINTF_DEFAULT_FLOAT_PRECISION; -// } -// // limit precision to 9, cause a prec >= 10 can lead to overflow errors -// while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { -// buf[len++] = '0'; -// prec--; -// } -// -// int whole = (int)value; -// double tmp = (value - whole) * pow10[prec]; -// unsigned long frac = (unsigned long)tmp; -// diff = tmp - frac; -// -// if (diff > 0.5) { -// ++frac; -// // handle rollover, e.g. case 0.99 with prec 1 is 1.0 -// if (frac >= pow10[prec]) { -// frac = 0; -// ++whole; -// } -// } -// else if (diff < 0.5) { -// } -// else if ((frac == 0U) || (frac & 1U)) { -// // if halfway, round up if odd OR if last digit is 0 -// ++frac; -// } -// -// if (prec == 0U) { -// diff = value - (double)whole; -// if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { -// // exactly 0.5 and ODD, then round up -// // 1.5 -> 2, but 2.5 -> 2 -// ++whole; -// } -// } -// else { -// unsigned int count = prec; -// // now do fractional part, as an unsigned number -// while (len < PRINTF_FTOA_BUFFER_SIZE) { -// --count; -// buf[len++] = (char)(48U + (frac % 10U)); -// if (!(frac /= 10U)) { -// break; -// } -// } -// // add extra 0s -// while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { -// buf[len++] = '0'; -// } -// if (len < PRINTF_FTOA_BUFFER_SIZE) { -// // add decimal -// buf[len++] = '.'; -// } -// } -// -// // do whole part, number is reversed -// while (len < PRINTF_FTOA_BUFFER_SIZE) { -// buf[len++] = (char)(48 + (whole % 10)); -// if (!(whole /= 10)) { -// break; -// } -// } -// -// // pad leading zeros -// if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { -// if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { -// width--; -// } -// while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) { -// buf[len++] = '0'; -// } -// } -// -// if (len < PRINTF_FTOA_BUFFER_SIZE) { -// if (negative) { -// buf[len++] = '-'; -// } -// else if (flags & FLAGS_PLUS) { -// buf[len++] = '+'; // ignore the space if the '+' exists -// } -// else if (flags & FLAGS_SPACE) { -// buf[len++] = ' '; -// } -// } -// -// return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -// } -// -// -// #if defined(PRINTF_SUPPORT_EXPONENTIAL) -// // internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse -// static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) -// { -// // check for NaN and special values -// if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) { -// return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); -// } -// -// // determine the sign -// const bool negative = value < 0; -// if (negative) { -// value = -value; -// } -// -// // default precision -// if (!(flags & FLAGS_PRECISION)) { -// prec = PRINTF_DEFAULT_FLOAT_PRECISION; -// } -// -// // determine the decimal exponent -// // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) -// union { -// uint64_t U; -// double F; -// } conv; -// -// conv.F = value; -// int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 -// conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) -// // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 -// int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); -// // now we want to compute 10^expval but we want to be sure it won't overflow -// exp2 = (int)(expval * 3.321928094887362 + 0.5); -// const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; -// const double z2 = z * z; -// conv.U = (uint64_t)(exp2 + 1023) << 52U; -// // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex -// conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); -// // correct for rounding errors -// if (value < conv.F) { -// expval--; -// conv.F /= 10; -// } -// -// // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters -// unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; -// -// // in "%g" mode, "prec" is the number of *significant figures* not decimals -// if (flags & FLAGS_ADAPT_EXP) { -// // do we want to fall-back to "%f" mode? -// if ((value >= 1e-4) && (value < 1e6)) { -// if ((int)prec > expval) { -// prec = (unsigned)((int)prec - expval - 1); -// } -// else { -// prec = 0; -// } -// flags |= FLAGS_PRECISION; // make sure _ftoa respects precision -// // no characters in exponent -// minwidth = 0U; -// expval = 0; -// } -// else { -// // we use one sigfig for the whole part -// if ((prec > 0) && (flags & FLAGS_PRECISION)) { -// --prec; -// } -// } -// } -// -// // will everything fit? -// unsigned int fwidth = width; -// if (width > minwidth) { -// // we didn't fall-back so subtract the characters required for the exponent -// fwidth -= minwidth; -// } else { -// // not enough characters, so go back to default sizing -// fwidth = 0U; -// } -// if ((flags & FLAGS_LEFT) && minwidth) { -// // if we're padding on the right, DON'T pad the floating part -// fwidth = 0U; -// } -// -// // rescale the float value -// if (expval) { -// value /= conv.F; -// } -// -// // output the floating part -// const size_t start_idx = idx; -// idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); -// -// // output the exponent part -// if (minwidth) { -// // output the exponential symbol -// out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); -// // output the exponent value -// idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS); -// // might need to right-pad spaces -// if (flags & FLAGS_LEFT) { -// while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); -// } -// } -// return idx; -// } -// #endif // PRINTF_SUPPORT_EXPONENTIAL -// #endif // PRINTF_SUPPORT_FLOAT - - -// internal vsnprintf -static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va) -{ - unsigned int flags, width, precision, n; - size_t idx = 0U; - - if (!buffer) { - // use null output function - out = _out_null; - } - - while (*format) - { - // format specifier? %[flags][width][.precision][length] - if (*format != '%') { - // no - out(*format, buffer, idx++, maxlen); - format++; - continue; - } - else { - // yes, evaluate it - format++; - } - - // evaluate flags - flags = 0U; - do { - switch (*format) { - case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; - case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; - case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; - case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; - case '#': flags |= FLAGS_HASH; format++; n = 1U; break; - default : n = 0U; break; - } - } while (n); - - // evaluate width field - width = 0U; - if (_is_digit(*format)) { - width = _atoi(&format); - } - else if (*format == '*') { - const int w = va_arg(va, int); - if (w < 0) { - flags |= FLAGS_LEFT; // reverse padding - width = (unsigned int)-w; - } - else { - width = (unsigned int)w; - } - format++; - } - - // evaluate precision field - precision = 0U; - if (*format == '.') { - flags |= FLAGS_PRECISION; - format++; - if (_is_digit(*format)) { - precision = _atoi(&format); - } - else if (*format == '*') { - const int prec = (int)va_arg(va, int); - precision = prec > 0 ? (unsigned int)prec : 0U; - format++; - } - } - - // evaluate length field - switch (*format) { - case 'l' : - flags |= FLAGS_LONG; - format++; - if (*format == 'l') { - flags |= FLAGS_LONG_LONG; - format++; - } - break; - case 'h' : - flags |= FLAGS_SHORT; - format++; - if (*format == 'h') { - flags |= FLAGS_CHAR; - format++; - } - break; -// #if defined(PRINTF_SUPPORT_PTRDIFF_T) -// case 't' : -// flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); -// format++; -// break; -// #endif - case 'j' : - flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - case 'z' : - flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - default : - break; - } - - // evaluate specifier - switch (*format) { - case 'd' : - case 'i' : - case 'u' : - case 'x' : - case 'X' : - case 'o' : - case 'b' : { - // set the base - unsigned int base; - if (*format == 'x' || *format == 'X') { - base = 16U; - } - else if (*format == 'o') { - base = 8U; - } - else if (*format == 'b') { - base = 2U; - } - else { - base = 10U; - flags &= ~FLAGS_HASH; // no hash for dec format - } - // uppercase - if (*format == 'X') { - flags |= FLAGS_UPPERCASE; - } - - // no plus or space flag for u, x, X, o, b - if ((*format != 'i') && (*format != 'd')) { - flags &= ~(FLAGS_PLUS | FLAGS_SPACE); - } - - // ignore '0' flag when precision is given - if (flags & FLAGS_PRECISION) { - flags &= ~FLAGS_ZEROPAD; - } - - // convert the integer - if ((*format == 'i') || (*format == 'd')) { - // signed - if (flags & FLAGS_LONG_LONG) { -#if defined(PRINTF_SUPPORT_LONG_LONG) - const long long value = va_arg(va, long long); - idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); -#endif - } - else if (flags & FLAGS_LONG) { - const long value = va_arg(va, long); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); - } - else { - const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); - } - } - else { - // unsigned - if (flags & FLAGS_LONG_LONG) { -#if defined(PRINTF_SUPPORT_LONG_LONG) - idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); -#endif - } - else if (flags & FLAGS_LONG) { - idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); - } - else { - const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); - idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); - } - } - format++; - break; - } -// #if defined(PRINTF_SUPPORT_FLOAT) -// case 'f' : -// case 'F' : -// if (*format == 'F') flags |= FLAGS_UPPERCASE; -// idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); -// format++; -// break; -// #if defined(PRINTF_SUPPORT_EXPONENTIAL) -// case 'e': -// case 'E': -// case 'g': -// case 'G': -// if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP; -// if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; -// idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); -// format++; -// break; -// #endif // PRINTF_SUPPORT_EXPONENTIAL -// #endif // PRINTF_SUPPORT_FLOAT - case 'c' : { - unsigned int l = 1U; - // pre padding - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // char output - out((char)va_arg(va, int), buffer, idx++, maxlen); - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 's' : { - const char* p = va_arg(va, char*); - unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1); - // pre padding - if (flags & FLAGS_PRECISION) { - l = (l < precision ? l : precision); - } - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // string output - while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { - out(*(p++), buffer, idx++, maxlen); - } - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 'p' : { - width = sizeof(void*) * 2U; - flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; -#if defined(PRINTF_SUPPORT_LONG_LONG) - const bool is_ll = sizeof(uintptr_t) == sizeof(long long); - if (is_ll) { - idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags); - } - else { -#endif - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags); -#if defined(PRINTF_SUPPORT_LONG_LONG) - } -#endif - format++; - break; - } - - case '%' : - out('%', buffer, idx++, maxlen); - format++; - break; - - default : - out(*format, buffer, idx++, maxlen); - format++; - break; - } - } - - // termination - out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); - - // return written chars without terminating \0 - return (int)idx; -} - - -/////////////////////////////////////////////////////////////////////////////// - -int printf_(const char* format, ...) -{ - va_list va; - va_start(va, format); - char buffer[1]; - const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); - va_end(va); - return ret; -} - - -int sprintf_(char* buffer, const char* format, ...) -{ - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va); - va_end(va); - return ret; -} - - -int snprintf_(char* buffer, size_t count, const char* format, ...) -{ - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); - va_end(va); - return ret; -} - - -int vprintf_(const char* format, va_list va) -{ - char buffer[1]; - return _vsnprintf(_out_char, buffer, (size_t)-1, format, va); -} - - -int vsnprintf_(char* buffer, size_t count, const char* format, va_list va) -{ - return _vsnprintf(_out_buffer, buffer, count, format, va); -} - - -int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...) -{ - va_list va; - va_start(va, format); - const out_fct_wrap_type out_fct_wrap = { out, arg }; - const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); - va_end(va); - return ret; -} diff --git a/c_project_sim_and_ulx3s/printf.h b/c_project_sim_and_ulx3s/printf.h deleted file mode 100644 index 165f348..0000000 --- a/c_project_sim_and_ulx3s/printf.h +++ /dev/null @@ -1,121 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. -// Use this instead of bloated standard/newlib printf. -// These routines are thread safe and reentrant. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _PRINTF_H_ -#define _PRINTF_H_ - -#include -#include - - -#ifdef __cplusplus -extern "C" { -#endif - -#define PRINTF_DISABLE_SUPPORT_FLOAT -#define PRINTF_DISABLE_SUPPORT_EXPONENTIAL -// #define PRINTF_DISABLE_SUPPORT_LONG_LONG -#define PRINTF_DISABLE_SUPPORT_PTRDIFF_T - -/** - * Output a character to a custom device like UART, used by the printf() function - * This function is declared here only. You have to write your custom implementation somewhere - * \param character Character to output - */ -void _putchar(char character); - - -/** - * Tiny printf implementation - * You have to implement _putchar if you use printf() - * To avoid conflicts with the regular printf() API it is overridden by macro defines - * and internal underscore-appended functions like printf_() are used - * \param format A string that specifies the format of the output - * \return The number of characters that are written into the array, not counting the terminating null character - */ -#define printf printf_ -int printf_(const char* format, ...); - - -/** - * Tiny sprintf implementation - * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD! - * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output! - * \param format A string that specifies the format of the output - * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character - */ -#define sprintf sprintf_ -int sprintf_(char* buffer, const char* format, ...); - - -/** - * Tiny snprintf/vsnprintf implementation - * \param buffer A pointer to the buffer where to store the formatted string - * \param count The maximum number of characters to store in the buffer, including a terminating null character - * \param format A string that specifies the format of the output - * \param va A value identifying a variable arguments list - * \return The number of characters that COULD have been written into the buffer, not counting the terminating - * null character. A value equal or larger than count indicates truncation. Only when the returned value - * is non-negative and less than count, the string has been completely written. - */ -#define snprintf snprintf_ -#define vsnprintf vsnprintf_ -int snprintf_(char* buffer, size_t count, const char* format, ...); -int vsnprintf_(char* buffer, size_t count, const char* format, va_list va); - - -/** - * Tiny vprintf implementation - * \param format A string that specifies the format of the output - * \param va A value identifying a variable arguments list - * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character - */ -#define vprintf vprintf_ -int vprintf_(const char* format, va_list va); - - -/** - * printf with output function - * You may use this as dynamic alternative to printf() with its fixed _putchar() output - * \param out An output function which takes one character and an argument pointer - * \param arg An argument pointer for user data passed to output function - * \param format A string that specifies the format of the output - * \return The number of characters that are sent to the output function, not counting the terminating null character - */ -int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...); - - -#ifdef __cplusplus -} -#endif - - -#endif // _PRINTF_H_ diff --git a/c_project_sim_and_ulx3s/volatile-split.ld b/c_project_sim_and_ulx3s/volatile-split.ld deleted file mode 100644 index 00d8d89..0000000 --- a/c_project_sim_and_ulx3s/volatile-split.ld +++ /dev/null @@ -1,137 +0,0 @@ -/* SECTIONS for volatile chip configuration, i.e. chips without flash */ - -SECTIONS -{ - .init : - { - KEEP (*(SORT_NONE(.init))) - } >rom - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >rom - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >rom - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >rom - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >rom - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >rom - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >rom - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >rom - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >rom - - /* RODATA is usally in ROM, however in volatile configurations this doesn't - make a lot of sense. */ - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >ram - - .data : - { - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); -} - -PROVIDE(_sp = ORIGIN(ram) + LENGTH(ram)); -PROVIDE(_heap_end = ORIGIN(ram) + LENGTH(ram)); diff --git a/ulx3s/Makefile b/ulx3s/Makefile new file mode 100644 index 0000000..cf812db --- /dev/null +++ b/ulx3s/Makefile @@ -0,0 +1,32 @@ +TOPMOD := PQVexRiscvUlx3s +CHIP := 85k +PACKAGE := CABGA381 +CONSTRAINTS := ulx3s_v20_constraints +VLOGFIL := $(TOPMOD).v +PROGPATH := ~/bin/ujprog/ujprog + +.PHONY: all + +all: $(TOPMOD).bit + +.PHONY: clean +clean: + rm -rf $(TOPMOD).json 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zvmfM5C_6x>=M>bA=;25xX(xK=?M-(?E9jxqa{PyH?D$!>_{~~NuFI_4v8E$}nr~KD z)(&ycU`GU*q*Eq4LG$J9jC7nWtjs#uQCjBD+_4fu?)uSEv|EnuvGQHj`-d7CbW}v+ zu*U5CxCfy)?c!}#!DP=J>mjK57h$=hv_7W#OwT+etFd}GUOHCeclsaGpHN3jPU8p6 zd|~BLPV{zlKTCCX5%#$V^! zVJFC%y@kM6%D+*QwP>*`N09rm@W*u|hJ@N-Bq0)NN1)wymZ2k-kZVnB_w#aWPulGB z?w|7Fx;&y{oMp+v660dd*qJiaoK0gnX)G?f zbnm|`MrhGpe?5__ciQ9B^9gVL-eQE7Dnr>hBgH7kX%9gQj)Zi}hHL+8F+s~FS$v}( zkA=tj^4x&8XyL}+M9f`BWrS+l>`N^PIz{ND6Ch}=bwst$mq3v%Bg-sA*r(l5u}dSI zd|yVW5tnnRFXw)`-LC0^pcrYa0aOe2&C8OTZQBzJ3mf_J990g{2$#-v@QxdiK1)45 zi55w7Os|+M!T-2ym4$Z2BHbslm#TKqb zHY2r@011!)36KB@coR7A1?LTIq&MWvkO@hE1W14cNPq;2OyGTg=e(g2dP7AvBejzN z36KB@kN^pI6ZmGA^M*Fl8}eqzgd{)$BtQZrKmtW3@S}^IHx$zwDzX`=odigL1W14c zNWh!GF@NE_p>cXc-VB+L1W14cNPq-LpvVMXGUU9W33@|CHY2r@011!)36KB@coVqj zlg=C3NpHxTArq1S36KB@kN^o3nZO&q?7X2Gy`dtTk=jXs1W14cNPq;q2|W8#=MC+m zH{{Kb2}ytiNPq-LfCP$6pnk3MhIZ2%DzX`=odigL1W14cNWh!GdtU6kq08wFc{5}} z5+DH*AOR8}fg%&QdyDgi5_&^LHY2r@011!)36KB@coXCPLvm)?*!Lnb5v5+DH*AOR96GJ(;TId7;=Z>Y#- zq;?V@0TLhq5+DI@0)Kys^M)RwH{{Kb2}ytiNPq-LfCP$6;Jp*h8+wf1P?60@?Ib_~ zBtQZrKmy(b9{8p6hQ3N~$eSS(k^l*i011!)2^5*YFZMZa=n%c3BAb!gNq_`MfCNZ@ z1iT5HbDQ&qeoSx3n;{dD011!)36KB@6q&%A>&_ec8NHz*n~~Z{fCNZ@1W14cya{Z) z#Cbzc(;M<;$b=+70wh2JBtQa1CNNO8-cVrZ4Hemp)J_55P=(%5kjW~6o!AOR8}0TLhqZvx+b(s@JU^oG0{G9d|&011!)36MaM3H;!%oHsN< zZ>Y#-q;?V@0TLhq5+DI@0w4J;=MC+oH{{Kb2}ytiNPq-LfCP$6;QFo38>-P8DzX`= zodigL1W14cNWh!G%dc|Y&@OsI-VB+L1W14cNPq-LpvVOJp6|S&-SmcvY({D)0TLhq z5+DH*@FuY39_I~RPH)JYArq1S36KB@kN^o3nZV`$?7X3b-cXUvNbMv*0wh2JBtQb* z1U4nk8=9gw7eny`dtTk=jXs1W14cNPq;q2|QSF-q3z}L*5LT zkOWA81W14cNTA3Bp1IU{LwC{}DzX`=odigL1W14cNWh!GJzsU+(7p7Aycsef36KB@ zkN^pgK#>W&`_s-Fs?!@PvKgtJ1W14cNPq-Lz?;Aow>xj>5qd-344IGwNPq-LfCNaO z$ON`N;Jl&7=nWOwjMPp7BtQZrKmsJ-P2i}vI&bK!^oG0{G9d|&011!)36MaM3B01$ zc|(Wj4Hemp)J_5>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_174_ = _zz_173_[31 : 0]; + assign _zz_175_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_176_ = _zz_75_[22 : 22]; + assign _zz_177_ = _zz_75_[15 : 15]; + assign _zz_178_ = ({memory_Mul16Plugin_hh,memory_Mul16Plugin_ll[31 : 16]} + _zz_179_); + assign _zz_179_ = {15'd0, memory_Mul16Plugin_hllh}; + assign _zz_180_ = _zz_75_[14 : 14]; + assign _zz_181_ = _zz_75_[11 : 11]; + assign _zz_182_ = (decode_PC >>> 1); + assign _zz_183_ = (decode_PC >>> 1); + assign _zz_184_ = (decode_PC >>> 1); + assign _zz_185_ = _zz_75_[3 : 3]; + assign _zz_186_ = _zz_75_[8 : 8]; + assign _zz_187_ = _zz_75_[23 : 23]; + assign _zz_188_ = _zz_75_[28 : 28]; + assign _zz_189_ = _zz_75_[16 : 16]; + assign _zz_190_ = _zz_75_[20 : 20]; + assign _zz_191_ = _zz_75_[9 : 9]; + assign _zz_192_ = (_zz_49_ & (~ _zz_193_)); + assign _zz_193_ = (_zz_49_ - (2'b01)); + assign _zz_194_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; + assign _zz_195_ = {29'd0, _zz_194_}; + assign _zz_196_ = (IBusSimplePlugin_pending_value + _zz_198_); + assign _zz_197_ = IBusSimplePlugin_pending_inc; + assign _zz_198_ = {2'd0, _zz_197_}; + assign _zz_199_ = IBusSimplePlugin_pending_dec; + assign _zz_200_ = {2'd0, _zz_199_}; + assign _zz_201_ = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000))); + assign _zz_202_ = {2'd0, _zz_201_}; + assign _zz_203_ = execute_SRC_LESS; + assign _zz_204_ = (3'b100); + assign _zz_205_ = decode_INSTRUCTION[19 : 15]; + assign _zz_206_ = decode_INSTRUCTION[31 : 20]; + assign _zz_207_ = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_208_ = ($signed(_zz_209_) + $signed(_zz_212_)); + assign _zz_209_ = ($signed(_zz_210_) + $signed(_zz_211_)); + assign _zz_210_ = execute_SRC1; + assign _zz_211_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_212_ = (execute_SRC_USE_SUB_LESS ? _zz_213_ : _zz_214_); + assign _zz_213_ = 32'h00000001; + assign _zz_214_ = 32'h0; + assign _zz_215_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_216_ = execute_INSTRUCTION[31 : 20]; + assign _zz_217_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_218_ = {1'd0, memory_Mul16Plugin_hl}; + assign _zz_219_ = (_zz_220_ + _zz_221_); + assign _zz_220_ = (writeBack_MUL[63 : 32] + (~ writeBack_Mul16Plugin_a)); + assign _zz_221_ = ((~ writeBack_Mul16Plugin_b) + 32'h00000002); + assign _zz_222_ = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_223_ = {5'd0, _zz_222_}; + assign _zz_224_ = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_225_ = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_226_ = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_227_ = {_zz_119_,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_228_ = _zz_229_; + assign _zz_229_ = _zz_230_; + assign _zz_230_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_120_) : _zz_120_)} + _zz_232_); + assign _zz_231_ = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_232_ = {32'd0, _zz_231_}; + assign _zz_233_ = _zz_122_; + assign _zz_234_ = {32'd0, _zz_233_}; + assign _zz_235_ = _zz_121_; + assign _zz_236_ = {31'd0, _zz_235_}; + assign _zz_237_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_238_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_239_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_240_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_241_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_242_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_243_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_244_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_245_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_246_ = 1'b1; + assign _zz_247_ = 1'b1; + assign _zz_248_ = 32'h02004064; + assign _zz_249_ = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_250_ = ((decode_INSTRUCTION & _zz_258_) == 32'h0); + assign _zz_251_ = {_zz_80_,(_zz_259_ == _zz_260_)}; + assign _zz_252_ = ((decode_INSTRUCTION & 32'h00004004) == 32'h00004000); + assign _zz_253_ = _zz_80_; + assign _zz_254_ = (1'b0); + assign _zz_255_ = ({_zz_78_,_zz_261_} != (2'b00)); + assign _zz_256_ = (_zz_262_ != (1'b0)); + assign _zz_257_ = {(_zz_263_ != _zz_264_),{_zz_265_,{_zz_266_,_zz_267_}}}; + assign _zz_258_ = 32'h00000018; + assign _zz_259_ = (decode_INSTRUCTION & 32'h00005004); + assign _zz_260_ = 32'h00001000; + assign _zz_261_ = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_262_ = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_263_ = {(_zz_268_ == _zz_269_),(_zz_270_ == _zz_271_)}; + assign _zz_264_ = (2'b00); + assign _zz_265_ = (_zz_79_ != (1'b0)); + assign _zz_266_ = ({_zz_272_,_zz_273_} != (2'b00)); + assign _zz_267_ = {(_zz_274_ != _zz_275_),{_zz_276_,{_zz_277_,_zz_278_}}}; + assign _zz_268_ = (decode_INSTRUCTION & 32'h00000034); + assign _zz_269_ = 32'h00000020; + assign _zz_270_ = (decode_INSTRUCTION & 32'h00000064); + assign _zz_271_ = 32'h00000020; + assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == 32'h00000040); + assign _zz_273_ = ((decode_INSTRUCTION & _zz_280_) == 32'h00000040); + assign _zz_274_ = ((decode_INSTRUCTION & _zz_281_) == 32'h00000024); + assign _zz_275_ = (1'b0); + assign _zz_276_ = (_zz_79_ != (1'b0)); + assign _zz_277_ = ({_zz_282_,_zz_283_} != (2'b00)); + assign _zz_278_ = {(_zz_284_ != _zz_285_),{_zz_286_,{_zz_287_,_zz_288_}}}; + assign _zz_279_ = 32'h00000050; + assign _zz_280_ = 32'h00103040; + assign _zz_281_ = 32'h00000064; + assign _zz_282_ = ((decode_INSTRUCTION & _zz_289_) == 32'h00005010); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_290_) == 32'h00005020); + assign _zz_284_ = {(_zz_291_ == _zz_292_),{_zz_293_,_zz_294_}}; + assign _zz_285_ = (3'b000); + assign _zz_286_ = ({_zz_295_,{_zz_296_,_zz_297_}} != (3'b000)); + assign _zz_287_ = ({_zz_298_,_zz_299_} != 5'h0); + assign _zz_288_ = {(_zz_300_ != _zz_301_),{_zz_302_,{_zz_303_,_zz_304_}}}; + assign _zz_289_ = 32'h00007034; + assign _zz_290_ = 32'h02007064; + assign _zz_291_ = (decode_INSTRUCTION & 32'h40003054); + assign _zz_292_ = 32'h40001010; + assign _zz_293_ = ((decode_INSTRUCTION & _zz_305_) == 32'h00001010); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_306_) == 32'h00001010); + assign _zz_295_ = ((decode_INSTRUCTION & _zz_307_) == 32'h00000040); + assign _zz_296_ = (_zz_308_ == _zz_309_); + assign _zz_297_ = (_zz_310_ == _zz_311_); + assign _zz_298_ = _zz_77_; + assign _zz_299_ = {_zz_312_,{_zz_313_,_zz_314_}}; + assign _zz_300_ = (_zz_315_ == _zz_316_); + assign _zz_301_ = (1'b0); + assign _zz_302_ = (_zz_317_ != (1'b0)); + assign _zz_303_ = (_zz_318_ != _zz_319_); + assign _zz_304_ = {_zz_320_,{_zz_321_,_zz_322_}}; + assign _zz_305_ = 32'h00007034; + assign _zz_306_ = 32'h02007054; + assign _zz_307_ = 32'h00000044; + assign _zz_308_ = (decode_INSTRUCTION & 32'h00002014); + assign _zz_309_ = 32'h00002010; + assign _zz_310_ = (decode_INSTRUCTION & 32'h40000034); + assign _zz_311_ = 32'h40000030; + assign _zz_312_ = ((decode_INSTRUCTION & 32'h00002030) == 32'h00002010); + assign _zz_313_ = ((decode_INSTRUCTION & _zz_323_) == 32'h00000010); + assign _zz_314_ = {(_zz_324_ == _zz_325_),(_zz_326_ == _zz_327_)}; + assign _zz_315_ = (decode_INSTRUCTION & 32'h02004074); + assign _zz_316_ = 32'h02000030; + assign _zz_317_ = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_318_ = ((decode_INSTRUCTION & _zz_328_) == 32'h0); + assign _zz_319_ = (1'b0); + assign _zz_320_ = ({_zz_329_,{_zz_330_,_zz_331_}} != 5'h0); + assign _zz_321_ = ({_zz_332_,_zz_333_} != (2'b00)); + assign _zz_322_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_323_ = 32'h00001030; + assign _zz_324_ = (decode_INSTRUCTION & 32'h02002060); + assign _zz_325_ = 32'h00002020; + assign _zz_326_ = (decode_INSTRUCTION & 32'h02003020); + assign _zz_327_ = 32'h00000020; + assign _zz_328_ = 32'h00000058; + assign _zz_329_ = ((decode_INSTRUCTION & _zz_339_) == 32'h00000040); + assign _zz_330_ = _zz_77_; + assign _zz_331_ = {_zz_340_,{_zz_341_,_zz_342_}}; + assign _zz_332_ = (_zz_343_ == _zz_344_); + assign _zz_333_ = (_zz_345_ == _zz_346_); + assign _zz_334_ = {_zz_78_,{_zz_347_,_zz_348_}}; + assign _zz_335_ = 6'h0; + assign _zz_336_ = (_zz_349_ != (1'b0)); + assign _zz_337_ = (_zz_350_ != _zz_351_); + assign _zz_338_ = {_zz_352_,{_zz_353_,_zz_354_}}; + assign _zz_339_ = 32'h00000040; + assign _zz_340_ = ((decode_INSTRUCTION & _zz_355_) == 32'h00004020); + assign _zz_341_ = (_zz_356_ == _zz_357_); + assign _zz_342_ = (_zz_358_ == _zz_359_); + assign _zz_343_ = (decode_INSTRUCTION & 32'h00001050); + assign _zz_344_ = 32'h00001050; + assign _zz_345_ = (decode_INSTRUCTION & 32'h00002050); + assign _zz_346_ = 32'h00002050; + assign _zz_347_ = (_zz_360_ == _zz_361_); + assign _zz_348_ = {_zz_362_,{_zz_363_,_zz_364_}}; + assign _zz_349_ = ((decode_INSTRUCTION & _zz_365_) == 32'h00000050); + assign _zz_350_ = {_zz_77_,_zz_366_}; + assign _zz_351_ = (2'b00); + assign _zz_352_ = ({_zz_367_,_zz_368_} != (2'b00)); + assign _zz_353_ = (_zz_369_ != _zz_370_); + assign _zz_354_ = {_zz_371_,{_zz_372_,_zz_373_}}; + assign _zz_355_ = 32'h00004020; + assign _zz_356_ = (decode_INSTRUCTION & 32'h00000030); + assign _zz_357_ = 32'h00000010; + assign _zz_358_ = (decode_INSTRUCTION & 32'h02000020); + assign _zz_359_ = 32'h00000020; + assign _zz_360_ = (decode_INSTRUCTION & 32'h00001010); + assign _zz_361_ = 32'h00001010; + assign _zz_362_ = ((decode_INSTRUCTION & _zz_374_) == 32'h00002010); + assign _zz_363_ = (_zz_375_ == _zz_376_); + assign _zz_364_ = {_zz_377_,_zz_378_}; + assign _zz_365_ = 32'h10003050; + assign _zz_366_ = ((decode_INSTRUCTION & _zz_379_) == 32'h00000020); + assign _zz_367_ = _zz_77_; + assign _zz_368_ = (_zz_380_ == _zz_381_); + assign _zz_369_ = {_zz_382_,_zz_76_}; + assign _zz_370_ = (2'b00); + assign _zz_371_ = ({_zz_383_,_zz_384_} != (2'b00)); + assign _zz_372_ = (_zz_385_ != _zz_386_); + assign _zz_373_ = {_zz_387_,{_zz_388_,_zz_389_}}; + assign _zz_374_ = 32'h00002010; + assign _zz_375_ = (decode_INSTRUCTION & 32'h00000050); + assign _zz_376_ = 32'h00000010; + assign _zz_377_ = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_378_ = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_379_ = 32'h00000070; + assign _zz_380_ = (decode_INSTRUCTION & 32'h00000020); + assign _zz_381_ = 32'h0; + assign _zz_382_ = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_383_ = ((decode_INSTRUCTION & _zz_390_) == 32'h00000004); + assign _zz_384_ = _zz_76_; + assign _zz_385_ = {(_zz_391_ == _zz_392_),(_zz_393_ == _zz_394_)}; + assign _zz_386_ = (2'b00); + assign _zz_387_ = ((_zz_395_ == _zz_396_) != (1'b0)); + assign _zz_388_ = (_zz_397_ != (1'b0)); + assign _zz_389_ = (_zz_398_ != (1'b0)); + assign _zz_390_ = 32'h00000044; + assign _zz_391_ = (decode_INSTRUCTION & 32'h00002010); + assign _zz_392_ = 32'h00002000; + assign _zz_393_ = (decode_INSTRUCTION & 32'h00005000); + assign _zz_394_ = 32'h00001000; + assign _zz_395_ = (decode_INSTRUCTION & 32'h00001000); + assign _zz_396_ = 32'h00001000; + assign _zz_397_ = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_398_ = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + always @ (posedge mainClock) begin + if(_zz_246_) begin + _zz_137_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge mainClock) begin + if(_zz_247_) begin + _zz_138_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge mainClock) begin + if(_zz_35_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_135_ ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_136_ ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE "; + default : _zz_1__string = "????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE "; + default : _zz_2__string = "????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE "; + default : _zz_3__string = "????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_7_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_7__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_7__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_7__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_7__string = "JALR"; + default : _zz_7__string = "????"; + endcase + end + always @(*) begin + case(_zz_8_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8__string = "JALR"; + default : _zz_8__string = "????"; + endcase + end + always @(*) begin + case(_zz_9_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9__string = "JALR"; + default : _zz_9__string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 "; + default : _zz_10__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; + default : _zz_11__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; + default : _zz_12__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14__string = "SRA_1 "; + default : _zz_14__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET"; + default : _zz_16__string = "????"; + endcase + end + always @(*) begin + case(_zz_17_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET"; + default : _zz_17__string = "????"; + endcase + end + always @(*) begin + case(_zz_18_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET"; + default : _zz_18__string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_19_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET"; + default : _zz_19__string = "????"; + endcase + end + always @(*) begin + case(_zz_20_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET"; + default : _zz_20__string = "????"; + endcase + end + always @(*) begin + case(_zz_21_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET"; + default : _zz_21__string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_22_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_22__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_22__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_22__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_22__string = "JALR"; + default : _zz_22__string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_24_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; + default : _zz_24__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_25_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_25__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_25__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_25__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_25__string = "SRA_1 "; + default : _zz_25__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_28_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_28__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_28__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_28__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_28__string = "PC "; + default : _zz_28__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_30_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_30__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_30__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_30__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_30__string = "URS1 "; + default : _zz_30__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_31_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_31__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_31__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_31__string = "BITWISE "; + default : _zz_31__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32__string = "AND_1"; + default : _zz_32__string = "?????"; + endcase + end + always @(*) begin + case(_zz_36_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36__string = "BITWISE "; + default : _zz_36__string = "????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_37__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_37__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_37__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_37__string = "JALR"; + default : _zz_37__string = "????"; + endcase + end + always @(*) begin + case(_zz_38_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1 "; + default : _zz_38__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_39__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_39__string = "XRET"; + default : _zz_39__string = "????"; + endcase + end + always @(*) begin + case(_zz_40_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; + default : _zz_40__string = "???"; + endcase + end + always @(*) begin + case(_zz_41_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41__string = "URS1 "; + default : _zz_41__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_42_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_42__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_42__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_42__string = "AND_1"; + default : _zz_42__string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_44_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_44__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_44__string = "XRET"; + default : _zz_44__string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_45_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_45__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_45__string = "XRET"; + default : _zz_45__string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_46_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_46__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_46__string = "XRET"; + default : _zz_46__string = "????"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81__string = "AND_1"; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(_zz_82_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_82__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_82__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_82__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_82__string = "URS1 "; + default : _zz_82__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_83_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_83__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_83__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_83__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_83__string = "PC "; + default : _zz_83__string = "???"; + endcase + end + always @(*) begin + case(_zz_84_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_84__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_84__string = "XRET"; + default : _zz_84__string = "????"; + endcase + end + always @(*) begin + case(_zz_85_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_85__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_85__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_85__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_85__string = "SRA_1 "; + default : _zz_85__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_86_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_86__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_86__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_86__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_86__string = "JALR"; + default : _zz_86__string = "????"; + endcase + end + always @(*) begin + case(_zz_87_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_87__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_87__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_87__string = "BITWISE "; + default : _zz_87__string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + `endif + + assign decode_MEMORY_ENABLE = _zz_168_[0]; + assign execute_BRANCH_DO = _zz_111_; + assign decode_IS_RS2_SIGNED = _zz_169_[0]; + assign execute_MUL_HH = (execute_Mul16Plugin_aHigh * execute_Mul16Plugin_bHigh); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign decode_ALU_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_IS_CSR = _zz_170_[0]; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_DIV = _zz_171_[0]; + assign execute_MUL_LH = (execute_Mul16Plugin_aLow * execute_Mul16Plugin_bHigh); + assign decode_MEMORY_STORE = _zz_172_[0]; + assign execute_MUL_HL = (execute_Mul16Plugin_aHigh * execute_Mul16Plugin_bLow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign execute_SHIFT_RIGHT = _zz_174_; + assign memory_PC = execute_to_memory_PC; + assign decode_IS_RS1_SIGNED = _zz_176_[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_177_[0]; + assign memory_MUL = {_zz_178_,memory_Mul16Plugin_ll[15 : 0]}; + assign memory_SRC2 = execute_to_memory_SRC2; + assign decode_SRC2 = _zz_95_; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_180_[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_181_[0]; + assign decode_BRANCH_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || (((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_182_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_183_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_184_))))); + assign memory_SRC1 = execute_to_memory_SRC1; + assign decode_SRC1 = _zz_90_; + assign decode_SRC_LESS_UNSIGNED = _zz_185_[0]; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_89_; + assign _zz_10_ = _zz_11_; + assign decode_SHIFT_CTRL = _zz_12_; + assign _zz_13_ = _zz_14_; + assign _zz_15_ = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ENV_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_MUL_LL = (execute_Mul16Plugin_aLow * execute_Mul16Plugin_bLow); + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_186_[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_MUL = memory_to_writeBack_MUL; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_SRC2 = memory_to_writeBack_SRC2; + assign writeBack_SRC1 = memory_to_writeBack_SRC1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_22_; + assign decode_RS2_USE = _zz_187_[0]; + assign decode_RS1_USE = _zz_188_[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_100_)begin + if((_zz_101_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_102_; + end + end + if(_zz_139_)begin + if(_zz_140_)begin + if(_zz_104_)begin + decode_RS2 = _zz_47_; + end + end + end + if(_zz_141_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_106_)begin + decode_RS2 = _zz_23_; + end + end + end + if(_zz_142_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_108_)begin + decode_RS2 = _zz_43_; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_100_)begin + if((_zz_101_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_102_; + end + end + if(_zz_139_)begin + if(_zz_140_)begin + if(_zz_103_)begin + decode_RS1 = _zz_47_; + end + end + end + if(_zz_141_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_105_)begin + decode_RS1 = _zz_23_; + end + end + end + if(_zz_142_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_107_)begin + decode_RS1 = _zz_43_; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_23_ = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_23_ = _zz_97_; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_23_ = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_143_)begin + _zz_23_ = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_24_; + assign execute_SHIFT_CTRL = _zz_25_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_26_ = decode_PC; + assign _zz_27_ = decode_RS2; + assign decode_SRC2_CTRL = _zz_28_; + assign _zz_29_ = decode_RS1; + assign decode_SRC1_CTRL = _zz_30_; + assign decode_SRC_USE_SUB_LESS = _zz_189_[0]; + assign decode_SRC_ADD_ZERO = _zz_190_[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_31_; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_ALU_BITWISE_CTRL = _zz_32_; + assign _zz_33_ = writeBack_INSTRUCTION; + assign _zz_34_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_35_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_35_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_191_[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_43_ = execute_REGFILE_WRITE_DATA; + if(_zz_144_)begin + _zz_43_ = execute_CsrPlugin_readData; + end + end + + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_44_; + assign execute_ENV_CTRL = _zz_45_; + assign writeBack_ENV_CTRL = _zz_46_; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_47_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_47_ = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_167_) + 2'b00 : begin + _zz_47_ = writeBack_MUL[31 : 0]; + end + default : begin + _zz_47_ = _zz_219_; + end + endcase + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = 1'b0; + always @ (*) begin + _zz_48_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_48_ = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + end + 3'b100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_98_ || _zz_99_)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65_)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_144_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if(_zz_145_)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_145_)begin + if(_zz_146_)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(_zz_145_)begin + if(_zz_146_)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_143_)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_147_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_148_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(_zz_147_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_148_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_145_)begin + if(_zz_146_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_149_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid || IBusSimplePlugin_iBusRsp_stages_2_input_valid))begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_147_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_148_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_147_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_148_)begin + case(_zz_150_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)); + assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid} != (2'b00)); + assign _zz_49_ = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_192_[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_195_); + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + assign _zz_50_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_50_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_50_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_51_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_51_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_51_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'b0; + assign _zz_52_ = (! IBusSimplePlugin_iBusRsp_stages_2_halt); + assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_ready && _zz_52_); + assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = (IBusSimplePlugin_iBusRsp_stages_2_input_valid && _zz_52_); + assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = IBusSimplePlugin_iBusRsp_stages_2_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_53_; + assign _zz_53_ = ((1'b0 && (! _zz_54_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_54_ = _zz_55_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_54_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_56_)) || IBusSimplePlugin_iBusRsp_stages_2_input_ready); + assign _zz_56_ = _zz_57_; + assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = _zz_56_; + assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = _zz_58_; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_59_; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_60_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_61_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_62_; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_63_; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_5; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + end + default : begin + end + endcase + end + + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_196_ - _zz_200_); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && (IBusSimplePlugin_pending_value != (3'b111))); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_1_input_payload[31 : 2],(2'b00)}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000)) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == (3'b000))); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_135_ = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_135_); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_2_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_2_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_64_ = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_64_); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_64_); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign _zz_65_ = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65_)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_66_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_66_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_66_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_66_; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_67_ = (4'b0001); + end + 2'b01 : begin + _zz_67_ = (4'b0011); + end + default : begin + _zz_67_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_67_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_68_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_69_[31] = _zz_68_; + _zz_69_[30] = _zz_68_; + _zz_69_[29] = _zz_68_; + _zz_69_[28] = _zz_68_; + _zz_69_[27] = _zz_68_; + _zz_69_[26] = _zz_68_; + _zz_69_[25] = _zz_68_; + _zz_69_[24] = _zz_68_; + _zz_69_[23] = _zz_68_; + _zz_69_[22] = _zz_68_; + _zz_69_[21] = _zz_68_; + _zz_69_[20] = _zz_68_; + _zz_69_[19] = _zz_68_; + _zz_69_[18] = _zz_68_; + _zz_69_[17] = _zz_68_; + _zz_69_[16] = _zz_68_; + _zz_69_[15] = _zz_68_; + _zz_69_[14] = _zz_68_; + _zz_69_[13] = _zz_68_; + _zz_69_[12] = _zz_68_; + _zz_69_[11] = _zz_68_; + _zz_69_[10] = _zz_68_; + _zz_69_[9] = _zz_68_; + _zz_69_[8] = _zz_68_; + _zz_69_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_70_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_71_[31] = _zz_70_; + _zz_71_[30] = _zz_70_; + _zz_71_[29] = _zz_70_; + _zz_71_[28] = _zz_70_; + _zz_71_[27] = _zz_70_; + _zz_71_[26] = _zz_70_; + _zz_71_[25] = _zz_70_; + _zz_71_[24] = _zz_70_; + _zz_71_[23] = _zz_70_; + _zz_71_[22] = _zz_70_; + _zz_71_[21] = _zz_70_; + _zz_71_[20] = _zz_70_; + _zz_71_[19] = _zz_70_; + _zz_71_[18] = _zz_70_; + _zz_71_[17] = _zz_70_; + _zz_71_[16] = _zz_70_; + _zz_71_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_165_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_69_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_71_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_72_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_73_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_74_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exception = 1'b0; + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + assign CsrPlugin_trapCause = CsrPlugin_interrupt_code; + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_166_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_76_ = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_77_ = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_78_ = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_79_ = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_80_ = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_75_ = {(((decode_INSTRUCTION & _zz_248_) == 32'h02004020) != (1'b0)),{({_zz_249_,{_zz_250_,_zz_251_}} != (4'b0000)),{(_zz_252_ != (1'b0)),{(_zz_253_ != _zz_254_),{_zz_255_,{_zz_256_,_zz_257_}}}}}}; + assign _zz_81_ = _zz_75_[2 : 1]; + assign _zz_42_ = _zz_81_; + assign _zz_82_ = _zz_75_[5 : 4]; + assign _zz_41_ = _zz_82_; + assign _zz_83_ = _zz_75_[7 : 6]; + assign _zz_40_ = _zz_83_; + assign _zz_84_ = _zz_75_[13 : 13]; + assign _zz_39_ = _zz_84_; + assign _zz_85_ = _zz_75_[18 : 17]; + assign _zz_38_ = _zz_85_; + assign _zz_86_ = _zz_75_[25 : 24]; + assign _zz_37_ = _zz_86_; + assign _zz_87_ = _zz_75_[27 : 26]; + assign _zz_36_ = _zz_87_; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_137_; + assign decode_RegFilePlugin_rs2Data = _zz_138_; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_34_ && writeBack_arbitration_isFiring); + if(_zz_88_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_33_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_47_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_89_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_89_ = {31'd0, _zz_203_}; + end + default : begin + _zz_89_ = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_90_ = _zz_29_; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_90_ = {29'd0, _zz_204_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_90_ = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_90_ = {27'd0, _zz_205_}; + end + endcase + end + + assign _zz_91_ = _zz_206_[11]; + always @ (*) begin + _zz_92_[19] = _zz_91_; + _zz_92_[18] = _zz_91_; + _zz_92_[17] = _zz_91_; + _zz_92_[16] = _zz_91_; + _zz_92_[15] = _zz_91_; + _zz_92_[14] = _zz_91_; + _zz_92_[13] = _zz_91_; + _zz_92_[12] = _zz_91_; + _zz_92_[11] = _zz_91_; + _zz_92_[10] = _zz_91_; + _zz_92_[9] = _zz_91_; + _zz_92_[8] = _zz_91_; + _zz_92_[7] = _zz_91_; + _zz_92_[6] = _zz_91_; + _zz_92_[5] = _zz_91_; + _zz_92_[4] = _zz_91_; + _zz_92_[3] = _zz_91_; + _zz_92_[2] = _zz_91_; + _zz_92_[1] = _zz_91_; + _zz_92_[0] = _zz_91_; + end + + assign _zz_93_ = _zz_207_[11]; + always @ (*) begin + _zz_94_[19] = _zz_93_; + _zz_94_[18] = _zz_93_; + _zz_94_[17] = _zz_93_; + _zz_94_[16] = _zz_93_; + _zz_94_[15] = _zz_93_; + _zz_94_[14] = _zz_93_; + _zz_94_[13] = _zz_93_; + _zz_94_[12] = _zz_93_; + _zz_94_[11] = _zz_93_; + _zz_94_[10] = _zz_93_; + _zz_94_[9] = _zz_93_; + _zz_94_[8] = _zz_93_; + _zz_94_[7] = _zz_93_; + _zz_94_[6] = _zz_93_; + _zz_94_[5] = _zz_93_; + _zz_94_[4] = _zz_93_; + _zz_94_[3] = _zz_93_; + _zz_94_[2] = _zz_93_; + _zz_94_[1] = _zz_93_; + _zz_94_[0] = _zz_93_; + end + + always @ (*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_95_ = _zz_27_; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_95_ = {_zz_92_,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_95_ = {_zz_94_,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_95_ = _zz_26_; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_208_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_96_[0] = execute_SRC1[31]; + _zz_96_[1] = execute_SRC1[30]; + _zz_96_[2] = execute_SRC1[29]; + _zz_96_[3] = execute_SRC1[28]; + _zz_96_[4] = execute_SRC1[27]; + _zz_96_[5] = execute_SRC1[26]; + _zz_96_[6] = execute_SRC1[25]; + _zz_96_[7] = execute_SRC1[24]; + _zz_96_[8] = execute_SRC1[23]; + _zz_96_[9] = execute_SRC1[22]; + _zz_96_[10] = execute_SRC1[21]; + _zz_96_[11] = execute_SRC1[20]; + _zz_96_[12] = execute_SRC1[19]; + _zz_96_[13] = execute_SRC1[18]; + _zz_96_[14] = execute_SRC1[17]; + _zz_96_[15] = execute_SRC1[16]; + _zz_96_[16] = execute_SRC1[15]; + _zz_96_[17] = execute_SRC1[14]; + _zz_96_[18] = execute_SRC1[13]; + _zz_96_[19] = execute_SRC1[12]; + _zz_96_[20] = execute_SRC1[11]; + _zz_96_[21] = execute_SRC1[10]; + _zz_96_[22] = execute_SRC1[9]; + _zz_96_[23] = execute_SRC1[8]; + _zz_96_[24] = execute_SRC1[7]; + _zz_96_[25] = execute_SRC1[6]; + _zz_96_[26] = execute_SRC1[5]; + _zz_96_[27] = execute_SRC1[4]; + _zz_96_[28] = execute_SRC1[3]; + _zz_96_[29] = execute_SRC1[2]; + _zz_96_[30] = execute_SRC1[1]; + _zz_96_[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_96_ : execute_SRC1); + always @ (*) begin + _zz_97_[0] = memory_SHIFT_RIGHT[31]; + _zz_97_[1] = memory_SHIFT_RIGHT[30]; + _zz_97_[2] = memory_SHIFT_RIGHT[29]; + _zz_97_[3] = memory_SHIFT_RIGHT[28]; + _zz_97_[4] = memory_SHIFT_RIGHT[27]; + _zz_97_[5] = memory_SHIFT_RIGHT[26]; + _zz_97_[6] = memory_SHIFT_RIGHT[25]; + _zz_97_[7] = memory_SHIFT_RIGHT[24]; + _zz_97_[8] = memory_SHIFT_RIGHT[23]; + _zz_97_[9] = memory_SHIFT_RIGHT[22]; + _zz_97_[10] = memory_SHIFT_RIGHT[21]; + _zz_97_[11] = memory_SHIFT_RIGHT[20]; + _zz_97_[12] = memory_SHIFT_RIGHT[19]; + _zz_97_[13] = memory_SHIFT_RIGHT[18]; + _zz_97_[14] = memory_SHIFT_RIGHT[17]; + _zz_97_[15] = memory_SHIFT_RIGHT[16]; + _zz_97_[16] = memory_SHIFT_RIGHT[15]; + _zz_97_[17] = memory_SHIFT_RIGHT[14]; + _zz_97_[18] = memory_SHIFT_RIGHT[13]; + _zz_97_[19] = memory_SHIFT_RIGHT[12]; + _zz_97_[20] = memory_SHIFT_RIGHT[11]; + _zz_97_[21] = memory_SHIFT_RIGHT[10]; + _zz_97_[22] = memory_SHIFT_RIGHT[9]; + _zz_97_[23] = memory_SHIFT_RIGHT[8]; + _zz_97_[24] = memory_SHIFT_RIGHT[7]; + _zz_97_[25] = memory_SHIFT_RIGHT[6]; + _zz_97_[26] = memory_SHIFT_RIGHT[5]; + _zz_97_[27] = memory_SHIFT_RIGHT[4]; + _zz_97_[28] = memory_SHIFT_RIGHT[3]; + _zz_97_[29] = memory_SHIFT_RIGHT[2]; + _zz_97_[30] = memory_SHIFT_RIGHT[1]; + _zz_97_[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_98_ = 1'b0; + if(_zz_151_)begin + if(_zz_152_)begin + if(_zz_103_)begin + _zz_98_ = 1'b1; + end + end + end + if(_zz_153_)begin + if(_zz_154_)begin + if(_zz_105_)begin + _zz_98_ = 1'b1; + end + end + end + if(_zz_155_)begin + if(_zz_156_)begin + if(_zz_107_)begin + _zz_98_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_98_ = 1'b0; + end + end + + always @ (*) begin + _zz_99_ = 1'b0; + if(_zz_151_)begin + if(_zz_152_)begin + if(_zz_104_)begin + _zz_99_ = 1'b1; + end + end + end + if(_zz_153_)begin + if(_zz_154_)begin + if(_zz_106_)begin + _zz_99_ = 1'b1; + end + end + end + if(_zz_155_)begin + if(_zz_156_)begin + if(_zz_108_)begin + _zz_99_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_99_ = 1'b0; + end + end + + assign _zz_103_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_104_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_105_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_106_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_107_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_108_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_109_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_109_ == (3'b000))) begin + _zz_110_ = execute_BranchPlugin_eq; + end else if((_zz_109_ == (3'b001))) begin + _zz_110_ = (! execute_BranchPlugin_eq); + end else if((((_zz_109_ & (3'b101)) == (3'b101)))) begin + _zz_110_ = (! execute_SRC_LESS); + end else begin + _zz_110_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_111_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_111_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_111_ = 1'b1; + end + default : begin + _zz_111_ = _zz_110_; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_112_ = _zz_215_[19]; + always @ (*) begin + _zz_113_[10] = _zz_112_; + _zz_113_[9] = _zz_112_; + _zz_113_[8] = _zz_112_; + _zz_113_[7] = _zz_112_; + _zz_113_[6] = _zz_112_; + _zz_113_[5] = _zz_112_; + _zz_113_[4] = _zz_112_; + _zz_113_[3] = _zz_112_; + _zz_113_[2] = _zz_112_; + _zz_113_[1] = _zz_112_; + _zz_113_[0] = _zz_112_; + end + + assign _zz_114_ = _zz_216_[11]; + always @ (*) begin + _zz_115_[19] = _zz_114_; + _zz_115_[18] = _zz_114_; + _zz_115_[17] = _zz_114_; + _zz_115_[16] = _zz_114_; + _zz_115_[15] = _zz_114_; + _zz_115_[14] = _zz_114_; + _zz_115_[13] = _zz_114_; + _zz_115_[12] = _zz_114_; + _zz_115_[11] = _zz_114_; + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_217_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_118_ = {{_zz_113_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_118_ = {_zz_115_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_118_ = {{_zz_117_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_118_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign execute_Mul16Plugin_a = execute_SRC1; + assign execute_Mul16Plugin_b = execute_SRC2; + assign execute_Mul16Plugin_aLow = execute_Mul16Plugin_a[15 : 0]; + assign execute_Mul16Plugin_bLow = execute_Mul16Plugin_b[15 : 0]; + assign execute_Mul16Plugin_aHigh = execute_Mul16Plugin_a[31 : 16]; + assign execute_Mul16Plugin_bHigh = execute_Mul16Plugin_b[31 : 16]; + assign memory_Mul16Plugin_ll = memory_MUL_LL; + assign memory_Mul16Plugin_lh = {1'd0, memory_MUL_LH}; + assign memory_Mul16Plugin_hl = memory_MUL_HL; + assign memory_Mul16Plugin_hh = memory_MUL_HH; + assign memory_Mul16Plugin_hllh = (memory_Mul16Plugin_lh + _zz_218_); + always @ (*) begin + case(_zz_157_) + 2'b01 : begin + writeBack_Mul16Plugin_aSigned = 1'b1; + end + 2'b10 : begin + writeBack_Mul16Plugin_aSigned = 1'b1; + end + default : begin + writeBack_Mul16Plugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_157_) + 2'b01 : begin + writeBack_Mul16Plugin_bSigned = 1'b1; + end + 2'b10 : begin + writeBack_Mul16Plugin_bSigned = 1'b0; + end + default : begin + writeBack_Mul16Plugin_bSigned = 1'b0; + end + endcase + end + + assign writeBack_Mul16Plugin_a = ((writeBack_Mul16Plugin_aSigned && writeBack_SRC1[31]) ? writeBack_SRC2 : 32'h0); + assign writeBack_Mul16Plugin_b = ((writeBack_Mul16Plugin_bSigned && writeBack_SRC2[31]) ? writeBack_SRC1 : 32'h0); + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_143_)begin + if(_zz_158_)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_159_)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_223_); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_119_ = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_119_[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_224_); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_225_ : _zz_226_); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_227_[31:0]; + assign _zz_120_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_121_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_122_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_123_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_123_[31 : 0] = execute_RS1; + end + + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_124_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusSimplePlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + IBusSimplePlugin_injectionPort_valid = 1'b1; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + default : begin + end + endcase + end + end + + assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_21_ = decode_ENV_CTRL; + assign _zz_18_ = execute_ENV_CTRL; + assign _zz_16_ = memory_ENV_CTRL; + assign _zz_19_ = _zz_39_; + assign _zz_45_ = decode_to_execute_ENV_CTRL; + assign _zz_44_ = execute_to_memory_ENV_CTRL; + assign _zz_46_ = memory_to_writeBack_ENV_CTRL; + assign _zz_14_ = decode_SHIFT_CTRL; + assign _zz_11_ = execute_SHIFT_CTRL; + assign _zz_12_ = _zz_38_; + assign _zz_25_ = decode_to_execute_SHIFT_CTRL; + assign _zz_24_ = execute_to_memory_SHIFT_CTRL; + assign _zz_30_ = _zz_41_; + assign _zz_9_ = decode_BRANCH_CTRL; + assign _zz_7_ = _zz_37_; + assign _zz_22_ = decode_to_execute_BRANCH_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_42_; + assign _zz_32_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_28_ = _zz_40_; + assign _zz_3_ = decode_ALU_CTRL; + assign _zz_1_ = _zz_36_; + assign _zz_31_ = decode_to_execute_ALU_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusSimplePlugin_injectionPort_ready = 1'b0; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + end + 3'b011 : begin + end + 3'b100 : begin + IBusSimplePlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_126_ = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_126_[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_126_[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_126_[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_127_ = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_127_[11 : 11] = CsrPlugin_mip_MEIP; + _zz_127_[7 : 7] = CsrPlugin_mip_MTIP; + _zz_127_[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_128_ = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_128_[11 : 11] = CsrPlugin_mie_MEIE; + _zz_128_[7 : 7] = CsrPlugin_mie_MTIE; + _zz_128_[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_129_ = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_129_[31 : 2] = CsrPlugin_mtvec_base; + _zz_129_[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_130_ = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_130_[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_130_[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_131_ = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_131_[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_132_ = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_132_[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_133_ = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_133_[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_134_ = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_134_[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + assign execute_CsrPlugin_readData = ((((_zz_126_ | _zz_127_) | (_zz_128_ | _zz_129_)) | ((_zz_130_ | _zz_131_) | (_zz_132_ | _zz_133_))) | _zz_134_); + assign _zz_136_ = 1'b0; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + IBusSimplePlugin_fetchPc_pcReg <= 32'h80000000; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_55_ <= 1'b0; + _zz_57_ <= 1'b0; + _zz_59_ <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusSimplePlugin_pending_value <= (3'b000); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (3'b000); + CsrPlugin_mtvec_mode <= (2'b00); + CsrPlugin_mtvec_base <= 30'h20000000; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_88_ <= 1'b1; + _zz_100_ <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_125_ <= (3'b000); + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_55_ <= 1'b0; + end + if(_zz_53_)begin + _zz_55_ <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_57_ <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + _zz_57_ <= (IBusSimplePlugin_iBusRsp_stages_1_output_valid && (! IBusSimplePlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt)begin + _zz_59_ <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_59_ <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_2_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= IBusSimplePlugin_injector_nextPcCalc_valids_4; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_202_); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= IBusSimplePlugin_pending_next; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_161_)begin + if(_zz_162_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_163_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_164_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_147_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_148_)begin + case(_zz_150_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_74_,{_zz_73_,_zz_72_}} != (3'b000)) || CsrPlugin_thirdPartyWake); + _zz_88_ <= 1'b0; + _zz_100_ <= (_zz_34_ && writeBack_arbitration_isFiring); + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_23_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_125_) + 3'b000 : begin + if(IBusSimplePlugin_injectionPort_valid)begin + _zz_125_ <= (3'b001); + end + end + 3'b001 : begin + _zz_125_ <= (3'b010); + end + 3'b010 : begin + _zz_125_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_125_ <= (3'b100); + end + end + 3'b100 : begin + _zz_125_ <= (3'b000); + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_240_[0]; + CsrPlugin_mstatus_MIE <= _zz_241_[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_243_[0]; + CsrPlugin_mie_MTIE <= _zz_244_[0]; + CsrPlugin_mie_MSIE <= _zz_245_[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + end + end + + always @ (posedge mainClock) begin + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + _zz_58_ <= IBusSimplePlugin_iBusRsp_stages_1_output_payload; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_60_ <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_61_ <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_62_ <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_63_ <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_161_)begin + if(_zz_162_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_163_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_164_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_147_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + end + default : begin + end + endcase + end + _zz_101_ <= _zz_33_[11 : 7]; + _zz_102_ <= _zz_47_; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_143_)begin + if(_zz_158_)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_228_[31:0]; + end + end + end + if(_zz_159_)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_122_ ? (~ _zz_123_) : _zz_123_) + _zz_234_); + memory_MulDivIterativePlugin_rs2 <= ((_zz_121_ ? (~ execute_RS2) : execute_RS2) + _zz_236_); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_122_ ^ (_zz_121_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_20_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_17_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_15_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_27_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC1 <= execute_SRC1; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC1 <= memory_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC2 <= execute_SRC2; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC2 <= memory_SRC2; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL <= memory_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= _zz_26_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= execute_PC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= _zz_29_; + end + if((_zz_125_ != (3'b000)))begin + _zz_62_ <= IBusSimplePlugin_injectionPort_payload; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_242_[0]; + end + end + end + + always @ (posedge mainClock) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusSimplePlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_47_; + end + _zz_124_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_145_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_237_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_238_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_239_[0]; + end + end + default : begin + end + endcase + end + if(_zz_145_)begin + if(_zz_146_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_149_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module JtagBridge ( + input io_jtag_tms, + input io_jtag_tdi, + output io_jtag_tdo, + input io_jtag_tck, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input mainClock, + input resetCtrl_mainClockReset +); + wire flowCCByToggle_1__io_output_valid; + wire flowCCByToggle_1__io_output_payload_last; + wire [0:0] flowCCByToggle_1__io_output_payload_fragment; + wire _zz_2_; + wire _zz_3_; + wire [0:0] _zz_4_; + wire [3:0] _zz_5_; + wire [1:0] _zz_6_; + wire [3:0] _zz_7_; + wire [1:0] _zz_8_; + wire [3:0] _zz_9_; + wire [0:0] _zz_10_; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + reg system_rsp_valid; + reg system_rsp_payload_error; + reg [31:0] system_rsp_payload_data; + wire `JtagState_defaultEncoding_type jtag_tap_fsm_stateNext; + reg `JtagState_defaultEncoding_type jtag_tap_fsm_state = `JtagState_defaultEncoding_RESET; + reg `JtagState_defaultEncoding_type _zz_1_; + reg [3:0] jtag_tap_instruction; + reg [3:0] jtag_tap_instructionShift; + reg jtag_tap_bypass; + reg jtag_tap_tdoUnbufferd; + reg jtag_tap_tdoUnbufferd_regNext; + wire jtag_idcodeArea_instructionHit; + reg [31:0] jtag_idcodeArea_shifter; + wire jtag_writeArea_instructionHit; + reg jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + wire jtag_readArea_instructionHit; + reg [33:0] jtag_readArea_shifter; + `ifndef SYNTHESIS + reg [79:0] jtag_tap_fsm_stateNext_string; + reg [79:0] jtag_tap_fsm_state_string; + reg [79:0] _zz_1__string; + `endif + + + assign _zz_2_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT); + assign _zz_3_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT); + assign _zz_4_ = (1'b1); + assign _zz_5_ = {3'd0, _zz_4_}; + assign _zz_6_ = (2'b10); + assign _zz_7_ = {2'd0, _zz_6_}; + assign _zz_8_ = (2'b11); + assign _zz_9_ = {2'd0, _zz_8_}; + assign _zz_10_ = (1'b1); + FlowCCByToggle flowCCByToggle_1_ ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1__io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1__io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1__io_output_payload_fragment ), //o + .io_jtag_tck (io_jtag_tck ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(jtag_tap_fsm_stateNext) + `JtagState_defaultEncoding_RESET : jtag_tap_fsm_stateNext_string = "RESET "; + `JtagState_defaultEncoding_IDLE : jtag_tap_fsm_stateNext_string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : jtag_tap_fsm_stateNext_string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : jtag_tap_fsm_stateNext_string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_RESET : jtag_tap_fsm_state_string = "RESET "; + `JtagState_defaultEncoding_IDLE : jtag_tap_fsm_state_string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : jtag_tap_fsm_state_string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : jtag_tap_fsm_state_string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : jtag_tap_fsm_state_string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : jtag_tap_fsm_state_string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : jtag_tap_fsm_state_string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : jtag_tap_fsm_state_string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : jtag_tap_fsm_state_string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : jtag_tap_fsm_state_string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : jtag_tap_fsm_state_string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : jtag_tap_fsm_state_string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : jtag_tap_fsm_state_string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : jtag_tap_fsm_state_string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : jtag_tap_fsm_state_string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : jtag_tap_fsm_state_string = "DR_UPDATE "; + default : jtag_tap_fsm_state_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `JtagState_defaultEncoding_RESET : _zz_1__string = "RESET "; + `JtagState_defaultEncoding_IDLE : _zz_1__string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : _zz_1__string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : _zz_1__string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : _zz_1__string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : _zz_1__string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : _zz_1__string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : _zz_1__string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : _zz_1__string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : _zz_1__string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : _zz_1__string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : _zz_1__string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : _zz_1__string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : _zz_1__string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : _zz_1__string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : _zz_1__string = "DR_UPDATE "; + default : _zz_1__string = "??????????"; + endcase + end + `endif + + assign io_remote_cmd_valid = system_cmd_valid; + assign io_remote_cmd_payload_last = system_cmd_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_payload_fragment; + assign io_remote_rsp_ready = 1'b1; + always @ (*) begin + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IDLE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + `JtagState_defaultEncoding_IR_SELECT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IR_CAPTURE); + end + `JtagState_defaultEncoding_IR_CAPTURE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_SHIFT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_EXIT1 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_PAUSE); + end + `JtagState_defaultEncoding_IR_PAUSE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT2 : `JtagState_defaultEncoding_IR_PAUSE); + end + `JtagState_defaultEncoding_IR_EXIT2 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_UPDATE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + `JtagState_defaultEncoding_DR_SELECT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_SELECT : `JtagState_defaultEncoding_DR_CAPTURE); + end + `JtagState_defaultEncoding_DR_CAPTURE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_SHIFT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_EXIT1 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_PAUSE); + end + `JtagState_defaultEncoding_DR_PAUSE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT2 : `JtagState_defaultEncoding_DR_PAUSE); + end + `JtagState_defaultEncoding_DR_EXIT2 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_UPDATE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + default : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IDLE); + end + endcase + end + + assign jtag_tap_fsm_stateNext = _zz_1_; + always @ (*) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IR_CAPTURE : begin + end + `JtagState_defaultEncoding_IR_SHIFT : begin + jtag_tap_tdoUnbufferd = jtag_tap_instructionShift[0]; + end + `JtagState_defaultEncoding_IR_UPDATE : begin + end + default : begin + end + endcase + if(jtag_idcodeArea_instructionHit)begin + if(_zz_2_)begin + jtag_tap_tdoUnbufferd = jtag_idcodeArea_shifter[0]; + end + end + if(jtag_readArea_instructionHit)begin + if(_zz_3_)begin + jtag_tap_tdoUnbufferd = jtag_readArea_shifter[0]; + end + end + end + + assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; + assign jtag_idcodeArea_instructionHit = (jtag_tap_instruction == _zz_5_); + assign jtag_writeArea_instructionHit = (jtag_tap_instruction == _zz_7_); + always @ (*) begin + jtag_writeArea_source_valid = 1'b0; + if(jtag_writeArea_instructionHit)begin + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT))begin + jtag_writeArea_source_valid = 1'b1; + end + end + end + + assign jtag_writeArea_source_payload_last = io_jtag_tms; + assign jtag_writeArea_source_payload_fragment[0] = io_jtag_tdi; + assign system_cmd_valid = flowCCByToggle_1__io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1__io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1__io_output_payload_fragment; + assign jtag_readArea_instructionHit = (jtag_tap_instruction == _zz_9_); + always @ (posedge mainClock) begin + if(io_remote_cmd_valid)begin + system_rsp_valid <= 1'b0; + end + if((io_remote_rsp_valid && io_remote_rsp_ready))begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @ (posedge io_jtag_tck) begin + jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; + jtag_tap_bypass <= io_jtag_tdi; + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IR_CAPTURE : begin + jtag_tap_instructionShift <= jtag_tap_instruction; + end + `JtagState_defaultEncoding_IR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); + end + `JtagState_defaultEncoding_IR_UPDATE : begin + jtag_tap_instruction <= jtag_tap_instructionShift; + end + default : begin + end + endcase + if(jtag_idcodeArea_instructionHit)begin + if(_zz_2_)begin + jtag_idcodeArea_shifter <= ({io_jtag_tdi,jtag_idcodeArea_shifter} >>> 1); + end + end + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_RESET))begin + jtag_idcodeArea_shifter <= 32'h10001fff; + jtag_tap_instruction <= {3'd0, _zz_10_}; + end + if(jtag_readArea_instructionHit)begin + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_CAPTURE))begin + jtag_readArea_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(_zz_3_)begin + jtag_readArea_shifter <= ({io_jtag_tdi,jtag_readArea_shifter} >>> 1); + end + end + end + + always @ (negedge io_jtag_tck) begin + jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; + end + + +endmodule + +module SystemDebugger ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input mainClock, + input resetCtrl_mainClockReset +); + wire _zz_2_; + wire [0:0] _zz_3_; + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire [66:0] _zz_1_; + + assign _zz_2_ = (dispatcher_headerLoaded == 1'b0); + assign _zz_3_ = _zz_1_[64 : 64]; + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_1_ = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_1_[31 : 0]; + assign io_mem_cmd_payload_data = _zz_1_[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_3_[0]; + assign io_mem_cmd_payload_size = _zz_1_[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= (3'b000); + end else begin + if(io_remote_cmd_valid)begin + if(_zz_2_)begin + dispatcher_counter <= (dispatcher_counter + (3'b001)); + if((dispatcher_counter == (3'b111)))begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last)begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= (3'b000); + end + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @ (posedge mainClock) begin + if(io_remote_cmd_valid)begin + if(_zz_2_)begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module PipelinedMemoryBusToApbBridge ( + input io_pipelinedMemoryBus_cmd_valid, + output io_pipelinedMemoryBus_cmd_ready, + input io_pipelinedMemoryBus_cmd_payload_write, + input [31:0] io_pipelinedMemoryBus_cmd_payload_address, + input [31:0] io_pipelinedMemoryBus_cmd_payload_data, + input [3:0] io_pipelinedMemoryBus_cmd_payload_mask, + output io_pipelinedMemoryBus_rsp_valid, + output [31:0] io_pipelinedMemoryBus_rsp_payload_data, + output [19:0] io_apb_PADDR, + output [0:0] io_apb_PSEL, + output io_apb_PENABLE, + input io_apb_PREADY, + output io_apb_PWRITE, + output [31:0] io_apb_PWDATA, + input [31:0] io_apb_PRDATA, + input io_apb_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_1_; + wire pipelinedMemoryBusStage_cmd_valid; + reg pipelinedMemoryBusStage_cmd_ready; + wire pipelinedMemoryBusStage_cmd_payload_write; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_address; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_data; + wire [3:0] pipelinedMemoryBusStage_cmd_payload_mask; + reg pipelinedMemoryBusStage_rsp_valid; + wire [31:0] pipelinedMemoryBusStage_rsp_payload_data; + reg pipelinedMemoryBusStage_rsp_regNext_valid; + reg [31:0] pipelinedMemoryBusStage_rsp_regNext_payload_data; + reg state; + + assign _zz_1_ = (! state); + assign pipelinedMemoryBusStage_cmd_valid = io_pipelinedMemoryBus_cmd_valid; + assign io_pipelinedMemoryBus_cmd_ready = pipelinedMemoryBusStage_cmd_ready; + assign pipelinedMemoryBusStage_cmd_payload_write = io_pipelinedMemoryBus_cmd_payload_write; + assign pipelinedMemoryBusStage_cmd_payload_address = io_pipelinedMemoryBus_cmd_payload_address; + assign pipelinedMemoryBusStage_cmd_payload_data = io_pipelinedMemoryBus_cmd_payload_data; + assign pipelinedMemoryBusStage_cmd_payload_mask = io_pipelinedMemoryBus_cmd_payload_mask; + assign io_pipelinedMemoryBus_rsp_valid = pipelinedMemoryBusStage_rsp_regNext_valid; + assign io_pipelinedMemoryBus_rsp_payload_data = pipelinedMemoryBusStage_rsp_regNext_payload_data; + always @ (*) begin + pipelinedMemoryBusStage_cmd_ready = 1'b0; + if(! _zz_1_) begin + if(io_apb_PREADY)begin + pipelinedMemoryBusStage_cmd_ready = 1'b1; + end + end + end + + assign io_apb_PSEL[0] = pipelinedMemoryBusStage_cmd_valid; + assign io_apb_PENABLE = state; + assign io_apb_PWRITE = pipelinedMemoryBusStage_cmd_payload_write; + assign io_apb_PADDR = pipelinedMemoryBusStage_cmd_payload_address[19:0]; + assign io_apb_PWDATA = pipelinedMemoryBusStage_cmd_payload_data; + always @ (*) begin + pipelinedMemoryBusStage_rsp_valid = 1'b0; + if(! _zz_1_) begin + if(io_apb_PREADY)begin + pipelinedMemoryBusStage_rsp_valid = (! pipelinedMemoryBusStage_cmd_payload_write); + end + end + end + + assign pipelinedMemoryBusStage_rsp_payload_data = io_apb_PRDATA; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + pipelinedMemoryBusStage_rsp_regNext_valid <= 1'b0; + state <= 1'b0; + end else begin + pipelinedMemoryBusStage_rsp_regNext_valid <= pipelinedMemoryBusStage_rsp_valid; + if(_zz_1_)begin + state <= pipelinedMemoryBusStage_cmd_valid; + end else begin + if(io_apb_PREADY)begin + state <= 1'b0; + end + end + end + end + + always @ (posedge mainClock) begin + pipelinedMemoryBusStage_rsp_regNext_payload_data <= pipelinedMemoryBusStage_rsp_payload_data; + end + + +endmodule + +module Apb3UartCtrl ( + input [4:0] io_apb_PADDR, + input [0:0] io_apb_PSEL, + input io_apb_PENABLE, + output io_apb_PREADY, + input io_apb_PWRITE, + input [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_7_; + reg _zz_8_; + wire _zz_9_; + wire uartCtrl_1__io_write_ready; + wire uartCtrl_1__io_read_valid; + wire [7:0] uartCtrl_1__io_read_payload; + wire uartCtrl_1__io_uart_txd; + wire uartCtrl_1__io_readError; + wire uartCtrl_1__io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1__io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload; + wire [4:0] uartCtrl_1__io_read_queueWithOccupancy_io_occupancy; + wire [4:0] uartCtrl_1__io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_10_; + wire [0:0] _zz_11_; + wire [0:0] _zz_12_; + wire [0:0] _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [0:0] _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [0:0] _zz_20_; + wire [0:0] _zz_21_; + wire [4:0] _zz_22_; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire [2:0] bridge_uartConfigReg_frame_dataLength; + wire `UartStopType_defaultEncoding_type bridge_uartConfigReg_frame_stop; + wire `UartParityType_defaultEncoding_type bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_1_; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg _zz_2_; + reg bridge_misc_readOverflowError; + reg _zz_3_; + reg bridge_misc_breakDetected; + reg uartCtrl_1__io_readBreak_regNext; + reg _zz_4_; + reg bridge_misc_doBreak; + reg _zz_5_; + reg _zz_6_; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + `endif + + function [19:0] zz_bridge_uartConfigReg_clockDivider(input dummy); + begin + zz_bridge_uartConfigReg_clockDivider = 20'h0; + zz_bridge_uartConfigReg_clockDivider = 20'h0002a; + end + endfunction + wire [19:0] _zz_23_; + + assign _zz_10_ = io_apb_PWDATA[0 : 0]; + assign _zz_11_ = (1'b0); + assign _zz_12_ = io_apb_PWDATA[1 : 1]; + assign _zz_13_ = (1'b0); + assign _zz_14_ = io_apb_PWDATA[9 : 9]; + assign _zz_15_ = (1'b0); + assign _zz_16_ = io_apb_PWDATA[10 : 10]; + assign _zz_17_ = (1'b1); + assign _zz_18_ = io_apb_PWDATA[11 : 11]; + assign _zz_19_ = (1'b0); + assign _zz_20_ = io_apb_PWDATA[0 : 0]; + assign _zz_21_ = io_apb_PWDATA[1 : 1]; + assign _zz_22_ = (5'h10 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + UartCtrl uartCtrl_1_ ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1__io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //i + .io_read_valid (uartCtrl_1__io_read_valid ), //o + .io_read_ready (uartCtrl_1__io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1__io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1__io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1__io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1__io_readBreak ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1__io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (_zz_7_ ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[4:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifo uartCtrl_1__io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1__io_read_valid ), //i + .io_push_ready (uartCtrl_1__io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1__io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (_zz_8_ ), //i + .io_pop_payload (uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (_zz_9_ ), //i + .io_occupancy (uartCtrl_1__io_read_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (uartCtrl_1__io_read_queueWithOccupancy_io_availability[4:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + `UartStopType_defaultEncoding_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + `UartStopType_defaultEncoding_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + `UartParityType_defaultEncoding_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + `UartParityType_defaultEncoding_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + `UartParityType_defaultEncoding_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1__io_uart_txd; + assign io_apb_PREADY = 1'b1; + always @ (*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 5'b00000 : begin + io_apb_PRDATA[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + io_apb_PRDATA[7 : 0] = bridge_read_streamBreaked_payload; + end + 5'b00100 : begin + io_apb_PRDATA[20 : 16] = _zz_22_; + io_apb_PRDATA[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + io_apb_PRDATA[28 : 24] = uartCtrl_1__io_read_queueWithOccupancy_io_occupancy; + io_apb_PRDATA[0 : 0] = bridge_interruptCtrl_writeIntEnable; + io_apb_PRDATA[1 : 1] = bridge_interruptCtrl_readIntEnable; + io_apb_PRDATA[8 : 8] = bridge_interruptCtrl_writeInt; + io_apb_PRDATA[9 : 9] = bridge_interruptCtrl_readInt; + end + 5'b10000 : begin + io_apb_PRDATA[0 : 0] = bridge_misc_readError; + io_apb_PRDATA[1 : 1] = bridge_misc_readOverflowError; + io_apb_PRDATA[8 : 8] = uartCtrl_1__io_readBreak; + io_apb_PRDATA[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + assign _zz_23_ = zz_bridge_uartConfigReg_clockDivider(1'b0); + always @ (*) bridge_uartConfigReg_clockDivider = _zz_23_; + assign bridge_uartConfigReg_frame_dataLength = (3'b111); + assign bridge_uartConfigReg_frame_parity = `UartParityType_defaultEncoding_NONE; + assign bridge_uartConfigReg_frame_stop = `UartStopType_defaultEncoding_ONE; + always @ (*) begin + _zz_1_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + if(busCtrl_doWrite)begin + _zz_1_ = 1'b1; + end + end + 5'b00100 : begin + end + 5'b10000 : begin + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_1_; + assign bridge_write_streamUnbuffered_payload = io_apb_PWDATA[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @ (*) begin + bridge_read_streamBreaked_valid = uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1__io_readBreak)begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @ (*) begin + _zz_8_ = bridge_read_streamBreaked_ready; + if(uartCtrl_1__io_readBreak)begin + _zz_8_ = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload; + always @ (*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + if(busCtrl_doRead)begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + 5'b00100 : begin + end + 5'b10000 : begin + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @ (*) begin + _zz_2_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_2_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_3_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_3_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_4_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_4_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_5_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_5_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_6_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_6_ = 1'b1; + end + end + default : begin + end + endcase + end + + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_7_ = 1'b0; + assign _zz_9_ = 1'b0; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_2_)begin + if(_zz_10_[0])begin + bridge_misc_readError <= _zz_11_[0]; + end + end + if(uartCtrl_1__io_readError)begin + bridge_misc_readError <= 1'b1; + end + if(_zz_3_)begin + if(_zz_12_[0])begin + bridge_misc_readOverflowError <= _zz_13_[0]; + end + end + if((uartCtrl_1__io_read_valid && (! uartCtrl_1__io_read_queueWithOccupancy_io_push_ready)))begin + bridge_misc_readOverflowError <= 1'b1; + end + if((uartCtrl_1__io_readBreak && (! uartCtrl_1__io_readBreak_regNext)))begin + bridge_misc_breakDetected <= 1'b1; + end + if(_zz_4_)begin + if(_zz_14_[0])begin + bridge_misc_breakDetected <= _zz_15_[0]; + end + end + if(_zz_5_)begin + if(_zz_16_[0])begin + bridge_misc_doBreak <= _zz_17_[0]; + end + end + if(_zz_6_)begin + if(_zz_18_[0])begin + bridge_misc_doBreak <= _zz_19_[0]; + end + end + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + if(busCtrl_doWrite)begin + bridge_interruptCtrl_writeIntEnable <= _zz_20_[0]; + bridge_interruptCtrl_readIntEnable <= _zz_21_[0]; + end + end + 5'b10000 : begin + end + default : begin + end + endcase + end + end + + always @ (posedge mainClock) begin + uartCtrl_1__io_readBreak_regNext <= uartCtrl_1__io_readBreak; + end + + +endmodule + +module MuraxApb3Timer ( + input [7:0] io_apb_PADDR, + input [0:0] io_apb_PSEL, + input io_apb_PENABLE, + output io_apb_PREADY, + input io_apb_PWRITE, + input [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output io_apb_PSLVERROR, + output io_interrupt, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_7_; + wire _zz_8_; + wire _zz_9_; + wire _zz_10_; + reg [1:0] _zz_11_; + reg [1:0] _zz_12_; + wire prescaler_1__io_overflow; + wire timerA_io_full; + wire [15:0] timerA_io_value; + wire timerB_io_full; + wire [15:0] timerB_io_value; + wire [1:0] interruptCtrl_1__io_pendings; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + reg [15:0] _zz_1_; + reg _zz_2_; + reg [1:0] timerABridge_ticksEnable; + reg [0:0] timerABridge_clearsEnable; + reg timerABridge_busClearing; + reg [15:0] timerA_io_limit_driver; + reg _zz_3_; + reg _zz_4_; + reg [1:0] timerBBridge_ticksEnable; + reg [0:0] timerBBridge_clearsEnable; + reg timerBBridge_busClearing; + reg [15:0] timerB_io_limit_driver; + reg _zz_5_; + reg _zz_6_; + reg [1:0] interruptCtrl_1__io_masks_driver; + + Prescaler prescaler_1_ ( + .io_clear (_zz_2_ ), //i + .io_limit (_zz_1_[15:0] ), //i + .io_overflow (prescaler_1__io_overflow ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Timer timerA ( + .io_tick (_zz_7_ ), //i + .io_clear (_zz_8_ ), //i + .io_limit (timerA_io_limit_driver[15:0] ), //i + .io_full (timerA_io_full ), //o + .io_value (timerA_io_value[15:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Timer timerB ( + .io_tick (_zz_9_ ), //i + .io_clear (_zz_10_ ), //i + .io_limit (timerB_io_limit_driver[15:0] ), //i + .io_full (timerB_io_full ), //o + .io_value (timerB_io_value[15:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + InterruptCtrl interruptCtrl_1_ ( + .io_inputs (_zz_11_[1:0] ), //i + .io_clears (_zz_12_[1:0] ), //i + .io_masks (interruptCtrl_1__io_masks_driver[1:0] ), //i + .io_pendings (interruptCtrl_1__io_pendings[1:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign io_apb_PREADY = 1'b1; + always @ (*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 8'b00000000 : begin + io_apb_PRDATA[15 : 0] = _zz_1_; + end + 8'b01000000 : begin + io_apb_PRDATA[1 : 0] = timerABridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerABridge_clearsEnable; + end + 8'b01000100 : begin + io_apb_PRDATA[15 : 0] = timerA_io_limit_driver; + end + 8'b01001000 : begin + io_apb_PRDATA[15 : 0] = timerA_io_value; + end + 8'b01010000 : begin + io_apb_PRDATA[1 : 0] = timerBBridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerBBridge_clearsEnable; + end + 8'b01010100 : begin + io_apb_PRDATA[15 : 0] = timerB_io_limit_driver; + end + 8'b01011000 : begin + io_apb_PRDATA[15 : 0] = timerB_io_value; + end + 8'b00010000 : begin + io_apb_PRDATA[1 : 0] = interruptCtrl_1__io_pendings; + end + 8'b00010100 : begin + io_apb_PRDATA[1 : 0] = interruptCtrl_1__io_masks_driver; + end + default : begin + end + endcase + end + + assign io_apb_PSLVERROR = 1'b0; + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + always @ (*) begin + _zz_2_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + if(busCtrl_doWrite)begin + _zz_2_ = 1'b1; + end + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + timerABridge_busClearing = 1'b0; + if(_zz_3_)begin + timerABridge_busClearing = 1'b1; + end + if(_zz_4_)begin + timerABridge_busClearing = 1'b1; + end + end + + always @ (*) begin + _zz_3_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + if(busCtrl_doWrite)begin + _zz_3_ = 1'b1; + end + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_4_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + if(busCtrl_doWrite)begin + _zz_4_ = 1'b1; + end + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + assign _zz_8_ = (((timerABridge_clearsEnable & timerA_io_full) != (1'b0)) || timerABridge_busClearing); + assign _zz_7_ = ((timerABridge_ticksEnable & {prescaler_1__io_overflow,1'b1}) != (2'b00)); + always @ (*) begin + timerBBridge_busClearing = 1'b0; + if(_zz_5_)begin + timerBBridge_busClearing = 1'b1; + end + if(_zz_6_)begin + timerBBridge_busClearing = 1'b1; + end + end + + always @ (*) begin + _zz_5_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + if(busCtrl_doWrite)begin + _zz_5_ = 1'b1; + end + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_6_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + if(busCtrl_doWrite)begin + _zz_6_ = 1'b1; + end + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + assign _zz_10_ = (((timerBBridge_clearsEnable & timerB_io_full) != (1'b0)) || timerBBridge_busClearing); + assign _zz_9_ = ((timerBBridge_ticksEnable & {prescaler_1__io_overflow,1'b1}) != (2'b00)); + always @ (*) begin + _zz_12_ = (2'b00); + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + if(busCtrl_doWrite)begin + _zz_12_ = io_apb_PWDATA[1 : 0]; + end + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_11_[0] = timerA_io_full; + _zz_11_[1] = timerB_io_full; + end + + assign io_interrupt = (interruptCtrl_1__io_pendings != (2'b00)); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + timerABridge_ticksEnable <= (2'b00); + timerABridge_clearsEnable <= (1'b0); + timerBBridge_ticksEnable <= (2'b00); + timerBBridge_clearsEnable <= (1'b0); + interruptCtrl_1__io_masks_driver <= (2'b00); + end else begin + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + if(busCtrl_doWrite)begin + timerABridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerABridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + if(busCtrl_doWrite)begin + timerBBridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerBBridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + if(busCtrl_doWrite)begin + interruptCtrl_1__io_masks_driver <= io_apb_PWDATA[1 : 0]; + end + end + default : begin + end + endcase + end + end + + always @ (posedge mainClock) begin + case(io_apb_PADDR) + 8'b00000000 : begin + if(busCtrl_doWrite)begin + _zz_1_ <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01000000 : begin + end + 8'b01000100 : begin + if(busCtrl_doWrite)begin + timerA_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + if(busCtrl_doWrite)begin + timerB_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + +endmodule + +module MyMem ( + input [19:0] io_bus_PADDR, + input [0:0] io_bus_PSEL, + input io_bus_PENABLE, + output io_bus_PREADY, + input io_bus_PWRITE, + input [31:0] io_bus_PWDATA, + output reg [31:0] io_bus_PRDATA, + output io_bus_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] myReg; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + + assign io_bus_PREADY = 1'b1; + always @ (*) begin + io_bus_PRDATA = 32'h0; + case(io_bus_PADDR) + 20'b00110000000000000000 : begin + io_bus_PRDATA[31 : 0] = myReg; + end + default : begin + end + endcase + end + + assign io_bus_PSLVERROR = 1'b0; + assign busCtrl_askWrite = ((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PWRITE); + assign busCtrl_askRead = ((io_bus_PSEL[0] && io_bus_PENABLE) && (! io_bus_PWRITE)); + assign busCtrl_doWrite = (((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PREADY) && io_bus_PWRITE); + assign busCtrl_doRead = (((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PREADY) && (! io_bus_PWRITE)); + always @ (posedge mainClock) begin + case(io_bus_PADDR) + 20'b00110000000000000000 : begin + if(busCtrl_doWrite)begin + myReg <= io_bus_PWDATA[31 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Apb3Decoder ( + input [19:0] io_input_PADDR, + input [0:0] io_input_PSEL, + input io_input_PENABLE, + output reg io_input_PREADY, + input io_input_PWRITE, + input [31:0] io_input_PWDATA, + output [31:0] io_input_PRDATA, + output reg io_input_PSLVERROR, + output [19:0] io_output_PADDR, + output reg [2:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR +); + wire _zz_1_; + + assign _zz_1_ = (io_input_PSEL[0] && (io_output_PSEL == (3'b000))); + assign io_output_PADDR = io_input_PADDR; + assign io_output_PENABLE = io_input_PENABLE; + assign io_output_PWRITE = io_input_PWRITE; + assign io_output_PWDATA = io_input_PWDATA; + always @ (*) begin + io_output_PSEL[0] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h10000) && io_input_PSEL[0]); + io_output_PSEL[1] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h20000) && io_input_PSEL[0]); + io_output_PSEL[2] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h30000) && io_input_PSEL[0]); + end + + always @ (*) begin + io_input_PREADY = io_output_PREADY; + if(_zz_1_)begin + io_input_PREADY = 1'b1; + end + end + + assign io_input_PRDATA = io_output_PRDATA; + always @ (*) begin + io_input_PSLVERROR = io_output_PSLVERROR; + if(_zz_1_)begin + io_input_PSLVERROR = 1'b1; + end + end + + +endmodule + +module Apb3Router ( + input [19:0] io_input_PADDR, + input [2:0] io_input_PSEL, + input io_input_PENABLE, + output io_input_PREADY, + input io_input_PWRITE, + input [31:0] io_input_PWDATA, + output [31:0] io_input_PRDATA, + output io_input_PSLVERROR, + output [19:0] io_outputs_0_PADDR, + output [0:0] io_outputs_0_PSEL, + output io_outputs_0_PENABLE, + input io_outputs_0_PREADY, + output io_outputs_0_PWRITE, + output [31:0] io_outputs_0_PWDATA, + input [31:0] io_outputs_0_PRDATA, + input io_outputs_0_PSLVERROR, + output [19:0] io_outputs_1_PADDR, + output [0:0] io_outputs_1_PSEL, + output io_outputs_1_PENABLE, + input io_outputs_1_PREADY, + output io_outputs_1_PWRITE, + output [31:0] io_outputs_1_PWDATA, + input [31:0] io_outputs_1_PRDATA, + input io_outputs_1_PSLVERROR, + output [19:0] io_outputs_2_PADDR, + output [0:0] io_outputs_2_PSEL, + output io_outputs_2_PENABLE, + input io_outputs_2_PREADY, + output io_outputs_2_PWRITE, + output [31:0] io_outputs_2_PWDATA, + input [31:0] io_outputs_2_PRDATA, + input io_outputs_2_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + reg _zz_3_; + reg [31:0] _zz_4_; + reg _zz_5_; + wire _zz_1_; + wire _zz_2_; + reg [1:0] selIndex; + + always @(*) begin + case(selIndex) + 2'b00 : begin + _zz_3_ = io_outputs_0_PREADY; + _zz_4_ = io_outputs_0_PRDATA; + _zz_5_ = io_outputs_0_PSLVERROR; + end + 2'b01 : begin + _zz_3_ = io_outputs_1_PREADY; + _zz_4_ = io_outputs_1_PRDATA; + _zz_5_ = io_outputs_1_PSLVERROR; + end + default : begin + _zz_3_ = io_outputs_2_PREADY; + _zz_4_ = io_outputs_2_PRDATA; + _zz_5_ = io_outputs_2_PSLVERROR; + end + endcase + end + + assign io_outputs_0_PADDR = io_input_PADDR; + assign io_outputs_0_PENABLE = io_input_PENABLE; + assign io_outputs_0_PSEL[0] = io_input_PSEL[0]; + assign io_outputs_0_PWRITE = io_input_PWRITE; + assign io_outputs_0_PWDATA = io_input_PWDATA; + assign io_outputs_1_PADDR = io_input_PADDR; + assign io_outputs_1_PENABLE = io_input_PENABLE; + assign io_outputs_1_PSEL[0] = io_input_PSEL[1]; + assign io_outputs_1_PWRITE = io_input_PWRITE; + assign io_outputs_1_PWDATA = io_input_PWDATA; + assign io_outputs_2_PADDR = io_input_PADDR; + assign io_outputs_2_PENABLE = io_input_PENABLE; + assign io_outputs_2_PSEL[0] = io_input_PSEL[2]; + assign io_outputs_2_PWRITE = io_input_PWRITE; + assign io_outputs_2_PWDATA = io_input_PWDATA; + assign _zz_1_ = io_input_PSEL[1]; + assign _zz_2_ = io_input_PSEL[2]; + assign io_input_PREADY = _zz_3_; + assign io_input_PRDATA = _zz_4_; + assign io_input_PSLVERROR = _zz_5_; + always @ (posedge mainClock) begin + selIndex <= {_zz_2_,_zz_1_}; + end + + +endmodule + +module PipelinedMemoryBusRamUlx3s ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_write, + input [15:0] io_bus_cmd_payload_address, + input [31:0] io_bus_cmd_payload_data, + input [3:0] io_bus_cmd_payload_mask, + output io_bus_rsp_valid, + output [31:0] io_bus_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_4_; + reg _zz_1_; + wire [13:0] _zz_2_; + wire [31:0] _zz_3_; + reg [7:0] ram_symbol0 [0:16383]; + reg [7:0] ram_symbol1 [0:16383]; + reg [7:0] ram_symbol2 [0:16383]; + reg [7:0] ram_symbol3 [0:16383]; + reg [7:0] _zz_5_; + reg [7:0] _zz_6_; + reg [7:0] _zz_7_; + reg [7:0] _zz_8_; + + always @ (*) begin + _zz_4_ = {_zz_8_, _zz_7_, _zz_6_, _zz_5_}; + end + always @ (posedge mainClock) begin + if(io_bus_cmd_valid) begin + _zz_5_ <= ram_symbol0[_zz_2_]; + _zz_6_ <= ram_symbol1[_zz_2_]; + _zz_7_ <= ram_symbol2[_zz_2_]; + _zz_8_ <= ram_symbol3[_zz_2_]; + end + end + + always @ (posedge mainClock) begin + if(io_bus_cmd_payload_mask[0] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol0[_zz_2_] <= _zz_3_[7 : 0]; + end + if(io_bus_cmd_payload_mask[1] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol1[_zz_2_] <= _zz_3_[15 : 8]; + end + if(io_bus_cmd_payload_mask[2] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol2[_zz_2_] <= _zz_3_[23 : 16]; + end + if(io_bus_cmd_payload_mask[3] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol3[_zz_2_] <= _zz_3_[31 : 24]; + end + end + + assign io_bus_rsp_valid = _zz_1_; + assign _zz_2_ = (io_bus_cmd_payload_address >>> 2); + assign _zz_3_ = io_bus_cmd_payload_data; + assign io_bus_rsp_payload_data = _zz_4_; + assign io_bus_cmd_ready = 1'b1; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_1_ <= 1'b0; + end else begin + _zz_1_ <= ((io_bus_cmd_valid && io_bus_cmd_ready) && (! io_bus_cmd_payload_write)); + end + end + + +endmodule +//PipelinedMemoryBusRamUlx3s_1_ replaced by PipelinedMemoryBusRamUlx3s + +module PipelinedMemoryBusDecoder ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_write, + input [31:0] io_input_cmd_payload_address, + input [31:0] io_input_cmd_payload_data, + input [3:0] io_input_cmd_payload_mask, + output io_input_rsp_valid, + output [31:0] io_input_rsp_payload_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_write, + output [31:0] io_outputs_0_cmd_payload_address, + output [31:0] io_outputs_0_cmd_payload_data, + output [3:0] io_outputs_0_cmd_payload_mask, + input io_outputs_0_rsp_valid, + input [31:0] io_outputs_0_rsp_payload_data, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_write, + output [31:0] io_outputs_1_cmd_payload_address, + output [31:0] io_outputs_1_cmd_payload_data, + output [3:0] io_outputs_1_cmd_payload_mask, + input io_outputs_1_rsp_valid, + input [31:0] io_outputs_1_rsp_payload_data, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_write, + output [31:0] io_outputs_2_cmd_payload_address, + output [31:0] io_outputs_2_cmd_payload_data, + output [3:0] io_outputs_2_cmd_payload_mask, + input io_outputs_2_rsp_valid, + input [31:0] io_outputs_2_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_4_; + wire [1:0] _zz_5_; + wire [0:0] _zz_6_; + wire [1:0] _zz_7_; + wire [0:0] _zz_8_; + wire [1:0] _zz_9_; + wire [1:0] _zz_10_; + wire logic_hits_0; + wire logic_hits_1; + wire logic_hits_2; + wire _zz_1_; + wire _zz_2_; + wire _zz_3_; + wire logic_noHit; + reg [1:0] logic_rspPendingCounter; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + wire logic_rspPending; + wire logic_rspNoHit; + wire logic_cmdWait; + + assign _zz_5_ = (logic_rspPendingCounter + _zz_7_); + assign _zz_6_ = ((io_input_cmd_valid && io_input_cmd_ready) && (! io_input_cmd_payload_write)); + assign _zz_7_ = {1'd0, _zz_6_}; + assign _zz_8_ = io_input_rsp_valid; + assign _zz_9_ = {1'd0, _zz_8_}; + assign _zz_10_ = {logic_rspHits_2,logic_rspHits_1}; + always @(*) begin + case(_zz_10_) + 2'b00 : begin + _zz_4_ = io_outputs_0_rsp_payload_data; + end + 2'b01 : begin + _zz_4_ = io_outputs_1_rsp_payload_data; + end + default : begin + _zz_4_ = io_outputs_2_rsp_payload_data; + end + endcase + end + + assign logic_hits_0 = ((io_input_cmd_payload_address & (~ 32'h000fffff)) == 32'hf0000000); + always @ (*) begin + io_outputs_0_cmd_valid = (io_input_cmd_valid && logic_hits_0); + if(logic_cmdWait)begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_1_ = io_input_cmd_payload_write; + assign io_outputs_0_cmd_payload_write = _zz_1_; + assign io_outputs_0_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_0_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_0_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_1 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80000000); + always @ (*) begin + io_outputs_1_cmd_valid = (io_input_cmd_valid && logic_hits_1); + if(logic_cmdWait)begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_2_ = io_input_cmd_payload_write; + assign io_outputs_1_cmd_payload_write = _zz_2_; + assign io_outputs_1_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_1_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_1_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_2 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80010000); + always @ (*) begin + io_outputs_2_cmd_valid = (io_input_cmd_valid && logic_hits_2); + if(logic_cmdWait)begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_3_ = io_input_cmd_payload_write; + assign io_outputs_2_cmd_payload_write = _zz_3_; + assign io_outputs_2_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_2_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_2_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_noHit = (! ({logic_hits_2,{logic_hits_1,logic_hits_0}} != (3'b000))); + always @ (*) begin + io_input_cmd_ready = (({(logic_hits_2 && io_outputs_2_cmd_ready),{(logic_hits_1 && io_outputs_1_cmd_ready),(logic_hits_0 && io_outputs_0_cmd_ready)}} != (3'b000)) || logic_noHit); + if(logic_cmdWait)begin + io_input_cmd_ready = 1'b0; + end + end + + assign logic_rspPending = (logic_rspPendingCounter != (2'b00)); + assign logic_rspNoHit = (! ({logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}} != (3'b000))); + assign io_input_rsp_valid = (({io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}} != (3'b000)) || (logic_rspPending && logic_rspNoHit)); + assign io_input_rsp_payload_data = _zz_4_; + assign logic_cmdWait = (((io_input_cmd_valid && logic_rspPending) && (((logic_hits_0 != logic_rspHits_0) || (logic_hits_1 != logic_rspHits_1)) || (logic_hits_2 != logic_rspHits_2))) || (logic_rspPendingCounter == (2'b11))); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + logic_rspPendingCounter <= (2'b00); + end else begin + logic_rspPendingCounter <= (_zz_5_ - _zz_9_); + end + end + + always @ (posedge mainClock) begin + if((io_input_cmd_valid && io_input_cmd_ready))begin + logic_rspHits_0 <= logic_hits_0; + logic_rspHits_1 <= logic_hits_1; + logic_rspHits_2 <= logic_hits_2; + end + end + + +endmodule + +module PipelinedMemoryBusDecoder_1_ ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_write, + input [31:0] io_input_cmd_payload_address, + input [31:0] io_input_cmd_payload_data, + input [3:0] io_input_cmd_payload_mask, + output io_input_rsp_valid, + output [31:0] io_input_rsp_payload_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_write, + output [31:0] io_outputs_0_cmd_payload_address, + output [31:0] io_outputs_0_cmd_payload_data, + output [3:0] io_outputs_0_cmd_payload_mask, + input io_outputs_0_rsp_valid, + input [31:0] io_outputs_0_rsp_payload_data, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_write, + output [31:0] io_outputs_1_cmd_payload_address, + output [31:0] io_outputs_1_cmd_payload_data, + output [3:0] io_outputs_1_cmd_payload_mask, + input io_outputs_1_rsp_valid, + input [31:0] io_outputs_1_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_3_; + wire [1:0] _zz_4_; + wire [0:0] _zz_5_; + wire [1:0] _zz_6_; + wire [0:0] _zz_7_; + wire [1:0] _zz_8_; + wire [0:0] _zz_9_; + wire logic_hits_0; + wire logic_hits_1; + wire _zz_1_; + wire _zz_2_; + wire logic_noHit; + reg [1:0] logic_rspPendingCounter; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHit; + wire logic_cmdWait; + + assign _zz_4_ = (logic_rspPendingCounter + _zz_6_); + assign _zz_5_ = ((io_input_cmd_valid && io_input_cmd_ready) && (! io_input_cmd_payload_write)); + assign _zz_6_ = {1'd0, _zz_5_}; + assign _zz_7_ = io_input_rsp_valid; + assign _zz_8_ = {1'd0, _zz_7_}; + assign _zz_9_ = logic_rspHits_1; + always @(*) begin + case(_zz_9_) + 1'b0 : begin + _zz_3_ = io_outputs_0_rsp_payload_data; + end + default : begin + _zz_3_ = io_outputs_1_rsp_payload_data; + end + endcase + end + + assign logic_hits_0 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80000000); + always @ (*) begin + io_outputs_0_cmd_valid = (io_input_cmd_valid && logic_hits_0); + if(logic_cmdWait)begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_1_ = io_input_cmd_payload_write; + assign io_outputs_0_cmd_payload_write = _zz_1_; + assign io_outputs_0_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_0_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_0_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_1 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80010000); + always @ (*) begin + io_outputs_1_cmd_valid = (io_input_cmd_valid && logic_hits_1); + if(logic_cmdWait)begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_2_ = io_input_cmd_payload_write; + assign io_outputs_1_cmd_payload_write = _zz_2_; + assign io_outputs_1_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_1_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_1_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_noHit = (! ({logic_hits_1,logic_hits_0} != (2'b00))); + always @ (*) begin + io_input_cmd_ready = (({(logic_hits_1 && io_outputs_1_cmd_ready),(logic_hits_0 && io_outputs_0_cmd_ready)} != (2'b00)) || logic_noHit); + if(logic_cmdWait)begin + io_input_cmd_ready = 1'b0; + end + end + + assign logic_rspPending = (logic_rspPendingCounter != (2'b00)); + assign logic_rspNoHit = (! ({logic_rspHits_1,logic_rspHits_0} != (2'b00))); + assign io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != (2'b00)) || (logic_rspPending && logic_rspNoHit)); + assign io_input_rsp_payload_data = _zz_3_; + assign logic_cmdWait = (((io_input_cmd_valid && logic_rspPending) && ((logic_hits_0 != logic_rspHits_0) || (logic_hits_1 != logic_rspHits_1))) || (logic_rspPendingCounter == (2'b11))); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + logic_rspPendingCounter <= (2'b00); + end else begin + logic_rspPendingCounter <= (_zz_4_ - _zz_8_); + end + end + + always @ (posedge mainClock) begin + if((io_input_cmd_valid && io_input_cmd_ready))begin + logic_rspHits_0 <= logic_hits_0; + logic_rspHits_1 <= logic_hits_1; + end + end + + +endmodule + +module PipelinedMemoryBusArbiter ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_write, + input [31:0] io_inputs_0_cmd_payload_address, + input [31:0] io_inputs_0_cmd_payload_data, + input [3:0] io_inputs_0_cmd_payload_mask, + output io_inputs_0_rsp_valid, + output [31:0] io_inputs_0_rsp_payload_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_write, + output [31:0] io_output_cmd_payload_address, + output [31:0] io_output_cmd_payload_data, + output [3:0] io_output_cmd_payload_mask, + input io_output_rsp_valid, + input [31:0] io_output_rsp_payload_data +); + + assign io_output_cmd_valid = io_inputs_0_cmd_valid; + assign io_output_cmd_payload_write = io_inputs_0_cmd_payload_write; + assign io_output_cmd_payload_address = io_inputs_0_cmd_payload_address; + assign io_output_cmd_payload_data = io_inputs_0_cmd_payload_data; + assign io_output_cmd_payload_mask = io_inputs_0_cmd_payload_mask; + assign io_inputs_0_cmd_ready = io_output_cmd_ready; + assign io_inputs_0_rsp_valid = io_output_rsp_valid; + assign io_inputs_0_rsp_payload_data = io_output_rsp_payload_data; + +endmodule + +module PipelinedMemoryBusArbiter_1_ ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_write, + input [15:0] io_inputs_0_cmd_payload_address, + input [31:0] io_inputs_0_cmd_payload_data, + input [3:0] io_inputs_0_cmd_payload_mask, + output io_inputs_0_rsp_valid, + output [31:0] io_inputs_0_rsp_payload_data, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_write, + input [15:0] io_inputs_1_cmd_payload_address, + input [31:0] io_inputs_1_cmd_payload_data, + input [3:0] io_inputs_1_cmd_payload_mask, + output io_inputs_1_rsp_valid, + output [31:0] io_inputs_1_rsp_payload_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_write, + output [15:0] io_output_cmd_payload_address, + output [31:0] io_output_cmd_payload_data, + output [3:0] io_output_cmd_payload_mask, + input io_output_rsp_valid, + input [31:0] io_output_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_1_; + wire logic_arbiter_io_inputs_0_ready; + wire logic_arbiter_io_inputs_1_ready; + wire logic_arbiter_io_output_valid; + wire logic_arbiter_io_output_payload_write; + wire [15:0] logic_arbiter_io_output_payload_address; + wire [31:0] logic_arbiter_io_output_payload_data; + wire [3:0] logic_arbiter_io_output_payload_mask; + wire [0:0] logic_arbiter_io_chosen; + wire [1:0] logic_arbiter_io_chosenOH; + wire streamFork_2__io_input_ready; + wire streamFork_2__io_outputs_0_valid; + wire streamFork_2__io_outputs_0_payload_write; + wire [15:0] streamFork_2__io_outputs_0_payload_address; + wire [31:0] streamFork_2__io_outputs_0_payload_data; + wire [3:0] streamFork_2__io_outputs_0_payload_mask; + wire streamFork_2__io_outputs_1_valid; + wire streamFork_2__io_outputs_1_payload_write; + wire [15:0] streamFork_2__io_outputs_1_payload_address; + wire [31:0] streamFork_2__io_outputs_1_payload_data; + wire [3:0] streamFork_2__io_outputs_1_payload_mask; + wire streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready; + wire streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_valid; + wire [1:0] streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload; + wire [2:0] streamFork_2__io_outputs_1_translated_thrown_fifo_io_occupancy; + wire [1:0] logic_rspRouteOh; + wire streamFork_2__io_outputs_1_translated_valid; + reg streamFork_2__io_outputs_1_translated_ready; + wire [1:0] streamFork_2__io_outputs_1_translated_payload; + reg streamFork_2__io_outputs_1_translated_thrown_valid; + wire streamFork_2__io_outputs_1_translated_thrown_ready; + wire [1:0] streamFork_2__io_outputs_1_translated_thrown_payload; + + StreamArbiter logic_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (logic_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_write (io_inputs_0_cmd_payload_write ), //i + .io_inputs_0_payload_address (io_inputs_0_cmd_payload_address[15:0] ), //i + .io_inputs_0_payload_data (io_inputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_0_payload_mask (io_inputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (logic_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_write (io_inputs_1_cmd_payload_write ), //i + .io_inputs_1_payload_address (io_inputs_1_cmd_payload_address[15:0] ), //i + .io_inputs_1_payload_data (io_inputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_1_payload_mask (io_inputs_1_cmd_payload_mask[3:0] ), //i + .io_output_valid (logic_arbiter_io_output_valid ), //o + .io_output_ready (streamFork_2__io_input_ready ), //i + .io_output_payload_write (logic_arbiter_io_output_payload_write ), //o + .io_output_payload_address (logic_arbiter_io_output_payload_address[15:0] ), //o + .io_output_payload_data (logic_arbiter_io_output_payload_data[31:0] ), //o + .io_output_payload_mask (logic_arbiter_io_output_payload_mask[3:0] ), //o + .io_chosen (logic_arbiter_io_chosen ), //o + .io_chosenOH (logic_arbiter_io_chosenOH[1:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFork streamFork_2_ ( + .io_input_valid (logic_arbiter_io_output_valid ), //i + .io_input_ready (streamFork_2__io_input_ready ), //o + .io_input_payload_write (logic_arbiter_io_output_payload_write ), //i + .io_input_payload_address (logic_arbiter_io_output_payload_address[15:0] ), //i + .io_input_payload_data (logic_arbiter_io_output_payload_data[31:0] ), //i + .io_input_payload_mask (logic_arbiter_io_output_payload_mask[3:0] ), //i + .io_outputs_0_valid (streamFork_2__io_outputs_0_valid ), //o + .io_outputs_0_ready (io_output_cmd_ready ), //i + .io_outputs_0_payload_write (streamFork_2__io_outputs_0_payload_write ), //o + .io_outputs_0_payload_address (streamFork_2__io_outputs_0_payload_address[15:0] ), //o + .io_outputs_0_payload_data (streamFork_2__io_outputs_0_payload_data[31:0] ), //o + .io_outputs_0_payload_mask (streamFork_2__io_outputs_0_payload_mask[3:0] ), //o + .io_outputs_1_valid (streamFork_2__io_outputs_1_valid ), //o + .io_outputs_1_ready (streamFork_2__io_outputs_1_translated_ready ), //i + .io_outputs_1_payload_write (streamFork_2__io_outputs_1_payload_write ), //o + .io_outputs_1_payload_address (streamFork_2__io_outputs_1_payload_address[15:0] ), //o + .io_outputs_1_payload_data (streamFork_2__io_outputs_1_payload_data[31:0] ), //o + .io_outputs_1_payload_mask (streamFork_2__io_outputs_1_payload_mask[3:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifoLowLatency_1_ streamFork_2__io_outputs_1_translated_thrown_fifo ( + .io_push_valid (streamFork_2__io_outputs_1_translated_thrown_valid ), //i + .io_push_ready (streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready ), //o + .io_push_payload (streamFork_2__io_outputs_1_translated_thrown_payload[1:0] ), //i + .io_pop_valid (streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_valid ), //o + .io_pop_ready (io_output_rsp_valid ), //i + .io_pop_payload (streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload[1:0] ), //o + .io_flush (_zz_1_ ), //i + .io_occupancy (streamFork_2__io_outputs_1_translated_thrown_fifo_io_occupancy[2:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign io_inputs_0_cmd_ready = logic_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = logic_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = streamFork_2__io_outputs_0_valid; + assign io_output_cmd_payload_write = streamFork_2__io_outputs_0_payload_write; + assign io_output_cmd_payload_address = streamFork_2__io_outputs_0_payload_address; + assign io_output_cmd_payload_data = streamFork_2__io_outputs_0_payload_data; + assign io_output_cmd_payload_mask = streamFork_2__io_outputs_0_payload_mask; + assign streamFork_2__io_outputs_1_translated_valid = streamFork_2__io_outputs_1_valid; + assign streamFork_2__io_outputs_1_translated_payload = logic_arbiter_io_chosenOH; + always @ (*) begin + streamFork_2__io_outputs_1_translated_thrown_valid = streamFork_2__io_outputs_1_translated_valid; + if(streamFork_2__io_outputs_1_payload_write)begin + streamFork_2__io_outputs_1_translated_thrown_valid = 1'b0; + end + end + + always @ (*) begin + streamFork_2__io_outputs_1_translated_ready = streamFork_2__io_outputs_1_translated_thrown_ready; + if(streamFork_2__io_outputs_1_payload_write)begin + streamFork_2__io_outputs_1_translated_ready = 1'b1; + end + end + + assign streamFork_2__io_outputs_1_translated_thrown_payload = streamFork_2__io_outputs_1_translated_payload; + assign streamFork_2__io_outputs_1_translated_thrown_ready = streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready; + assign logic_rspRouteOh = streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && logic_rspRouteOh[0]); + assign io_inputs_0_rsp_payload_data = io_output_rsp_payload_data; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && logic_rspRouteOh[1]); + assign io_inputs_1_rsp_payload_data = io_output_rsp_payload_data; + assign _zz_1_ = 1'b0; + +endmodule +//PipelinedMemoryBusArbiter_2_ replaced by PipelinedMemoryBusArbiter_1_ + +module PQVexRiscvUlx3s ( + input io_asyncReset, + input io_mainClock, + output io_uart_txd, + input io_uart_rxd, + input io_jtag_tms, + input io_jtag_tdi, + output io_jtag_tdo, + input io_jtag_tck +); + wire _zz_36_; + wire _zz_37_; + wire [7:0] _zz_38_; + wire _zz_39_; + wire [4:0] _zz_40_; + wire [7:0] _zz_41_; + wire _zz_42_; + wire [15:0] _zz_43_; + wire [15:0] _zz_44_; + wire [15:0] _zz_45_; + wire [15:0] _zz_46_; + wire asyncReset_buffercc_io_dataOut; + wire core_cpu_iBus_cmd_valid; + wire [31:0] core_cpu_iBus_cmd_payload_pc; + wire core_cpu_debug_bus_cmd_ready; + wire [31:0] core_cpu_debug_bus_rsp_data; + wire core_cpu_debug_resetOut; + wire core_cpu_dBus_cmd_valid; + wire core_cpu_dBus_cmd_payload_wr; + wire [31:0] core_cpu_dBus_cmd_payload_address; + wire [31:0] core_cpu_dBus_cmd_payload_data; + wire [1:0] core_cpu_dBus_cmd_payload_size; + wire jtagBridge_1__io_jtag_tdo; + wire jtagBridge_1__io_remote_cmd_valid; + wire jtagBridge_1__io_remote_cmd_payload_last; + wire [0:0] jtagBridge_1__io_remote_cmd_payload_fragment; + wire jtagBridge_1__io_remote_rsp_ready; + wire systemDebugger_1__io_remote_cmd_ready; + wire systemDebugger_1__io_remote_rsp_valid; + wire systemDebugger_1__io_remote_rsp_payload_error; + wire [31:0] systemDebugger_1__io_remote_rsp_payload_data; + wire systemDebugger_1__io_mem_cmd_valid; + wire [31:0] systemDebugger_1__io_mem_cmd_payload_address; + wire [31:0] systemDebugger_1__io_mem_cmd_payload_data; + wire systemDebugger_1__io_mem_cmd_payload_wr; + wire [1:0] systemDebugger_1__io_mem_cmd_payload_size; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data; + wire [19:0] pipelinedMemoryBusToApbBridge_1__io_apb_PADDR; + wire [0:0] pipelinedMemoryBusToApbBridge_1__io_apb_PSEL; + wire pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE; + wire pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA; + wire apb3UartCtrl_1__io_apb_PREADY; + wire [31:0] apb3UartCtrl_1__io_apb_PRDATA; + wire apb3UartCtrl_1__io_uart_txd; + wire apb3UartCtrl_1__io_interrupt; + wire muraxApb3Timer_1__io_apb_PREADY; + wire [31:0] muraxApb3Timer_1__io_apb_PRDATA; + wire muraxApb3Timer_1__io_apb_PSLVERROR; + wire muraxApb3Timer_1__io_interrupt; + wire myMem_1__io_bus_PREADY; + wire [31:0] myMem_1__io_bus_PRDATA; + wire myMem_1__io_bus_PSLVERROR; + wire io_apb_decoder_io_input_PREADY; + wire [31:0] io_apb_decoder_io_input_PRDATA; + wire io_apb_decoder_io_input_PSLVERROR; + wire [19:0] io_apb_decoder_io_output_PADDR; + wire [2:0] io_apb_decoder_io_output_PSEL; + wire io_apb_decoder_io_output_PENABLE; + wire io_apb_decoder_io_output_PWRITE; + wire [31:0] io_apb_decoder_io_output_PWDATA; + wire apb3Router_1__io_input_PREADY; + wire [31:0] apb3Router_1__io_input_PRDATA; + wire apb3Router_1__io_input_PSLVERROR; + wire [19:0] apb3Router_1__io_outputs_0_PADDR; + wire [0:0] apb3Router_1__io_outputs_0_PSEL; + wire apb3Router_1__io_outputs_0_PENABLE; + wire apb3Router_1__io_outputs_0_PWRITE; + wire [31:0] apb3Router_1__io_outputs_0_PWDATA; + wire [19:0] apb3Router_1__io_outputs_1_PADDR; + wire [0:0] apb3Router_1__io_outputs_1_PSEL; + wire apb3Router_1__io_outputs_1_PENABLE; + wire apb3Router_1__io_outputs_1_PWRITE; + wire [31:0] apb3Router_1__io_outputs_1_PWDATA; + wire [19:0] apb3Router_1__io_outputs_2_PADDR; + wire [0:0] apb3Router_1__io_outputs_2_PSEL; + wire apb3Router_1__io_outputs_2_PENABLE; + wire apb3Router_1__io_outputs_2_PWRITE; + wire [31:0] apb3Router_1__io_outputs_2_PWDATA; + wire memory_ramBlocks_0_io_bus_cmd_ready; + wire memory_ramBlocks_0_io_bus_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_cmd_ready; + wire memory_ramBlocks_1_io_bus_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_rsp_payload_data; + wire core_dbus_decoder_io_input_cmd_ready; + wire core_dbus_decoder_io_input_rsp_valid; + wire [31:0] core_dbus_decoder_io_input_rsp_payload_data; + wire core_dbus_decoder_io_outputs_0_cmd_valid; + wire core_dbus_decoder_io_outputs_0_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_0_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_0_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_0_cmd_payload_mask; + wire core_dbus_decoder_io_outputs_1_cmd_valid; + wire core_dbus_decoder_io_outputs_1_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_1_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_1_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_1_cmd_payload_mask; + wire core_dbus_decoder_io_outputs_2_cmd_valid; + wire core_dbus_decoder_io_outputs_2_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_2_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_2_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_2_cmd_payload_mask; + wire core_ibus_decoder_io_input_cmd_ready; + wire core_ibus_decoder_io_input_rsp_valid; + wire [31:0] core_ibus_decoder_io_input_rsp_payload_data; + wire core_ibus_decoder_io_outputs_0_cmd_valid; + wire core_ibus_decoder_io_outputs_0_cmd_payload_write; + wire [31:0] core_ibus_decoder_io_outputs_0_cmd_payload_address; + wire [31:0] core_ibus_decoder_io_outputs_0_cmd_payload_data; + wire [3:0] core_ibus_decoder_io_outputs_0_cmd_payload_mask; + wire core_ibus_decoder_io_outputs_1_cmd_valid; + wire core_ibus_decoder_io_outputs_1_cmd_payload_write; + wire [31:0] core_ibus_decoder_io_outputs_1_cmd_payload_address; + wire [31:0] core_ibus_decoder_io_outputs_1_cmd_payload_data; + wire [3:0] core_ibus_decoder_io_outputs_1_cmd_payload_mask; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data; + wire [3:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data; + wire memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid; + wire memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write; + wire [15:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data; + wire [3:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid; + wire memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write; + wire [15:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data; + wire [3:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask; + wire _zz_47_; + wire _zz_48_; + wire asyncReset; + wire mainClock; + wire resetCtrl_bufferedReset; + reg resetCtrl_mainClockReset; + reg resetCtrl_systemClockReset; + reg core_timerInterrupt; + reg core_externalInterrupt; + wire core_ibus_cmd_valid; + wire core_ibus_cmd_ready; + wire core_ibus_cmd_payload_write; + wire [31:0] core_ibus_cmd_payload_address; + wire [31:0] core_ibus_cmd_payload_data; + wire [3:0] core_ibus_cmd_payload_mask; + wire core_ibus_rsp_valid; + wire [31:0] core_ibus_rsp_payload_data; + wire core_dbus_cmd_valid; + wire core_dbus_cmd_ready; + wire core_dbus_cmd_payload_write; + wire [31:0] core_dbus_cmd_payload_address; + wire [31:0] core_dbus_cmd_payload_data; + wire [3:0] core_dbus_cmd_payload_mask; + wire core_dbus_rsp_valid; + wire [31:0] core_dbus_rsp_payload_data; + wire _zz_1_; + wire _zz_2_; + wire [31:0] _zz_3_; + wire _zz_4_; + reg _zz_5_; + reg _zz_6_; + reg [31:0] _zz_7_; + reg [31:0] _zz_8_; + reg [3:0] _zz_9_; + wire _zz_10_; + reg _zz_11_; + reg _zz_12_; + reg [31:0] _zz_13_; + reg [31:0] _zz_14_; + reg [3:0] _zz_15_; + wire _zz_16_; + wire _zz_17_; + wire _zz_18_; + wire [31:0] _zz_19_; + wire [31:0] _zz_20_; + wire [3:0] _zz_21_; + reg [3:0] _zz_22_; + wire _zz_23_; + reg _zz_24_; + reg _zz_25_; + reg [31:0] _zz_26_; + reg [31:0] _zz_27_; + reg [3:0] _zz_28_; + wire _zz_29_; + reg _zz_30_; + reg _zz_31_; + reg [31:0] _zz_32_; + reg [31:0] _zz_33_; + reg [3:0] _zz_34_; + reg core_cpu_debug_resetOut_regNext; + reg _zz_35_; + + assign _zz_47_ = (_zz_2_ && (! _zz_4_)); + assign _zz_48_ = (_zz_17_ && (! _zz_23_)); + BufferCC_2_ asyncReset_buffercc ( + .io_dataIn (asyncReset ), //i + .io_dataOut (asyncReset_buffercc_io_dataOut ), //o + .mainClock (mainClock ) //i + ); + VexRiscv core_cpu ( + .iBus_cmd_valid (core_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (_zz_2_ ), //i + .iBus_cmd_payload_pc (core_cpu_iBus_cmd_payload_pc[31:0] ), //o + .iBus_rsp_valid (core_ibus_rsp_valid ), //i + .iBus_rsp_payload_error (_zz_36_ ), //i + .iBus_rsp_payload_inst (core_ibus_rsp_payload_data[31:0] ), //i + .timerInterrupt (core_timerInterrupt ), //i + .externalInterrupt (core_externalInterrupt ), //i + .softwareInterrupt (_zz_37_ ), //i + .debug_bus_cmd_valid (systemDebugger_1__io_mem_cmd_valid ), //i + .debug_bus_cmd_ready (core_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (systemDebugger_1__io_mem_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (_zz_38_[7:0] ), //i + .debug_bus_cmd_payload_data (systemDebugger_1__io_mem_cmd_payload_data[31:0] ), //i + .debug_bus_rsp_data (core_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (core_cpu_debug_resetOut ), //o + .dBus_cmd_valid (core_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (_zz_17_ ), //i + .dBus_cmd_payload_wr (core_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_address (core_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (core_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_size (core_cpu_dBus_cmd_payload_size[1:0] ), //o + .dBus_rsp_ready (core_dbus_rsp_valid ), //i + .dBus_rsp_error (_zz_39_ ), //i + .dBus_rsp_data (core_dbus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + JtagBridge jtagBridge_1_ ( + .io_jtag_tms (io_jtag_tms ), //i + .io_jtag_tdi (io_jtag_tdi ), //i + .io_jtag_tdo (jtagBridge_1__io_jtag_tdo ), //o + .io_jtag_tck (io_jtag_tck ), //i + .io_remote_cmd_valid (jtagBridge_1__io_remote_cmd_valid ), //o + .io_remote_cmd_ready (systemDebugger_1__io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (jtagBridge_1__io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (jtagBridge_1__io_remote_cmd_payload_fragment ), //o + .io_remote_rsp_valid (systemDebugger_1__io_remote_rsp_valid ), //i + .io_remote_rsp_ready (jtagBridge_1__io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (systemDebugger_1__io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (systemDebugger_1__io_remote_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + SystemDebugger systemDebugger_1_ ( + .io_remote_cmd_valid (jtagBridge_1__io_remote_cmd_valid ), //i + .io_remote_cmd_ready (systemDebugger_1__io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (jtagBridge_1__io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (jtagBridge_1__io_remote_cmd_payload_fragment ), //i + .io_remote_rsp_valid (systemDebugger_1__io_remote_rsp_valid ), //o + .io_remote_rsp_ready (jtagBridge_1__io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (systemDebugger_1__io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (systemDebugger_1__io_remote_rsp_payload_data[31:0] ), //o + .io_mem_cmd_valid (systemDebugger_1__io_mem_cmd_valid ), //o + .io_mem_cmd_ready (core_cpu_debug_bus_cmd_ready ), //i + .io_mem_cmd_payload_address (systemDebugger_1__io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (systemDebugger_1__io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (systemDebugger_1__io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (systemDebugger_1__io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (_zz_35_ ), //i + .io_mem_rsp_payload (core_cpu_debug_bus_rsp_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + PipelinedMemoryBusToApbBridge pipelinedMemoryBusToApbBridge_1_ ( + .io_pipelinedMemoryBus_cmd_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid ), //i + .io_pipelinedMemoryBus_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready ), //o + .io_pipelinedMemoryBus_cmd_payload_write (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write ), //i + .io_pipelinedMemoryBus_cmd_payload_address (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address[31:0] ), //i + .io_pipelinedMemoryBus_cmd_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_pipelinedMemoryBus_cmd_payload_mask (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_pipelinedMemoryBus_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid ), //o + .io_pipelinedMemoryBus_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data[31:0] ), //o + .io_apb_PADDR (pipelinedMemoryBusToApbBridge_1__io_apb_PADDR[19:0] ), //o + .io_apb_PSEL (pipelinedMemoryBusToApbBridge_1__io_apb_PSEL ), //o + .io_apb_PENABLE (pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE ), //o + .io_apb_PREADY (io_apb_decoder_io_input_PREADY ), //i + .io_apb_PWRITE (pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE ), //o + .io_apb_PWDATA (pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA[31:0] ), //o + .io_apb_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //i + .io_apb_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Apb3UartCtrl apb3UartCtrl_1_ ( + .io_apb_PADDR (_zz_40_[4:0] ), //i + .io_apb_PSEL (apb3Router_1__io_outputs_0_PSEL ), //i + .io_apb_PENABLE (apb3Router_1__io_outputs_0_PENABLE ), //i + .io_apb_PREADY (apb3UartCtrl_1__io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1__io_outputs_0_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1__io_outputs_0_PWDATA[31:0] ), //i + .io_apb_PRDATA (apb3UartCtrl_1__io_apb_PRDATA[31:0] ), //o + .io_uart_txd (apb3UartCtrl_1__io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_interrupt (apb3UartCtrl_1__io_interrupt ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + MuraxApb3Timer muraxApb3Timer_1_ ( + .io_apb_PADDR (_zz_41_[7:0] ), //i + .io_apb_PSEL (apb3Router_1__io_outputs_1_PSEL ), //i + .io_apb_PENABLE (apb3Router_1__io_outputs_1_PENABLE ), //i + .io_apb_PREADY (muraxApb3Timer_1__io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1__io_outputs_1_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1__io_outputs_1_PWDATA[31:0] ), //i + .io_apb_PRDATA (muraxApb3Timer_1__io_apb_PRDATA[31:0] ), //o + .io_apb_PSLVERROR (muraxApb3Timer_1__io_apb_PSLVERROR ), //o + .io_interrupt (muraxApb3Timer_1__io_interrupt ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + MyMem myMem_1_ ( + .io_bus_PADDR (apb3Router_1__io_outputs_2_PADDR[19:0] ), //i + .io_bus_PSEL (apb3Router_1__io_outputs_2_PSEL ), //i + .io_bus_PENABLE (apb3Router_1__io_outputs_2_PENABLE ), //i + .io_bus_PREADY (myMem_1__io_bus_PREADY ), //o + .io_bus_PWRITE (apb3Router_1__io_outputs_2_PWRITE ), //i + .io_bus_PWDATA (apb3Router_1__io_outputs_2_PWDATA[31:0] ), //i + .io_bus_PRDATA (myMem_1__io_bus_PRDATA[31:0] ), //o + .io_bus_PSLVERROR (myMem_1__io_bus_PSLVERROR ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Apb3Decoder io_apb_decoder ( + .io_input_PADDR (pipelinedMemoryBusToApbBridge_1__io_apb_PADDR[19:0] ), //i + .io_input_PSEL (pipelinedMemoryBusToApbBridge_1__io_apb_PSEL ), //i + .io_input_PENABLE (pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE ), //i + .io_input_PREADY (io_apb_decoder_io_input_PREADY ), //o + .io_input_PWRITE (pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE ), //i + .io_input_PWDATA (pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA[31:0] ), //i + .io_input_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //o + .io_output_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //o + .io_output_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //o + .io_output_PENABLE (io_apb_decoder_io_output_PENABLE ), //o + .io_output_PREADY (apb3Router_1__io_input_PREADY ), //i + .io_output_PWRITE (io_apb_decoder_io_output_PWRITE ), //o + .io_output_PWDATA (io_apb_decoder_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (apb3Router_1__io_input_PRDATA[31:0] ), //i + .io_output_PSLVERROR (apb3Router_1__io_input_PSLVERROR ) //i + ); + Apb3Router apb3Router_1_ ( + .io_input_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //i + .io_input_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //i + .io_input_PENABLE (io_apb_decoder_io_output_PENABLE ), //i + .io_input_PREADY (apb3Router_1__io_input_PREADY ), //o + .io_input_PWRITE (io_apb_decoder_io_output_PWRITE ), //i + .io_input_PWDATA (io_apb_decoder_io_output_PWDATA[31:0] ), //i + .io_input_PRDATA (apb3Router_1__io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (apb3Router_1__io_input_PSLVERROR ), //o + .io_outputs_0_PADDR (apb3Router_1__io_outputs_0_PADDR[19:0] ), //o + .io_outputs_0_PSEL (apb3Router_1__io_outputs_0_PSEL ), //o + .io_outputs_0_PENABLE (apb3Router_1__io_outputs_0_PENABLE ), //o + .io_outputs_0_PREADY (apb3UartCtrl_1__io_apb_PREADY ), //i + .io_outputs_0_PWRITE (apb3Router_1__io_outputs_0_PWRITE ), //o + .io_outputs_0_PWDATA (apb3Router_1__io_outputs_0_PWDATA[31:0] ), //o + .io_outputs_0_PRDATA (apb3UartCtrl_1__io_apb_PRDATA[31:0] ), //i + .io_outputs_0_PSLVERROR (_zz_42_ ), //i + .io_outputs_1_PADDR (apb3Router_1__io_outputs_1_PADDR[19:0] ), //o + .io_outputs_1_PSEL (apb3Router_1__io_outputs_1_PSEL ), //o + .io_outputs_1_PENABLE (apb3Router_1__io_outputs_1_PENABLE ), //o + .io_outputs_1_PREADY (muraxApb3Timer_1__io_apb_PREADY ), //i + .io_outputs_1_PWRITE (apb3Router_1__io_outputs_1_PWRITE ), //o + .io_outputs_1_PWDATA (apb3Router_1__io_outputs_1_PWDATA[31:0] ), //o + .io_outputs_1_PRDATA (muraxApb3Timer_1__io_apb_PRDATA[31:0] ), //i + .io_outputs_1_PSLVERROR (muraxApb3Timer_1__io_apb_PSLVERROR ), //i + .io_outputs_2_PADDR (apb3Router_1__io_outputs_2_PADDR[19:0] ), //o + .io_outputs_2_PSEL (apb3Router_1__io_outputs_2_PSEL ), //o + .io_outputs_2_PENABLE (apb3Router_1__io_outputs_2_PENABLE ), //o + .io_outputs_2_PREADY (myMem_1__io_bus_PREADY ), //i + .io_outputs_2_PWRITE (apb3Router_1__io_outputs_2_PWRITE ), //o + .io_outputs_2_PWDATA (apb3Router_1__io_outputs_2_PWDATA[31:0] ), //o + .io_outputs_2_PRDATA (myMem_1__io_bus_PRDATA[31:0] ), //i + .io_outputs_2_PSLVERROR (myMem_1__io_bus_PSLVERROR ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusRamUlx3s memory_ramBlocks_0 ( + .io_bus_cmd_valid (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid ), //i + .io_bus_cmd_ready (memory_ramBlocks_0_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_write (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write ), //i + .io_bus_cmd_payload_address (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //i + .io_bus_cmd_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_bus_cmd_payload_mask (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_bus_rsp_valid (memory_ramBlocks_0_io_bus_rsp_valid ), //o + .io_bus_rsp_payload_data (memory_ramBlocks_0_io_bus_rsp_payload_data[31:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusRamUlx3s memory_ramBlocks_1 ( + .io_bus_cmd_valid (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid ), //i + .io_bus_cmd_ready (memory_ramBlocks_1_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_write (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write ), //i + .io_bus_cmd_payload_address (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //i + .io_bus_cmd_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_bus_cmd_payload_mask (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_bus_rsp_valid (memory_ramBlocks_1_io_bus_rsp_valid ), //o + .io_bus_rsp_payload_data (memory_ramBlocks_1_io_bus_rsp_payload_data[31:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusDecoder core_dbus_decoder ( + .io_input_cmd_valid (core_dbus_cmd_valid ), //i + .io_input_cmd_ready (core_dbus_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_write (core_dbus_cmd_payload_write ), //i + .io_input_cmd_payload_address (core_dbus_cmd_payload_address[31:0] ), //i + .io_input_cmd_payload_data (core_dbus_cmd_payload_data[31:0] ), //i + .io_input_cmd_payload_mask (core_dbus_cmd_payload_mask[3:0] ), //i + .io_input_rsp_valid (core_dbus_decoder_io_input_rsp_valid ), //o + .io_input_rsp_payload_data (core_dbus_decoder_io_input_rsp_payload_data[31:0] ), //o + .io_outputs_0_cmd_valid (core_dbus_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_0_cmd_payload_write ), //o + .io_outputs_0_cmd_payload_address (core_dbus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //o + .io_outputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //o + .io_outputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //o + .io_outputs_0_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_0_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .io_outputs_1_cmd_valid (core_dbus_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_1_cmd_payload_write (core_dbus_decoder_io_outputs_1_cmd_payload_write ), //o + .io_outputs_1_cmd_payload_address (core_dbus_decoder_io_outputs_1_cmd_payload_address[31:0] ), //o + .io_outputs_1_cmd_payload_data (core_dbus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //o + .io_outputs_1_cmd_payload_mask (core_dbus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //o + .io_outputs_1_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_1_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .io_outputs_2_cmd_valid (core_dbus_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_2_cmd_payload_write (core_dbus_decoder_io_outputs_2_cmd_payload_write ), //o + .io_outputs_2_cmd_payload_address (core_dbus_decoder_io_outputs_2_cmd_payload_address[31:0] ), //o + .io_outputs_2_cmd_payload_data (core_dbus_decoder_io_outputs_2_cmd_payload_data[31:0] ), //o + .io_outputs_2_cmd_payload_mask (core_dbus_decoder_io_outputs_2_cmd_payload_mask[3:0] ), //o + .io_outputs_2_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_2_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusDecoder_1_ core_ibus_decoder ( + .io_input_cmd_valid (core_ibus_cmd_valid ), //i + .io_input_cmd_ready (core_ibus_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_write (core_ibus_cmd_payload_write ), //i + .io_input_cmd_payload_address (core_ibus_cmd_payload_address[31:0] ), //i + .io_input_cmd_payload_data (core_ibus_cmd_payload_data[31:0] ), //i + .io_input_cmd_payload_mask (core_ibus_cmd_payload_mask[3:0] ), //i + .io_input_rsp_valid (core_ibus_decoder_io_input_rsp_valid ), //o + .io_input_rsp_payload_data (core_ibus_decoder_io_input_rsp_payload_data[31:0] ), //o + .io_outputs_0_cmd_valid (core_ibus_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_write (core_ibus_decoder_io_outputs_0_cmd_payload_write ), //o + .io_outputs_0_cmd_payload_address (core_ibus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //o + .io_outputs_0_cmd_payload_data (core_ibus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //o + .io_outputs_0_cmd_payload_mask (core_ibus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //o + .io_outputs_0_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //i + .io_outputs_1_cmd_valid (core_ibus_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_1_cmd_payload_write ), //o + .io_outputs_1_cmd_payload_address (core_ibus_decoder_io_outputs_1_cmd_payload_address[31:0] ), //o + .io_outputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //o + .io_outputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //o + .io_outputs_1_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_1_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusArbiter pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_0_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_0_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (core_dbus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready ), //i + .io_output_cmd_payload_write (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address[31:0] ), //o + .io_output_cmd_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid ), //i + .io_output_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data[31:0] ) //i + ); + PipelinedMemoryBusArbiter_1_ memory_ramBlocks_0_io_bus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_1_cmd_valid ), //i + .io_inputs_0_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_1_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (_zz_43_[15:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_inputs_1_cmd_valid (core_ibus_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_0_cmd_payload_write ), //i + .io_inputs_1_cmd_payload_address (_zz_44_[15:0] ), //i + .io_inputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_1_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (memory_ramBlocks_0_io_bus_cmd_ready ), //i + .io_output_cmd_payload_write (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //o + .io_output_cmd_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (memory_ramBlocks_0_io_bus_rsp_valid ), //i + .io_output_rsp_payload_data (memory_ramBlocks_0_io_bus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusArbiter_1_ memory_ramBlocks_1_io_bus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_2_cmd_valid ), //i + .io_inputs_0_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_2_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (_zz_45_[15:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_2_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_2_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_inputs_1_cmd_valid (core_ibus_decoder_io_outputs_1_cmd_valid ), //i + .io_inputs_1_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_1_cmd_payload_write ), //i + .io_inputs_1_cmd_payload_address (_zz_46_[15:0] ), //i + .io_inputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //i + .io_inputs_1_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (memory_ramBlocks_1_io_bus_cmd_ready ), //i + .io_output_cmd_payload_write (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //o + .io_output_cmd_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (memory_ramBlocks_1_io_bus_rsp_valid ), //i + .io_output_rsp_payload_data (memory_ramBlocks_1_io_bus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign resetCtrl_bufferedReset = asyncReset_buffercc_io_dataOut; + always @ (*) begin + core_timerInterrupt = 1'b0; + if(muraxApb3Timer_1__io_interrupt)begin + core_timerInterrupt = 1'b1; + end + end + + always @ (*) begin + core_externalInterrupt = 1'b0; + if(apb3UartCtrl_1__io_interrupt)begin + core_externalInterrupt = 1'b1; + end + end + + assign _zz_1_ = core_cpu_iBus_cmd_valid; + assign _zz_3_ = core_cpu_iBus_cmd_payload_pc; + assign _zz_36_ = 1'b0; + assign _zz_2_ = (! _zz_5_); + assign _zz_4_ = ((1'b1 && (! _zz_10_)) || core_ibus_cmd_ready); + assign _zz_10_ = _zz_11_; + assign core_ibus_cmd_valid = _zz_10_; + assign core_ibus_cmd_payload_write = _zz_12_; + assign core_ibus_cmd_payload_address = _zz_13_; + assign core_ibus_cmd_payload_data = _zz_14_; + assign core_ibus_cmd_payload_mask = _zz_15_; + assign _zz_16_ = core_cpu_dBus_cmd_valid; + assign _zz_18_ = core_cpu_dBus_cmd_payload_wr; + assign _zz_19_ = core_cpu_dBus_cmd_payload_address; + assign _zz_20_ = core_cpu_dBus_cmd_payload_data; + always @ (*) begin + case(core_cpu_dBus_cmd_payload_size) + 2'b00 : begin + _zz_22_ = (4'b0001); + end + 2'b01 : begin + _zz_22_ = (4'b0011); + end + default : begin + _zz_22_ = (4'b1111); + end + endcase + end + + assign _zz_21_ = (_zz_22_ <<< core_cpu_dBus_cmd_payload_address[1 : 0]); + assign _zz_17_ = (! _zz_24_); + assign _zz_23_ = ((1'b1 && (! _zz_29_)) || core_dbus_cmd_ready); + assign _zz_29_ = _zz_30_; + assign core_dbus_cmd_valid = _zz_29_; + assign core_dbus_cmd_payload_write = _zz_31_; + assign core_dbus_cmd_payload_address = _zz_32_; + assign core_dbus_cmd_payload_data = _zz_33_; + assign core_dbus_cmd_payload_mask = _zz_34_; + assign _zz_39_ = 1'b0; + assign _zz_38_ = systemDebugger_1__io_mem_cmd_payload_address[7:0]; + assign _zz_40_ = apb3Router_1__io_outputs_0_PADDR[4:0]; + assign _zz_42_ = 1'b0; + assign _zz_41_ = apb3Router_1__io_outputs_1_PADDR[7:0]; + assign asyncReset = io_asyncReset; + assign mainClock = io_mainClock; + assign io_uart_txd = apb3UartCtrl_1__io_uart_txd; + assign io_jtag_tdo = jtagBridge_1__io_jtag_tdo; + assign core_dbus_cmd_ready = core_dbus_decoder_io_input_cmd_ready; + assign core_dbus_rsp_valid = core_dbus_decoder_io_input_rsp_valid; + assign core_dbus_rsp_payload_data = core_dbus_decoder_io_input_rsp_payload_data; + assign core_ibus_cmd_ready = core_ibus_decoder_io_input_cmd_ready; + assign core_ibus_rsp_valid = core_ibus_decoder_io_input_rsp_valid; + assign core_ibus_rsp_payload_data = core_ibus_decoder_io_input_rsp_payload_data; + assign _zz_43_ = core_dbus_decoder_io_outputs_1_cmd_payload_address[15:0]; + assign _zz_45_ = core_dbus_decoder_io_outputs_2_cmd_payload_address[15:0]; + assign _zz_44_ = core_ibus_decoder_io_outputs_0_cmd_payload_address[15:0]; + assign _zz_46_ = core_ibus_decoder_io_outputs_1_cmd_payload_address[15:0]; + assign _zz_37_ = 1'b0; + always @ (posedge mainClock) begin + resetCtrl_mainClockReset <= resetCtrl_bufferedReset; + resetCtrl_systemClockReset <= resetCtrl_bufferedReset; + if(core_cpu_debug_resetOut_regNext)begin + resetCtrl_systemClockReset <= 1'b1; + end + end + + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_5_ <= 1'b0; + _zz_11_ <= 1'b0; + _zz_24_ <= 1'b0; + _zz_30_ <= 1'b0; + end else begin + if(_zz_4_)begin + _zz_5_ <= 1'b0; + end + if(_zz_47_)begin + _zz_5_ <= _zz_1_; + end + if(_zz_4_)begin + _zz_11_ <= (_zz_1_ || _zz_5_); + end + if(_zz_23_)begin + _zz_24_ <= 1'b0; + end + if(_zz_48_)begin + _zz_24_ <= _zz_16_; + end + if(_zz_23_)begin + _zz_30_ <= (_zz_16_ || _zz_24_); + end + end + end + + always @ (posedge mainClock) begin + if(_zz_47_)begin + _zz_6_ <= 1'b0; + _zz_7_ <= _zz_3_; + _zz_8_ <= 32'h0; + _zz_9_ <= (4'bxxxx); + end + if(_zz_4_)begin + _zz_12_ <= (_zz_5_ ? _zz_6_ : 1'b0); + _zz_13_ <= (_zz_5_ ? _zz_7_ : _zz_3_); + _zz_14_ <= (_zz_5_ ? _zz_8_ : 32'h0); + _zz_15_ <= (_zz_5_ ? _zz_9_ : (4'bxxxx)); + end + if(_zz_48_)begin + _zz_25_ <= _zz_18_; + _zz_26_ <= _zz_19_; + _zz_27_ <= _zz_20_; + _zz_28_ <= _zz_21_; + end + if(_zz_23_)begin + _zz_31_ <= (_zz_24_ ? _zz_25_ : _zz_18_); + _zz_32_ <= (_zz_24_ ? _zz_26_ : _zz_19_); + _zz_33_ <= (_zz_24_ ? _zz_27_ : _zz_20_); + _zz_34_ <= (_zz_24_ ? _zz_28_ : _zz_21_); + end + end + + always @ (posedge mainClock) begin + core_cpu_debug_resetOut_regNext <= core_cpu_debug_resetOut; + end + + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + _zz_35_ <= 1'b0; + end else begin + _zz_35_ <= (systemDebugger_1__io_mem_cmd_valid && core_cpu_debug_bus_cmd_ready); + end + end + + +endmodule diff --git a/ulx3s/PQVexRiscvUlx3s.ys b/ulx3s/PQVexRiscvUlx3s.ys new file mode 100644 index 0000000..438c9a8 --- /dev/null +++ b/ulx3s/PQVexRiscvUlx3s.ys @@ -0,0 +1,2 @@ +read_verilog PQVexRiscvUlx3s.v +synth_ecp5 -json PQVexRiscvUlx3s.json diff --git a/ulx3s/PQVexRiscvUlx3s_yosys.log b/ulx3s/PQVexRiscvUlx3s_yosys.log new file mode 100644 index 0000000..1640408 --- /dev/null +++ b/ulx3s/PQVexRiscvUlx3s_yosys.log @@ -0,0 +1,7803 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os) + + +-- Parsing `PQVexRiscvUlx3s.v' using frontend `verilog' -- + +1. Executing Verilog-2005 frontend: PQVexRiscvUlx3s.v +Parsing Verilog input from `PQVexRiscvUlx3s.v' to AST representation. +Generating RTLIL representation for module `\BufferCC'. +Generating RTLIL representation for module `\BufferCC_1_'. +Generating RTLIL representation for module `\UartCtrlTx'. +Generating RTLIL representation for module `\UartCtrlRx'. +Generating RTLIL representation for module `\StreamFifoLowLatency'. +Generating RTLIL representation for module `\FlowCCByToggle'. +Generating RTLIL representation for module `\UartCtrl'. +Generating RTLIL representation for module `\StreamFifo'. +Generating RTLIL representation for module `\Prescaler'. +Generating RTLIL representation for module `\Timer'. +Generating RTLIL representation for module `\InterruptCtrl'. +Generating RTLIL representation for module `\StreamArbiter'. +Generating RTLIL representation for module `\StreamFork'. +Generating RTLIL representation for module `\StreamFifoLowLatency_1_'. +Generating RTLIL representation for module `\BufferCC_2_'. +Generating RTLIL representation for module `\VexRiscv'. +Generating RTLIL representation for module `\JtagBridge'. +Generating RTLIL representation for module `\SystemDebugger'. +Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'. +Generating RTLIL representation for module `\Apb3UartCtrl'. +Generating RTLIL representation for module `\MuraxApb3Timer'. +Generating RTLIL representation for module `\MyMem'. +Generating RTLIL representation for module `\Apb3Decoder'. +Generating RTLIL representation for module `\Apb3Router'. +Generating RTLIL representation for module `\PipelinedMemoryBusRamUlx3s'. +Generating RTLIL representation for module `\PipelinedMemoryBusDecoder'. +Generating RTLIL representation for module `\PipelinedMemoryBusDecoder_1_'. +Generating RTLIL representation for module `\PipelinedMemoryBusArbiter'. +Generating RTLIL representation for module `\PipelinedMemoryBusArbiter_1_'. +Generating RTLIL representation for module `\PQVexRiscvUlx3s'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -top PQVexRiscvUlx3s -json PQVexRiscvUlx3s.json' -- + +2. Executing SYNTH_ECP5 pass. + +2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_SLICE'. +Generating RTLIL representation for module `\DP16KD'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\DCUA'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +2.3. Executing HIERARCHY pass (managing design hierarchy). + +2.3.1. Analyzing design hierarchy.. +Top module: \PQVexRiscvUlx3s +Used module: \PipelinedMemoryBusArbiter_1_ +Used module: \StreamFifoLowLatency_1_ +Used module: \StreamFork +Used module: \StreamArbiter +Used module: \PipelinedMemoryBusArbiter +Used module: \PipelinedMemoryBusDecoder_1_ +Used module: \PipelinedMemoryBusDecoder +Used module: \PipelinedMemoryBusRamUlx3s +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \MyMem +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Timer +Used module: \Prescaler +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx +Used module: \PipelinedMemoryBusToApbBridge +Used module: \SystemDebugger +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1_ +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \BufferCC_2_ + +2.3.2. Analyzing design hierarchy.. +Top module: \PQVexRiscvUlx3s +Used module: \PipelinedMemoryBusArbiter_1_ +Used module: \StreamFifoLowLatency_1_ +Used module: \StreamFork +Used module: \StreamArbiter +Used module: \PipelinedMemoryBusArbiter +Used module: \PipelinedMemoryBusDecoder_1_ +Used module: \PipelinedMemoryBusDecoder +Used module: \PipelinedMemoryBusRamUlx3s +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \MyMem +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Timer +Used module: \Prescaler +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx +Used module: \PipelinedMemoryBusToApbBridge +Used module: \SystemDebugger +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1_ +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \BufferCC_2_ +Removed 0 unused modules. + +2.4. Executing PROC pass (convert processes to netlists). + +2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'. +Cleaned up 1 empty switch. + +2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8216$1266 in module PQVexRiscvUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8157$1253 in module PQVexRiscvUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8106$1246 in module PQVexRiscvUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8084$1241 in module PQVexRiscvUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:8077$1240 in module PQVexRiscvUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7489$1233 in module PipelinedMemoryBusArbiter_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7482$1232 in module PipelinedMemoryBusArbiter_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7306$1228 in module PipelinedMemoryBusDecoder_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7294$1210 in module PipelinedMemoryBusDecoder_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7281$1206 in module PipelinedMemoryBusDecoder_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7268$1202 in module PipelinedMemoryBusDecoder_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7256$1199 in module PipelinedMemoryBusDecoder_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7184$1191 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7172$1170 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7159$1166 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7146$1162 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7133$1158 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7118$1155 in module PipelinedMemoryBusDecoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:7042$1143 in module PipelinedMemoryBusRamUlx3s. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6938$1109 in module Apb3Router. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6885$1108 in module Apb3Decoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6877$1107 in module Apb3Decoder. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6815$1081 in module MyMem. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6715$1079 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6680$1076 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6649$1070 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6620$1069 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6610$1068 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6579$1062 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6550$1061 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6540$1060 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6511$1059 in module MuraxApb3Timer. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6469$1046 in module MuraxApb3Timer. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6323$1037 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6303$1036 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6286$1035 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6269$1034 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6252$1033 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6235$1032 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6215$1027 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6207$1026 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6200$1025 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6180$1024 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:6144$1009 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5954$1004 in module PipelinedMemoryBusToApbBridge. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5944$1001 in module PipelinedMemoryBusToApbBridge. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5930$999 in module PipelinedMemoryBusToApbBridge. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5875$995 in module SystemDebugger. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5849$991 in module SystemDebugger. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5738$974 in module JtagBridge. +Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5710$971 in module JtagBridge. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5656$954 in module JtagBridge. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:5432$946 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4817$790 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4808$781 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4801$780 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4794$779 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4787$778 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4779$777 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4771$776 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4762$775 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4753$774 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4744$773 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4725$772 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4657$718 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4646$716 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4623$715 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4599$703 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4590$700 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4581$699 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4564$694 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4550$693 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4521$688 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4441$682 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4429$675 in module VexRiscv. +Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4393$666 in module VexRiscv. +Marked 10 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4365$664 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4285$656 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4268$655 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4203$652 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4189$651 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4175$647 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4166$645 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4130$624 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4116$608 in module VexRiscv. +Marked 16 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4069$603 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4056$601 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4045$600 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4035$597 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4020$591 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:4006$590 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3939$583 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3923$581 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3908$580 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3898$570 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3874$561 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3839$549 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3818$543 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3792$525 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3774$519 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3765$517 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3758$516 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3750$514 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3739$510 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3732$508 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3725$507 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3709$506 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3699$505 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3692$504 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3681$502 in module VexRiscv. +Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3660$501 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3646$500 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3638$499 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3629$498 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3621$497 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3608$487 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3599$486 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3590$485 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3583$484 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3576$483 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3564$475 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3555$474 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3542$464 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3523$463 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3512$462 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3484$459 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3469$458 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3462$456 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3454$454 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3416$453 in module VexRiscv. +Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3385$451 in module VexRiscv. +Marked 11 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:3355$449 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1421$231 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1413$227 in module StreamFifoLowLatency_1_. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1393$216 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1384$213 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1377$212 in module StreamFifoLowLatency_1_. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1366$210 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1357$207 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1350$206 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1343$205 in module StreamFifoLowLatency_1_. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1270$195 in module StreamFork. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1250$188 in module StreamFork. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1202$185 in module StreamArbiter. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1138$167 in module InterruptCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1101$163 in module Timer. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1038$150 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1020$132 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1011$129 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:1004$128 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:997$126 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:988$123 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:981$122 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:974$121 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:899$111 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:884$110 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:877$109 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:780$106 in module FlowCCByToggle. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:706$99 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:697$97 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:689$96 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:680$95 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:665$87 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:658$86 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:649$84 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:642$83 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:635$82 in module StreamFifoLowLatency. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:553$61 in module UartCtrlRx. +Marked 6 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:474$43 in module UartCtrlRx. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:461$41 in module UartCtrlRx. +Marked 5 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:431$39 in module UartCtrlRx. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:260$14 in module UartCtrlTx. +Marked 3 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:238$13 in module UartCtrlTx. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:219$11 in module UartCtrlTx. +Marked 2 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:208$9 in module UartCtrlTx. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:198$6 in module UartCtrlTx. +Marked 1 switch rules as full_case in process $proc$PQVexRiscvUlx3s.v:97$1 in module BufferCC. +Removed a total of 0 dead cases. + +2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 30 redundant assignments. +Promoted 417 assignments to connections. + +2.4.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'. + Set init value: \Q = 1'0 +Found init rule in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'. + Set init value: \jtag_tap_fsm_state = 4'0000 +Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'. + Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000 +Found init rule in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'. + Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000 +Found init rule in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'. + Set init value: \inputArea_target = 1'0 + +2.4.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \resetCtrl_mainClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'. +Found async reset \resetCtrl_systemClockReset in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. +Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'. +Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'. +Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'. +Found async reset \resetCtrl_systemClockReset in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. +Found async reset \resetCtrl_systemClockReset in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. +Found async reset \resetCtrl_systemClockReset in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. +Found async reset \resetCtrl_mainClockReset in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. +Found async reset \resetCtrl_mainClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. +Found async reset \resetCtrl_systemClockReset in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. +Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. +Found async reset \resetCtrl_systemClockReset in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. +Found async reset \resetCtrl_systemClockReset in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'. +Found async reset \resetCtrl_systemClockReset in `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'. +Found async reset \resetCtrl_systemClockReset in `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'. +Found async reset \resetCtrl_systemClockReset in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. +Found async reset \resetCtrl_systemClockReset in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'. +Found async reset \resetCtrl_mainClockReset in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'. +Found async reset \resetCtrl_systemClockReset in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'. +Found async reset \resetCtrl_systemClockReset in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. +Found async reset \resetCtrl_systemClockReset in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. +Found async reset \resetCtrl_systemClockReset in `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'. + +2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'. +Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. + 1/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_EN[3:0]$1473 + 2/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_DATA[3:0]$1472 + 3/3: $0$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_ADDR[3:0]$1471 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. + 1/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_EN[3:0]$1417 + 2/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_DATA[3:0]$1416 + 3/3: $0$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_ADDR[3:0]$1415 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'. +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'. + 1/1: $0\_zz_35_[0:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'. +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + 1/16: $0\_zz_34_[3:0] + 2/16: $0\_zz_33_[31:0] + 3/16: $0\_zz_32_[31:0] + 4/16: $0\_zz_31_[0:0] + 5/16: $0\_zz_28_[3:0] + 6/16: $0\_zz_27_[31:0] + 7/16: $0\_zz_26_[31:0] + 8/16: $0\_zz_25_[0:0] + 9/16: $0\_zz_15_[3:0] + 10/16: $0\_zz_14_[31:0] + 11/16: $0\_zz_13_[31:0] + 12/16: $0\_zz_12_[0:0] + 13/16: $0\_zz_9_[3:0] + 14/16: $0\_zz_8_[31:0] + 15/16: $0\_zz_7_[31:0] + 16/16: $0\_zz_6_[0:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. + 1/4: $0\_zz_30_[0:0] + 2/4: $0\_zz_24_[0:0] + 3/4: $0\_zz_11_[0:0] + 4/4: $0\_zz_5_[0:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'. + 1/1: $0\resetCtrl_systemClockReset[0:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'. + 1/1: $1\_zz_22_[3:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'. + 1/1: $1\core_externalInterrupt[0:0] +Creating decoders for process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'. + 1/1: $1\core_timerInterrupt[0:0] +Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'. + 1/1: $1\streamFork_2__io_outputs_1_translated_ready[0:0] +Creating decoders for process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'. + 1/1: $1\streamFork_2__io_outputs_1_translated_thrown_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'. + 1/2: $0\logic_rspHits_1[0:0] + 2/2: $0\logic_rspHits_0[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'. + 1/1: $0\logic_rspPendingCounter[1:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'. + 1/1: $1\io_input_cmd_ready[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'. + 1/1: $1\io_outputs_1_cmd_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'. + 1/1: $1\io_outputs_0_cmd_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'. + 1/1: $1\_zz_3_[31:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. + 1/3: $0\logic_rspHits_2[0:0] + 2/3: $0\logic_rspHits_1[0:0] + 3/3: $0\logic_rspHits_0[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'. + 1/1: $0\logic_rspPendingCounter[1:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'. + 1/1: $1\io_input_cmd_ready[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'. + 1/1: $1\io_outputs_2_cmd_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'. + 1/1: $1\io_outputs_1_cmd_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'. + 1/1: $1\io_outputs_0_cmd_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'. + 1/1: $1\_zz_4_[31:0] +Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'. + 1/1: $0\_zz_1_[0:0] +Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + 1/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 + 2/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA[7:0]$1123 + 3/12: $0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_ADDR[13:0]$1122 + 4/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 + 5/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA[7:0]$1126 + 6/12: $0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_ADDR[13:0]$1125 + 7/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 + 8/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA[7:0]$1129 + 9/12: $0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_ADDR[13:0]$1128 + 10/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 + 11/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA[7:0]$1132 + 12/12: $0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_ADDR[13:0]$1131 +Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. + 1/4: $0\_zz_8_[7:0] + 2/4: $0\_zz_7_[7:0] + 3/4: $0\_zz_6_[7:0] + 4/4: $0\_zz_5_[7:0] +Creating decoders for process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'. +Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'. +Creating decoders for process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. + 1/3: $1\_zz_5_[0:0] + 2/3: $1\_zz_4_[31:0] + 3/3: $1\_zz_3_[0:0] +Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'. + 1/1: $1\io_input_PSLVERROR[0:0] +Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'. + 1/1: $1\io_input_PREADY[0:0] +Creating decoders for process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'. +Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'. + 1/1: $0\myReg[31:0] +Creating decoders for process `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'. + 1/1: $1\io_bus_PRDATA[31:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. + 1/3: $0\timerB_io_limit_driver[15:0] + 2/3: $0\timerA_io_limit_driver[15:0] + 3/3: $0\_zz_1_[15:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + 1/5: $0\interruptCtrl_1__io_masks_driver[1:0] + 2/5: $0\timerBBridge_clearsEnable[0:0] + 3/5: $0\timerBBridge_ticksEnable[1:0] + 4/5: $0\timerABridge_clearsEnable[0:0] + 5/5: $0\timerABridge_ticksEnable[1:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'. +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'. + 1/2: $2\_zz_12_[1:0] + 2/2: $1\_zz_12_[1:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'. + 1/2: $2\_zz_6_[0:0] + 2/2: $1\_zz_6_[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'. + 1/2: $2\_zz_5_[0:0] + 2/2: $1\_zz_5_[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'. + 1/2: $2\timerBBridge_busClearing[0:0] + 2/2: $1\timerBBridge_busClearing[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'. + 1/2: $2\_zz_4_[0:0] + 2/2: $1\_zz_4_[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'. + 1/2: $2\_zz_3_[0:0] + 2/2: $1\_zz_3_[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'. + 1/2: $2\timerABridge_busClearing[0:0] + 2/2: $1\timerABridge_busClearing[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'. + 1/2: $2\_zz_2_[0:0] + 2/2: $1\_zz_2_[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'. + 1/3: $1\io_apb_PRDATA[16:0] [16] + 2/3: $1\io_apb_PRDATA[16:0] [15:2] + 3/3: $1\io_apb_PRDATA[16:0] [1:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'. +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'. +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + 1/6: $0\bridge_misc_doBreak[0:0] + 2/6: $0\bridge_misc_breakDetected[0:0] + 3/6: $0\bridge_misc_readOverflowError[0:0] + 4/6: $0\bridge_misc_readError[0:0] + 5/6: $0\bridge_interruptCtrl_readIntEnable[0:0] + 6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'. + 1/2: $2\_zz_6_[0:0] + 2/2: $1\_zz_6_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'. + 1/2: $2\_zz_5_[0:0] + 2/2: $1\_zz_5_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'. + 1/2: $2\_zz_4_[0:0] + 2/2: $1\_zz_4_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'. + 1/2: $2\_zz_3_[0:0] + 2/2: $1\_zz_3_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'. + 1/2: $2\_zz_2_[0:0] + 2/2: $1\_zz_2_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'. + 1/2: $2\bridge_read_streamBreaked_ready[0:0] + 2/2: $1\bridge_read_streamBreaked_ready[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'. + 1/1: $1\_zz_8_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'. + 1/1: $1\bridge_read_streamBreaked_valid[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'. + 1/2: $2\_zz_1_[0:0] + 2/2: $1\_zz_1_[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'. +Creating decoders for process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'. + 1/9: $2\io_apb_PRDATA[20:15] [5:2] + 2/9: $1\io_apb_PRDATA[9:0] [7:2] + 3/9: $2\io_apb_PRDATA[20:15] [1] + 4/9: $1\io_apb_PRDATA[9:0] [8] + 5/9: $2\io_apb_PRDATA[20:15] [0] + 6/9: $1\io_apb_PRDATA[9:0] [1] + 7/9: $3\io_apb_PRDATA[28:24] + 8/9: $1\io_apb_PRDATA[9:0] [9] + 9/9: $1\io_apb_PRDATA[9:0] [0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'. +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. + 1/2: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0] + 2/2: $0\state[0:0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'. + 1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0] + 2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'. + 1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0] + 2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0] +Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'. + 1/2: $0\dispatcher_headerShifter[7:0] + 2/2: $0\dispatcher_dataShifter[66:0] +Creating decoders for process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. + 1/3: $0\dispatcher_counter[2:0] + 2/3: $0\dispatcher_headerLoaded[0:0] + 3/3: $0\dispatcher_dataLoaded[0:0] +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'. +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'. +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + 1/4: $0\jtag_readArea_shifter[33:0] + 2/4: $0\jtag_idcodeArea_shifter[31:0] + 3/4: $0\jtag_tap_instructionShift[3:0] + 4/4: $0\jtag_tap_instruction[3:0] +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. + 1/3: $0\system_rsp_payload_data[31:0] + 2/3: $0\system_rsp_payload_error[0:0] + 3/3: $0\system_rsp_valid[0:0] +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'. + 1/2: $2\jtag_writeArea_source_valid[0:0] + 2/2: $1\jtag_writeArea_source_valid[0:0] +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'. + 1/5: $5\jtag_tap_tdoUnbufferd[0:0] + 2/5: $4\jtag_tap_tdoUnbufferd[0:0] + 3/5: $3\jtag_tap_tdoUnbufferd[0:0] + 4/5: $2\jtag_tap_tdoUnbufferd[0:0] + 5/5: $1\jtag_tap_tdoUnbufferd[0:0] +Creating decoders for process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'. + 1/1: $1\_zz_1_[3:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + 1/8: $0\DebugPlugin_hardwareBreakpoints_2_valid[0:0] + 2/8: $0\DebugPlugin_hardwareBreakpoints_1_valid[0:0] + 3/8: $0\DebugPlugin_hardwareBreakpoints_0_valid[0:0] + 4/8: $0\DebugPlugin_haltedByBreak[0:0] + 5/8: $0\DebugPlugin_godmode[0:0] + 6/8: $0\DebugPlugin_stepIt[0:0] + 7/8: $0\DebugPlugin_haltIt[0:0] + 8/8: $0\DebugPlugin_resetIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + 1/5: $0\DebugPlugin_firstCycle[0:0] + 2/5: $0\DebugPlugin_busReadDataReg[31:0] + 3/5: $0\DebugPlugin_hardwareBreakpoints_2_pc[30:0] + 4/5: $0\DebugPlugin_hardwareBreakpoints_1_pc[30:0] + 5/5: $0\DebugPlugin_hardwareBreakpoints_0_pc[30:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + 1/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [32] + 2/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [31:0] + 3/92: $0\memory_MulDivIterativePlugin_accumulator[64:0] [64:32] + 4/92: $0\execute_CsrPlugin_csr_2946[0:0] + 5/92: $0\execute_CsrPlugin_csr_2818[0:0] + 6/92: $0\execute_CsrPlugin_csr_2944[0:0] + 7/92: $0\execute_CsrPlugin_csr_2816[0:0] + 8/92: $0\execute_CsrPlugin_csr_834[0:0] + 9/92: $0\execute_CsrPlugin_csr_773[0:0] + 10/92: $0\execute_CsrPlugin_csr_772[0:0] + 11/92: $0\execute_CsrPlugin_csr_836[0:0] + 12/92: $0\execute_CsrPlugin_csr_768[0:0] + 13/92: $0\decode_to_execute_RS1[31:0] + 14/92: $0\memory_to_writeBack_MEMORY_ENABLE[0:0] + 15/92: $0\execute_to_memory_MEMORY_ENABLE[0:0] + 16/92: $0\decode_to_execute_MEMORY_ENABLE[0:0] + 17/92: $0\execute_to_memory_BRANCH_DO[0:0] + 18/92: $0\decode_to_execute_IS_RS2_SIGNED[0:0] + 19/92: $0\execute_to_memory_MUL_HH[31:0] + 20/92: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0] + 21/92: $0\execute_to_memory_FORMAL_PC_NEXT[31:0] + 22/92: $0\decode_to_execute_FORMAL_PC_NEXT[31:0] + 23/92: $0\decode_to_execute_ALU_CTRL[1:0] + 24/92: $0\decode_to_execute_IS_CSR[0:0] + 25/92: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0] + 26/92: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0] + 27/92: $0\execute_to_memory_IS_DIV[0:0] + 28/92: $0\decode_to_execute_IS_DIV[0:0] + 29/92: $0\execute_to_memory_MUL_LH[31:0] + 30/92: $0\memory_to_writeBack_MEMORY_STORE[0:0] + 31/92: $0\execute_to_memory_MEMORY_STORE[0:0] + 32/92: $0\decode_to_execute_MEMORY_STORE[0:0] + 33/92: $0\execute_to_memory_MUL_HL[31:0] + 34/92: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0] + 35/92: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0] + 36/92: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0] + 37/92: $0\execute_to_memory_BRANCH_CALC[31:0] + 38/92: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0] + 39/92: $0\execute_to_memory_SHIFT_RIGHT[31:0] + 40/92: $0\memory_to_writeBack_PC[31:0] + 41/92: $0\execute_to_memory_PC[31:0] + 42/92: $0\decode_to_execute_PC[31:0] + 43/92: $0\decode_to_execute_IS_RS1_SIGNED[0:0] + 44/92: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0] + 45/92: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0] + 46/92: $0\memory_to_writeBack_MUL[63:0] + 47/92: $0\memory_to_writeBack_SRC2[31:0] + 48/92: $0\execute_to_memory_SRC2[31:0] + 49/92: $0\decode_to_execute_SRC2[31:0] + 50/92: $0\execute_to_memory_INSTRUCTION[31:0] + 51/92: $0\decode_to_execute_INSTRUCTION[31:0] + 52/92: $0\memory_to_writeBack_IS_MUL[0:0] + 53/92: $0\execute_to_memory_IS_MUL[0:0] + 54/92: $0\decode_to_execute_IS_MUL[0:0] + 55/92: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0] + 56/92: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0] + 57/92: $0\decode_to_execute_BRANCH_CTRL[1:0] + 58/92: $0\decode_to_execute_DO_EBREAK[0:0] + 59/92: $0\memory_to_writeBack_SRC1[31:0] + 60/92: $0\execute_to_memory_SRC1[31:0] + 61/92: $0\decode_to_execute_SRC1[31:0] + 62/92: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0] + 63/92: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0] + 64/92: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0] + 65/92: $0\decode_to_execute_CSR_READ_OPCODE[0:0] + 66/92: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0] + 67/92: $0\decode_to_execute_RS2[31:0] + 68/92: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0] + 69/92: $0\execute_to_memory_SHIFT_CTRL[1:0] + 70/92: $0\decode_to_execute_SHIFT_CTRL[1:0] + 71/92: $0\memory_to_writeBack_ENV_CTRL[0:0] + 72/92: $0\execute_to_memory_ENV_CTRL[0:0] + 73/92: $0\decode_to_execute_ENV_CTRL[0:0] + 74/92: $0\execute_to_memory_MUL_LL[31:0] + 75/92: $0\memory_MulDivIterativePlugin_div_result[31:0] + 76/92: $0\memory_MulDivIterativePlugin_div_done[0:0] + 77/92: $0\memory_MulDivIterativePlugin_div_needRevert[0:0] + 78/92: $0\memory_MulDivIterativePlugin_rs1[32:0] [31:0] + 79/92: $0\memory_MulDivIterativePlugin_rs2[31:0] + 80/92: $0\CsrPlugin_mip_MSIP[0:0] + 81/92: $0\CsrPlugin_interrupt_targetPrivilege[1:0] + 82/92: $0\CsrPlugin_interrupt_code[3:0] + 83/92: $0\CsrPlugin_minstret[63:0] + 84/92: $0\CsrPlugin_mcause_exceptionCode[3:0] + 85/92: $0\CsrPlugin_mcause_interrupt[0:0] + 86/92: $0\CsrPlugin_mepc[31:0] + 87/92: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0] + 88/92: $0\_zz_63_[0:0] + 89/92: $0\_zz_62_[31:0] + 90/92: $0\_zz_61_[0:0] + 91/92: $0\_zz_60_[31:0] + 92/92: $0\_zz_58_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + 1/38: $0\memory_MulDivIterativePlugin_div_counter_value[5:0] + 2/38: $0\_zz_100_[0:0] + 3/38: $0\_zz_88_[0:0] + 4/38: $0\execute_CsrPlugin_wfiWake[0:0] + 5/38: $0\CsrPlugin_hadException[0:0] + 6/38: $0\CsrPlugin_interrupt_valid[0:0] + 7/38: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0] + 8/38: $0\IBusSimplePlugin_pending_value[2:0] + 9/38: $0\IBusSimplePlugin_fetchPc_booted[0:0] + 10/38: $0\_zz_125_[2:0] + 11/38: $0\memory_to_writeBack_INSTRUCTION[31:0] + 12/38: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0] + 13/38: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0] + 14/38: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0] + 15/38: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0] + 16/38: $0\CsrPlugin_mie_MSIE[0:0] + 17/38: $0\CsrPlugin_mie_MTIE[0:0] + 18/38: $0\CsrPlugin_mie_MEIE[0:0] + 19/38: $0\CsrPlugin_mstatus_MPP[1:0] + 20/38: $0\CsrPlugin_mstatus_MPIE[0:0] + 21/38: $0\CsrPlugin_mstatus_MIE[0:0] + 22/38: $0\CsrPlugin_mtvec_base[29:0] + 23/38: $0\CsrPlugin_mtvec_mode[1:0] + 24/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0] + 25/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0] + 26/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0] + 27/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0] + 28/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0] + 29/38: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0] + 30/38: $0\_zz_59_[0:0] + 31/38: $0\_zz_57_[0:0] + 32/38: $0\_zz_55_[0:0] + 33/38: $0\IBusSimplePlugin_fetchPc_inc[0:0] + 34/38: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0] + 35/38: $0\IBusSimplePlugin_fetchPc_pcReg[31:0] + 36/38: $0\writeBack_arbitration_isValid[0:0] + 37/38: $0\memory_arbitration_isValid[0:0] + 38/38: $0\execute_arbitration_isValid[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'. + 1/1: $1\_zz_134_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'. + 1/1: $1\_zz_133_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'. + 1/1: $1\_zz_132_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'. + 1/1: $1\_zz_131_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'. + 1/2: $1\_zz_130_[3:0] + 2/2: $2\_zz_130_[31:31] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'. + 1/2: $1\_zz_129_[31:0] [31:2] + 2/2: $1\_zz_129_[31:0] [1:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'. + 1/3: $1\_zz_128_[3:3] + 2/3: $2\_zz_128_[7:7] + 3/3: $3\_zz_128_[11:11] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'. + 1/3: $1\_zz_127_[3:3] + 2/3: $2\_zz_127_[7:7] + 3/3: $3\_zz_127_[11:11] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'. + 1/3: $1\_zz_126_[3:3] + 2/3: $2\_zz_126_[7:7] + 3/3: $3\_zz_126_[12:11] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'. + 1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'. + 1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0] + 2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0] + 3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'. + 1/5: $1\debug_bus_rsp_data[4:0] [4] + 2/5: $1\debug_bus_rsp_data[4:0] [2] + 3/5: $1\debug_bus_rsp_data[4:0] [1] + 4/5: $1\debug_bus_rsp_data[4:0] [0] + 5/5: $1\debug_bus_rsp_data[4:0] [3] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'. + 1/3: $3\debug_bus_cmd_ready[0:0] + 2/3: $2\debug_bus_cmd_ready[0:0] + 3/3: $1\debug_bus_cmd_ready[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'. + 1/2: $2\memory_MulDivIterativePlugin_div_counter_valueNext[5:0] + 2/2: $1\memory_MulDivIterativePlugin_div_counter_valueNext[5:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'. + 1/1: $1\memory_MulDivIterativePlugin_div_counter_willClear[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'. + 1/2: $2\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0] + 2/2: $1\memory_MulDivIterativePlugin_div_counter_willIncrement[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'. + 1/1: $1\writeBack_Mul16Plugin_bSigned[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'. + 1/1: $1\writeBack_Mul16Plugin_aSigned[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'. + 1/1: $1\_zz_118_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'. + 1/1: $1\_zz_111_[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'. + 1/3: $3\_zz_110_[0:0] + 2/3: $2\_zz_110_[0:0] + 3/3: $1\_zz_110_[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'. + 1/10: $10\_zz_99_[0:0] + 2/10: $9\_zz_99_[0:0] + 3/10: $8\_zz_99_[0:0] + 4/10: $7\_zz_99_[0:0] + 5/10: $6\_zz_99_[0:0] + 6/10: $5\_zz_99_[0:0] + 7/10: $4\_zz_99_[0:0] + 8/10: $3\_zz_99_[0:0] + 9/10: $2\_zz_99_[0:0] + 10/10: $1\_zz_99_[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'. + 1/10: $10\_zz_98_[0:0] + 2/10: $9\_zz_98_[0:0] + 3/10: $8\_zz_98_[0:0] + 4/10: $7\_zz_98_[0:0] + 5/10: $6\_zz_98_[0:0] + 6/10: $5\_zz_98_[0:0] + 7/10: $4\_zz_98_[0:0] + 8/10: $3\_zz_98_[0:0] + 9/10: $2\_zz_98_[0:0] + 10/10: $1\_zz_98_[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'. + 1/1: $1\execute_SrcPlugin_addSub[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'. + 1/1: $1\_zz_95_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'. + 1/1: $1\_zz_90_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'. + 1/1: $1\_zz_89_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'. + 1/1: $1\execute_IntAluPlugin_bitwise[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'. + 1/1: $1\lastStageRegFileWrite_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'. + 1/1: $1\execute_CsrPlugin_writeData[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'. + 1/2: $2\execute_CsrPlugin_illegalInstruction[0:0] + 2/2: $1\execute_CsrPlugin_illegalInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'. + 1/16: $16\execute_CsrPlugin_illegalAccess[0:0] + 2/16: $15\execute_CsrPlugin_illegalAccess[0:0] + 3/16: $14\execute_CsrPlugin_illegalAccess[0:0] + 4/16: $13\execute_CsrPlugin_illegalAccess[0:0] + 5/16: $12\execute_CsrPlugin_illegalAccess[0:0] + 6/16: $11\execute_CsrPlugin_illegalAccess[0:0] + 7/16: $10\execute_CsrPlugin_illegalAccess[0:0] + 8/16: $9\execute_CsrPlugin_illegalAccess[0:0] + 9/16: $8\execute_CsrPlugin_illegalAccess[0:0] + 10/16: $7\execute_CsrPlugin_illegalAccess[0:0] + 11/16: $6\execute_CsrPlugin_illegalAccess[0:0] + 12/16: $5\execute_CsrPlugin_illegalAccess[0:0] + 13/16: $4\execute_CsrPlugin_illegalAccess[0:0] + 14/16: $3\execute_CsrPlugin_illegalAccess[0:0] + 15/16: $2\execute_CsrPlugin_illegalAccess[0:0] + 16/16: $1\execute_CsrPlugin_illegalAccess[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'. + 1/1: $1\CsrPlugin_xtvec_base[29:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'. + 1/1: $1\CsrPlugin_xtvec_mode[1:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'. + 1/1: $1\CsrPlugin_pipelineLiberator_done[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'. + 1/1: $1\CsrPlugin_privilege[1:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'. + 1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'. +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'. + 1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8] + 2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'. + 1/1: $1\_zz_67_[3:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'. + 1/1: $1\_zz_66_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'. + 1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'. + 1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'. + 1/1: $1\decode_arbitration_isValid[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'. + 1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0] + 2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'. + 1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'. + 1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'. + 1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'. + 1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'. + 1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'. + 1/1: $1\CsrPlugin_allowException[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'. + 1/1: $1\CsrPlugin_allowInterrupts[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'. + 1/1: $1\CsrPlugin_forceMachineWire[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'. + 1/3: $3\CsrPlugin_jumpInterface_payload[31:0] + 2/3: $2\CsrPlugin_jumpInterface_payload[31:0] + 3/3: $1\CsrPlugin_jumpInterface_payload[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'. + 1/2: $2\CsrPlugin_jumpInterface_valid[0:0] + 2/2: $1\CsrPlugin_jumpInterface_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'. + 1/1: $1\CsrPlugin_thirdPartyWake[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'. + 1/2: $2\IBusSimplePlugin_incomingInstruction[0:0] + 2/2: $1\IBusSimplePlugin_incomingInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'. + 1/6: $6\IBusSimplePlugin_fetcherHalt[0:0] + 2/6: $5\IBusSimplePlugin_fetcherHalt[0:0] + 3/6: $4\IBusSimplePlugin_fetcherHalt[0:0] + 4/6: $3\IBusSimplePlugin_fetcherHalt[0:0] + 5/6: $2\IBusSimplePlugin_fetcherHalt[0:0] + 6/6: $1\IBusSimplePlugin_fetcherHalt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'. + 1/2: $2\writeBack_arbitration_flushNext[0:0] + 2/2: $1\writeBack_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'. + 1/1: $1\writeBack_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'. + 1/1: $1\memory_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'. + 1/1: $1\memory_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'. + 1/3: $3\memory_arbitration_haltItself[0:0] + 2/3: $2\memory_arbitration_haltItself[0:0] + 3/3: $1\memory_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'. + 1/2: $2\execute_arbitration_flushNext[0:0] + 2/2: $1\execute_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'. + 1/2: $2\execute_arbitration_flushIt[0:0] + 2/2: $1\execute_arbitration_flushIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'. + 1/1: $1\execute_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'. + 1/1: $1\execute_arbitration_haltByOther[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'. + 1/3: $3\execute_arbitration_haltItself[0:0] + 2/3: $2\execute_arbitration_haltItself[0:0] + 3/3: $1\execute_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'. + 1/1: $1\decode_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'. + 1/3: $3\decode_arbitration_haltByOther[0:0] + 2/3: $2\decode_arbitration_haltByOther[0:0] + 3/3: $1\decode_arbitration_haltByOther[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'. + 1/1: $1\decode_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'. + 1/1: $1\_zz_48_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'. + 1/3: $3\_zz_47_[31:0] + 2/3: $2\_zz_47_[31:0] + 3/3: $1\_zz_47_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'. + 1/1: $1\_zz_43_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'. + 1/1: $1\decode_REGFILE_WRITE_VALID[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'. + 1/1: $1\_zz_35_[0:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'. + 1/3: $3\_zz_23_[31:0] + 2/3: $2\_zz_23_[31:0] + 3/3: $1\_zz_23_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'. + 1/11: $11\decode_RS1[31:0] + 2/11: $10\decode_RS1[31:0] + 3/11: $9\decode_RS1[31:0] + 4/11: $8\decode_RS1[31:0] + 5/11: $7\decode_RS1[31:0] + 6/11: $6\decode_RS1[31:0] + 7/11: $5\decode_RS1[31:0] + 8/11: $4\decode_RS1[31:0] + 9/11: $3\decode_RS1[31:0] + 10/11: $2\decode_RS1[31:0] + 11/11: $1\decode_RS1[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'. + 1/11: $11\decode_RS2[31:0] + 2/11: $10\decode_RS2[31:0] + 3/11: $9\decode_RS2[31:0] + 4/11: $8\decode_RS2[31:0] + 5/11: $7\decode_RS2[31:0] + 6/11: $6\decode_RS2[31:0] + 7/11: $5\decode_RS2[31:0] + 8/11: $4\decode_RS2[31:0] + 9/11: $3\decode_RS2[31:0] + 10/11: $2\decode_RS2[31:0] + 11/11: $1\decode_RS2[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. + 1/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 + 2/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_DATA[31:0]$419 + 3/3: $0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_ADDR[4:0]$418 +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'. + 1/1: $0\_zz_138_[31:0] +Creating decoders for process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'. + 1/1: $0\_zz_137_[31:0] +Creating decoders for process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'. +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. + 1/3: $0\popPtr_value[2:0] + 2/3: $0\pushPtr_value[2:0] + 3/3: $0\risingOccupancy[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'. + 1/1: $1\io_occupancy[2:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'. + 1/2: $2\popPtr_valueNext[2:0] + 2/2: $1\popPtr_valueNext[2:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'. + 1/1: $1\popPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'. + 1/1: $1\popPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'. + 1/2: $2\pushPtr_valueNext[2:0] + 2/2: $1\pushPtr_valueNext[2:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'. + 1/1: $1\pushPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'. + 1/1: $1\pushPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'. + 1/1: $1\_zz_1_[0:0] +Creating decoders for process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. + 1/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 + 2/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_DATA[1:0]$203 + 3/3: $0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_ADDR[2:0]$202 +Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. + 1/2: $0\_zz_1_[0:0] + 2/2: $0\_zz_2_[0:0] +Creating decoders for process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'. + 1/2: $2\io_input_ready[0:0] + 2/2: $1\io_input_ready[0:0] +Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'. + 1/2: $0\maskLocked_1[0:0] + 2/2: $0\maskLocked_0[0:0] +Creating decoders for process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'. + 1/1: $0\locked[0:0] +Creating decoders for process `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'. + 1/1: $0\pendings[1:0] +Creating decoders for process `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'. + 1/1: $0\counter[15:0] +Creating decoders for process `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'. + 1/1: $0\inhibitFull[0:0] +Creating decoders for process `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'. + 1/1: $0\counter[15:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. + 1/4: $0\_zz_2_[0:0] + 2/4: $0\logic_popPtr_value[3:0] + 3/4: $0\logic_pushPtr_value[3:0] + 4/4: $0\logic_risingOccupancy[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'. + 1/1: $1\logic_popPtr_valueNext[3:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'. + 1/1: $1\logic_popPtr_willClear[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'. + 1/1: $1\logic_popPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'. + 1/1: $1\logic_pushPtr_valueNext[3:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'. + 1/1: $1\logic_pushPtr_willClear[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'. + 1/1: $1\logic_pushPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'. + 1/1: $1\_zz_1_[0:0] +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. + 1/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 + 2/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA[7:0]$119 + 3/3: $0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR[3:0]$118 +Creating decoders for process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'. + 1/1: $0\_zz_3_[7:0] +Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'. + 1/1: $0\clockDivider_counter[19:0] +Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'. + 1/1: $1\io_write_ready[0:0] +Creating decoders for process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'. + 1/1: $1\io_write_thrown_valid[0:0] +Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'. +Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'. + 1/1: $0\outputArea_flow_regNext_valid[0:0] +Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'. +Creating decoders for process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. + 1/3: $0\inputArea_data_fragment[0:0] + 2/3: $0\inputArea_data_last[0:0] + 3/3: $0\inputArea_target[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'. + 1/1: $0\_zz_3_[32:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'. + 1/1: $0\risingOccupancy[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'. + 1/1: $1\io_pop_payload_inst[31:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'. + 1/1: $1\io_pop_payload_error[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'. + 1/1: $1\io_pop_valid[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'. + 1/1: $1\popPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'. + 1/1: $1\popPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'. + 1/1: $1\pushPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'. + 1/1: $1\pushPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'. + 1/1: $1\_zz_1_[0:0] +Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + 1/9: $2$lookahead\stateMachine_shifter$60[7:0]$74 + 2/9: $2$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$73 + 3/9: $2$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$72 + 4/9: $1$lookahead\stateMachine_shifter$60[7:0]$70 + 5/9: $1$bitselwrite$data$PQVexRiscvUlx3s.v:580$28[7:0]$69 + 6/9: $1$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27[7:0]$68 + 7/9: $0\bitCounter_value[2:0] + 8/9: $0\bitTimer_counter[2:0] + 9/9: $0\stateMachine_parity[0:0] +Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + 1/8: $0\stateMachine_validReg[0:0] + 2/8: $0\sampler_tick[0:0] + 3/8: $0\sampler_value[0:0] + 4/8: $0\_zz_1_[0:0] + 5/8: $0\break_counter[6:0] + 6/8: $0\sampler_samples_2[0:0] + 7/8: $0\sampler_samples_1[0:0] + 8/8: $0\stateMachine_state[2:0] +Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'. + 1/2: $2\bitTimer_tick[0:0] + 2/2: $1\bitTimer_tick[0:0] +Creating decoders for process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'. + 1/5: $5\io_error[0:0] + 2/5: $4\io_error[0:0] + 3/5: $3\io_error[0:0] + 4/5: $2\io_error[0:0] + 5/5: $1\io_error[0:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'. + 1/2: $0\stateMachine_parity[0:0] + 2/2: $0\tickCounter_value[2:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. + 1/3: $0\_zz_1_[0:0] + 2/3: $0\clockDivider_counter_value[2:0] + 3/3: $0\stateMachine_state[2:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'. + 1/3: $3\io_write_ready[0:0] + 2/3: $2\io_write_ready[0:0] + 3/3: $1\io_write_ready[0:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'. + 1/1: $1\stateMachine_txd[0:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'. + 1/2: $2\clockDivider_counter_valueNext[2:0] + 2/2: $1\clockDivider_counter_valueNext[2:0] +Creating decoders for process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'. + 1/1: $1\clockDivider_counter_willIncrement[0:0] +Creating decoders for process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'. +Creating decoders for process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'. + 1/2: $0\buffers_1[0:0] + 2/2: $0\buffers_0[0:0] + +2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\PQVexRiscvUlx3s.\_zz_22_' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'. +No latch inferred for signal `\PQVexRiscvUlx3s.\core_externalInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'. +No latch inferred for signal `\PQVexRiscvUlx3s.\core_timerInterrupt' from process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'. +No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_ready' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'. +No latch inferred for signal `\PipelinedMemoryBusArbiter_1_.\streamFork_2__io_outputs_1_translated_thrown_valid' from process `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'. +No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'. +No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'. +No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'. +No latch inferred for signal `\PipelinedMemoryBusDecoder_1_.\_zz_3_' from process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'. +No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_input_cmd_ready' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'. +No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_2_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'. +No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_1_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'. +No latch inferred for signal `\PipelinedMemoryBusDecoder.\io_outputs_0_cmd_valid' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'. +No latch inferred for signal `\PipelinedMemoryBusDecoder.\_zz_4_' from process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'. +No latch inferred for signal `\PipelinedMemoryBusRamUlx3s.\_zz_4_' from process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'. +No latch inferred for signal `\Apb3Router.\_zz_3_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. +No latch inferred for signal `\Apb3Router.\_zz_4_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. +No latch inferred for signal `\Apb3Router.\_zz_5_' from process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. +No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'. +No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'. +No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'. +No latch inferred for signal `\MyMem.\io_bus_PRDATA' from process `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_11_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_12_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_6_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_5_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'. +No latch inferred for signal `\MuraxApb3Timer.\timerBBridge_busClearing' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_4_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_3_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'. +No latch inferred for signal `\MuraxApb3Timer.\timerABridge_busClearing' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_2_' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'. +No latch inferred for signal `\MuraxApb3Timer.\io_apb_PRDATA' from process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'. +No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6175$1006$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'. +No latch inferred for signal `\Apb3UartCtrl.$func$\zz_bridge_uartConfigReg_clockDivider$PQVexRiscvUlx3s.v:6175$1007$\zz_bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_6_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_5_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_4_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_3_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_2_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_8_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_1_' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'. +No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'. +No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'. +No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'. +No latch inferred for signal `\JtagBridge.\jtag_writeArea_source_valid' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'. +No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'. +No latch inferred for signal `\JtagBridge.\_zz_1_' from process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'. +No latch inferred for signal `\VexRiscv.\_zz_134_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'. +No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'. +No latch inferred for signal `\VexRiscv.\_zz_132_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'. +No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'. +No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'. +No latch inferred for signal `\VexRiscv.\_zz_129_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'. +No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'. +No latch inferred for signal `\VexRiscv.\_zz_127_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'. +No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'. +No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'. +No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'. +No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'. +No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_valueNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'. +No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willClear' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'. +No latch inferred for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'. +No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_bSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'. +No latch inferred for signal `\VexRiscv.\writeBack_Mul16Plugin_aSigned' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'. +No latch inferred for signal `\VexRiscv.\_zz_118_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'. +No latch inferred for signal `\VexRiscv.\_zz_117_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'. +No latch inferred for signal `\VexRiscv.\_zz_115_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'. +No latch inferred for signal `\VexRiscv.\_zz_113_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'. +No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'. +No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'. +No latch inferred for signal `\VexRiscv.\_zz_99_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'. +No latch inferred for signal `\VexRiscv.\_zz_98_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'. +No latch inferred for signal `\VexRiscv.\_zz_97_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'. +No latch inferred for signal `\VexRiscv.\_zz_96_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'. +No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'. +No latch inferred for signal `\VexRiscv.\_zz_95_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'. +No latch inferred for signal `\VexRiscv.\_zz_94_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'. +No latch inferred for signal `\VexRiscv.\_zz_92_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'. +No latch inferred for signal `\VexRiscv.\_zz_90_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'. +No latch inferred for signal `\VexRiscv.\_zz_89_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'. +No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'. +No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'. +No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'. +No latch inferred for signal `\VexRiscv.\_zz_71_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'. +No latch inferred for signal `\VexRiscv.\_zz_69_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'. +No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'. +No latch inferred for signal `\VexRiscv.\_zz_67_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'. +No latch inferred for signal `\VexRiscv.\_zz_66_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'. +No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'. +No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'. +No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'. +No latch inferred for signal `\VexRiscv.\_zz_48_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'. +No latch inferred for signal `\VexRiscv.\_zz_47_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'. +No latch inferred for signal `\VexRiscv.\_zz_43_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'. +No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'. +No latch inferred for signal `\VexRiscv.\_zz_35_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'. +No latch inferred for signal `\VexRiscv.\_zz_23_' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'. +No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'. +No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\io_occupancy' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\popPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_valueNext' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willClear' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\pushPtr_willIncrement' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'. +No latch inferred for signal `\StreamFifoLowLatency_1_.\_zz_1_' from process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'. +No latch inferred for signal `\StreamFork.\io_input_ready' from process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'. +No latch inferred for signal `\StreamFifo.\_zz_1_' from process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'. +No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'. +No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'. +No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'. +No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'. +No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'. +No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'. +No latch inferred for signal `\StreamFifoLowLatency.\_zz_1_' from process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'. +No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'. +No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'. +No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'. +No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'. +No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'. +No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'. + +2.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'. + created $dff cell `$procdff$3812' with positive edge clock. +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. + created $dff cell `$procdff$3813' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. + created $dff cell `$procdff$3814' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$1469_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. + created $dff cell `$procdff$3815' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. + created $dff cell `$procdff$3816' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. + created $dff cell `$procdff$3817' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$1412_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. + created $dff cell `$procdff$3818' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'. + created direct connection (no actual register cell created). +Creating register for signal `\PQVexRiscvUlx3s.\_zz_35_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'. + created $adff cell `$procdff$3819' with positive edge clock and positive level reset. +Creating register for signal `\PQVexRiscvUlx3s.\core_cpu_debug_resetOut_regNext' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'. + created $dff cell `$procdff$3820' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_6_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3821' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_7_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3822' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_8_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3823' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_9_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3824' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_12_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3825' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_13_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3826' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_14_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3827' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_15_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3828' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_25_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3829' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_26_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3830' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_27_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3831' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_28_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3832' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_31_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3833' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_32_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3834' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_33_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3835' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_34_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. + created $dff cell `$procdff$3836' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_5_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. + created $adff cell `$procdff$3837' with positive edge clock and positive level reset. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_11_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. + created $adff cell `$procdff$3838' with positive edge clock and positive level reset. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_24_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. + created $adff cell `$procdff$3839' with positive edge clock and positive level reset. +Creating register for signal `\PQVexRiscvUlx3s.\_zz_30_' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. + created $adff cell `$procdff$3840' with positive edge clock and positive level reset. +Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_systemClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'. + created $dff cell `$procdff$3841' with positive edge clock. +Creating register for signal `\PQVexRiscvUlx3s.\resetCtrl_mainClockReset' using process `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'. + created $dff cell `$procdff$3842' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'. + created $dff cell `$procdff$3843' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'. + created $dff cell `$procdff$3844' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder_1_.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'. + created $adff cell `$procdff$3845' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_0' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. + created $dff cell `$procdff$3846' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_1' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. + created $dff cell `$procdff$3847' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspHits_2' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. + created $dff cell `$procdff$3848' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusDecoder.\logic_rspPendingCounter' using process `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'. + created $adff cell `$procdff$3849' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_1_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'. + created $adff cell `$procdff$3850' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3851' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3852' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3853' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3854' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3855' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3856' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3857' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3858' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3859' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_ADDR' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3860' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3861' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. + created $dff cell `$procdff$3862' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_5_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. + created $dff cell `$procdff$3863' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_6_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. + created $dff cell `$procdff$3864' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_7_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. + created $dff cell `$procdff$3865' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusRamUlx3s.\_zz_8_' using process `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. + created $dff cell `$procdff$3866' with positive edge clock. +Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'. + created $dff cell `$procdff$3867' with positive edge clock. +Creating register for signal `\MyMem.\myReg' using process `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'. + created $dff cell `$procdff$3868' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\_zz_1_' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. + created $dff cell `$procdff$3869' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerA_io_limit_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. + created $dff cell `$procdff$3870' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerB_io_limit_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. + created $dff cell `$procdff$3871' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerABridge_ticksEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + created $adff cell `$procdff$3872' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerABridge_clearsEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + created $adff cell `$procdff$3873' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerBBridge_ticksEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + created $adff cell `$procdff$3874' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerBBridge_clearsEnable' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + created $adff cell `$procdff$3875' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\interruptCtrl_1__io_masks_driver' using process `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. + created $adff cell `$procdff$3876' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\uartCtrl_1__io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'. + created $dff cell `$procdff$3877' with positive edge clock. +Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3878' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3879' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3880' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3881' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3882' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. + created $adff cell `$procdff$3883' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'. + created $dff cell `$procdff$3884' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. + created $adff cell `$procdff$3885' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. + created $adff cell `$procdff$3886' with positive edge clock and positive level reset. +Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'. + created $dff cell `$procdff$3887' with positive edge clock. +Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'. + created $dff cell `$procdff$3888' with positive edge clock. +Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. + created $adff cell `$procdff$3889' with positive edge clock and positive level reset. +Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. + created $adff cell `$procdff$3890' with positive edge clock and positive level reset. +Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. + created $adff cell `$procdff$3891' with positive edge clock and positive level reset. +Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'. + created $dff cell `$procdff$3892' with negative edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3893' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3894' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3895' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3896' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3897' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_readArea_shifter' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. + created $dff cell `$procdff$3898' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. + created $dff cell `$procdff$3899' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. + created $dff cell `$procdff$3900' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. + created $dff cell `$procdff$3901' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3902' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3903' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3904' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3905' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3906' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3907' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3908' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. + created $adff cell `$procdff$3909' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3910' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3911' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3912' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_0_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3913' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_1_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3914' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_hardwareBreakpoints_2_pc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3915' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3916' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_124_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3917' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. + created $dff cell `$procdff$3918' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_58_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3919' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_60_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3920' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_61_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3921' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_62_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3922' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_63_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3923' with positive edge clock. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3924' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3925' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3926' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3927' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3928' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3929' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3930' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3931' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3932' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3933' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3934' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3935' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_102_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3936' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3937' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_rs2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3938' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_accumulator' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3939' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_needRevert' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3940' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_done' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3941' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_result' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3942' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3943' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3944' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3945' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3946' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3947' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3948' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3949' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3950' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3951' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3952' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3953' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3954' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3955' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3956' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3957' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3958' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3959' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3960' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3961' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3962' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3963' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3964' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3965' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3966' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3967' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3968' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3969' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_SRC2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3970' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3971' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3972' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3973' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3974' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3975' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3976' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3977' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3978' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3979' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3980' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3981' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3982' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3983' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3984' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3985' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3986' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3987' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3988' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3989' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3990' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3991' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3992' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3993' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3994' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3995' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3996' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3997' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3998' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$3999' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4000' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4001' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4002' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4003' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4004' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4005' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4006' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4007' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4008' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4009' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2816' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4010' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2944' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4011' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2818' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4012' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_2946' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. + created $dff cell `$procdff$4013' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4014' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4015' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4016' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4017' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4018' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4019' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4020' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_55_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4021' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_57_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4022' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_59_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4023' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4024' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4025' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4026' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4027' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4028' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4029' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4030' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4031' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4032' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4033' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4034' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4035' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4036' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4037' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4038' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4039' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4040' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4041' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4042' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4043' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4044' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4045' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_88_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4046' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_100_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4047' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\memory_MulDivIterativePlugin_div_counter_value' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4048' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4049' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4050' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_125_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. + created $adff cell `$procdff$4051' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_ADDR' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. + created $dff cell `$procdff$4052' with positive edge clock. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_DATA' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. + created $dff cell `$procdff$4053' with positive edge clock. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. + created $dff cell `$procdff$4054' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_138_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'. + created $dff cell `$procdff$4055' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_137_' using process `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'. + created $dff cell `$procdff$4056' with positive edge clock. +Creating register for signal `\BufferCC_2_.\buffers_0' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'. + created $dff cell `$procdff$4057' with positive edge clock. +Creating register for signal `\BufferCC_2_.\buffers_1' using process `\BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'. + created $dff cell `$procdff$4058' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency_1_.\risingOccupancy' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. + created $adff cell `$procdff$4059' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifoLowLatency_1_.\pushPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. + created $adff cell `$procdff$4060' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifoLowLatency_1_.\popPtr_value' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. + created $adff cell `$procdff$4061' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_ADDR' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. + created $dff cell `$procdff$4062' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_DATA' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. + created $dff cell `$procdff$4063' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency_1_.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN' using process `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. + created $dff cell `$procdff$4064' with positive edge clock. +Creating register for signal `\StreamFork.\_zz_2_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. + created $adff cell `$procdff$4065' with positive edge clock and positive level reset. +Creating register for signal `\StreamFork.\_zz_1_' using process `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. + created $adff cell `$procdff$4066' with positive edge clock and positive level reset. +Creating register for signal `\StreamArbiter.\maskLocked_0' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'. + created $dff cell `$procdff$4067' with positive edge clock. +Creating register for signal `\StreamArbiter.\maskLocked_1' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'. + created $dff cell `$procdff$4068' with positive edge clock. +Creating register for signal `\StreamArbiter.\locked' using process `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'. + created $adff cell `$procdff$4069' with positive edge clock and positive level reset. +Creating register for signal `\InterruptCtrl.\pendings' using process `\InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'. + created $adff cell `$procdff$4070' with positive edge clock and positive level reset. +Creating register for signal `\Timer.\counter' using process `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'. + created $dff cell `$procdff$4071' with positive edge clock. +Creating register for signal `\Timer.\inhibitFull' using process `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'. + created $adff cell `$procdff$4072' with positive edge clock and positive level reset. +Creating register for signal `\Prescaler.\counter' using process `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'. + created $dff cell `$procdff$4073' with positive edge clock. +Creating register for signal `\StreamFifo.\_zz_2_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. + created $adff cell `$procdff$4074' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. + created $adff cell `$procdff$4075' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. + created $adff cell `$procdff$4076' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. + created $adff cell `$procdff$4077' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_ADDR' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. + created $dff cell `$procdff$4078' with positive edge clock. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_DATA' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. + created $dff cell `$procdff$4079' with positive edge clock. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. + created $dff cell `$procdff$4080' with positive edge clock. +Creating register for signal `\StreamFifo.\_zz_3_' using process `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'. + created $dff cell `$procdff$4081' with positive edge clock. +Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'. + created $adff cell `$procdff$4082' with positive edge clock and positive level reset. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_valid' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'. + created $adff cell `$procdff$4083' with positive edge clock and positive level reset. +Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'. + created $dff cell `$procdff$4084' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'. + created $dff cell `$procdff$4085' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_regNext_payload_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'. + created $dff cell `$procdff$4086' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. + created $dff cell `$procdff$4087' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. + created $dff cell `$procdff$4088' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. + created $dff cell `$procdff$4089' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency.\_zz_3_' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'. + created $dff cell `$procdff$4090' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'. + created $adff cell `$procdff$4091' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4092' with positive edge clock. +Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4093' with positive edge clock. +Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4094' with positive edge clock. +Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4095' with positive edge clock. +Creating register for signal `\UartCtrlRx.$bitselwrite$mask$PQVexRiscvUlx3s.v:580$27' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4096' with positive edge clock. +Creating register for signal `\UartCtrlRx.$bitselwrite$data$PQVexRiscvUlx3s.v:580$28' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4097' with positive edge clock. +Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$60' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. + created $dff cell `$procdff$4098' with positive edge clock. +Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4099' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\_zz_1_' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4100' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4101' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4102' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4103' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4104' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4105' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. + created $adff cell `$procdff$4106' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'. + created $dff cell `$procdff$4107' with positive edge clock. +Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'. + created $dff cell `$procdff$4108' with positive edge clock. +Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. + created $adff cell `$procdff$4109' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. + created $adff cell `$procdff$4110' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlTx.\_zz_1_' using process `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. + created $adff cell `$procdff$4111' with positive edge clock and positive level reset. +Creating register for signal `\BufferCC_1_.\buffers_0' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'. + created $dff cell `$procdff$4112' with positive edge clock. +Creating register for signal `\BufferCC_1_.\buffers_1' using process `\BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'. + created $dff cell `$procdff$4113' with positive edge clock. +Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'. +Warning: Async reset value `\io_initial' is not constant! + created $dffsr cell `$procdff$4114' with positive edge clock and positive level non-const reset. +Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'. +Warning: Async reset value `\io_initial' is not constant! + created $dffsr cell `$procdff$4121' with positive edge clock and positive level non-const reset. + +2.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1498'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'. +Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$1494'. +Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1491'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. +Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$1470'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$1436'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$1414'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$1413'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8216$1266'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8212$1265'. +Found and cleaned up 4 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8185$1256'. +Found and cleaned up 6 empty switches in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8157$1253'. +Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8149$1252'. +Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8106$1246'. +Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8084$1241'. +Found and cleaned up 1 empty switch in `\PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'. +Removing empty process `PQVexRiscvUlx3s.$proc$PQVexRiscvUlx3s.v:8077$1240'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'. +Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7489$1233'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'. +Removing empty process `PipelinedMemoryBusArbiter_1_.$proc$PQVexRiscvUlx3s.v:7482$1232'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7314$1230'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7306$1228'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7294$1210'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7281$1206'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7268$1202'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'. +Removing empty process `PipelinedMemoryBusDecoder_1_.$proc$PQVexRiscvUlx3s.v:7256$1199'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7192$1193'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7184$1191'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7172$1170'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7159$1166'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7146$1162'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7133$1158'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'. +Removing empty process `PipelinedMemoryBusDecoder.$proc$PQVexRiscvUlx3s.v:7118$1155'. +Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7042$1143'. +Found and cleaned up 4 empty switches in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. +Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7022$1121'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. +Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7013$1116'. +Removing empty process `PipelinedMemoryBusRamUlx3s.$proc$PQVexRiscvUlx3s.v:7010$1115'. +Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6978$1110'. +Found and cleaned up 1 empty switch in `\Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. +Removing empty process `Apb3Router.$proc$PQVexRiscvUlx3s.v:6938$1109'. +Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'. +Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6885$1108'. +Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'. +Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6877$1107'. +Removing empty process `Apb3Decoder.$proc$PQVexRiscvUlx3s.v:6871$1097'. +Found and cleaned up 2 empty switches in `\MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'. +Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6831$1094'. +Found and cleaned up 1 empty switch in `\MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'. +Removing empty process `MyMem.$proc$PQVexRiscvUlx3s.v:6815$1081'. +Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6759$1080'. +Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6715$1079'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6709$1077'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6680$1076'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6649$1070'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6620$1069'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6610$1068'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6579$1062'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6550$1061'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6540$1060'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6511$1059'. +Found and cleaned up 1 empty switch in `\MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'. +Removing empty process `MuraxApb3Timer.$proc$PQVexRiscvUlx3s.v:6469$1046'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:0$1043'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6383$1042'. +Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6323$1037'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6303$1036'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6286$1035'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6269$1034'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6252$1033'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6235$1032'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6215$1027'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6207$1026'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6200$1025'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6180$1024'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6176$1023'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'. +Removing empty process `Apb3UartCtrl.$proc$PQVexRiscvUlx3s.v:6144$1009'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5970$1005'. +Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5954$1004'. +Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5944$1001'. +Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$PQVexRiscvUlx3s.v:5930$999'. +Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'. +Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5875$995'. +Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. +Removing empty process `SystemDebugger.$proc$PQVexRiscvUlx3s.v:5849$991'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5544$986'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5799$985'. +Found and cleaned up 7 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5764$979'. +Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5753$977'. +Found and cleaned up 2 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5738$974'. +Found and cleaned up 5 empty switches in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5710$971'. +Found and cleaned up 1 empty switch in `\JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'. +Removing empty process `JtagBridge.$proc$PQVexRiscvUlx3s.v:5656$954'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2122$951'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2121$950'. +Found and cleaned up 17 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5432$946'. +Found and cleaned up 8 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5390$943'. +Found and cleaned up 90 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:5079$840'. +Found and cleaned up 61 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4817$790'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4808$781'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4801$780'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4794$779'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4787$778'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4779$777'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4771$776'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4762$775'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4753$774'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4744$773'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4725$772'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4657$718'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4646$716'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4623$715'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4618$713'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4599$703'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4590$700'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4581$699'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4564$694'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4550$693'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4521$688'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4499$687'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4475$686'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4460$685'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4441$682'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4429$675'. +Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4393$666'. +Found and cleaned up 10 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4365$664'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4330$663'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4294$660'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4285$656'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4268$655'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4245$654'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4221$653'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4203$652'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4189$651'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4175$647'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4166$645'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4130$624'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4116$608'. +Found and cleaned up 16 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4069$603'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4056$601'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4045$600'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4035$597'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4020$591'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:4006$590'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3986$589'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3957$586'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3939$583'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3923$581'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3908$580'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3898$570'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3874$561'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3839$549'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3818$543'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3792$525'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3774$519'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3765$517'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3758$516'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3750$514'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3739$510'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3732$508'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3725$507'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3709$506'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3699$505'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3692$504'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3681$502'. +Found and cleaned up 6 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3660$501'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3646$500'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3638$499'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3629$498'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3621$497'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3608$487'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3599$486'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3590$485'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3583$484'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3576$483'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3564$475'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3555$474'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3542$464'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3523$463'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3512$462'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3484$459'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3469$458'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3462$456'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3454$454'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3416$453'. +Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3385$451'. +Found and cleaned up 11 empty switches in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:3355$449'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2696$417'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2690$415'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'. +Removing empty process `VexRiscv.$proc$PQVexRiscvUlx3s.v:2684$413'. +Removing empty process `BufferCC_2_.$proc$PQVexRiscvUlx3s.v:1453$234'. +Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1421$231'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1413$227'. +Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1393$216'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1384$213'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1377$212'. +Found and cleaned up 2 empty switches in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1366$210'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1357$207'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1350$206'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1343$205'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. +Removing empty process `StreamFifoLowLatency_1_.$proc$PQVexRiscvUlx3s.v:1337$201'. +Found and cleaned up 3 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. +Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1270$195'. +Found and cleaned up 2 empty switches in `\StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'. +Removing empty process `StreamFork.$proc$PQVexRiscvUlx3s.v:1250$188'. +Found and cleaned up 1 empty switch in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'. +Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1215$187'. +Found and cleaned up 2 empty switches in `\StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'. +Removing empty process `StreamArbiter.$proc$PQVexRiscvUlx3s.v:1202$185'. +Removing empty process `InterruptCtrl.$proc$PQVexRiscvUlx3s.v:1138$167'. +Found and cleaned up 2 empty switches in `\Timer.$proc$PQVexRiscvUlx3s.v:1114$164'. +Removing empty process `Timer.$proc$PQVexRiscvUlx3s.v:1114$164'. +Found and cleaned up 2 empty switches in `\Timer.$proc$PQVexRiscvUlx3s.v:1101$163'. +Removing empty process `Timer.$proc$PQVexRiscvUlx3s.v:1101$163'. +Found and cleaned up 1 empty switch in `\Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'. +Removing empty process `Prescaler.$proc$PQVexRiscvUlx3s.v:1071$155'. +Found and cleaned up 2 empty switches in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1038$150'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1020$132'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1011$129'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:1004$128'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:997$126'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:988$123'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:981$122'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:974$121'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:968$117'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'. +Removing empty process `StreamFifo.$proc$PQVexRiscvUlx3s.v:962$115'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'. +Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:899$111'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'. +Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:884$110'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'. +Removing empty process `UartCtrl.$proc$PQVexRiscvUlx3s.v:877$109'. +Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:741$107'. +Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:780$106'. +Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:774$105'. +Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. +Removing empty process `FlowCCByToggle.$proc$PQVexRiscvUlx3s.v:766$103'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:719$101'. +Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:706$99'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:697$97'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:689$96'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:680$95'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:665$87'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:658$86'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:649$84'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:642$83'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'. +Removing empty process `StreamFifoLowLatency.$proc$PQVexRiscvUlx3s.v:635$82'. +Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. +Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:553$61'. +Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. +Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:474$43'. +Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'. +Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:461$41'. +Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'. +Removing empty process `UartCtrlRx.$proc$PQVexRiscvUlx3s.v:431$39'. +Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:306$23'. +Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:260$14'. +Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:238$13'. +Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:219$11'. +Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:208$9'. +Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'. +Removing empty process `UartCtrlTx.$proc$PQVexRiscvUlx3s.v:198$6'. +Removing empty process `BufferCC_1_.$proc$PQVexRiscvUlx3s.v:120$2'. +Removing empty process `BufferCC.$proc$PQVexRiscvUlx3s.v:97$1'. +Cleaned up 579 empty switches. + +2.5. Executing FLATTEN pass (flatten design). +Deleting now unused module PipelinedMemoryBusArbiter_1_. +Deleting now unused module PipelinedMemoryBusArbiter. +Deleting now unused module PipelinedMemoryBusDecoder_1_. +Deleting now unused module PipelinedMemoryBusDecoder. +Deleting now unused module PipelinedMemoryBusRamUlx3s. +Deleting now unused module Apb3Router. +Deleting now unused module Apb3Decoder. +Deleting now unused module MyMem. +Deleting now unused module MuraxApb3Timer. +Deleting now unused module Apb3UartCtrl. +Deleting now unused module PipelinedMemoryBusToApbBridge. +Deleting now unused module SystemDebugger. +Deleting now unused module JtagBridge. +Deleting now unused module VexRiscv. +Deleting now unused module BufferCC_2_. +Deleting now unused module StreamFifoLowLatency_1_. +Deleting now unused module StreamFork. +Deleting now unused module StreamArbiter. +Deleting now unused module InterruptCtrl. +Deleting now unused module Timer. +Deleting now unused module Prescaler. +Deleting now unused module StreamFifo. +Deleting now unused module UartCtrl. +Deleting now unused module FlowCCByToggle. +Deleting now unused module StreamFifoLowLatency. +Deleting now unused module UartCtrlRx. +Deleting now unused module UartCtrlTx. +Deleting now unused module BufferCC_1_. +Deleting now unused module BufferCC. + + +2.6. Executing TRIBUF pass. + +2.7. Executing DEMINOUT pass (demote inout ports to input or output). + +2.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 299 unused cells and 2697 unused wires. + + +2.10. Executing CHECK pass (checking for obvious problems). +Checking module PQVexRiscvUlx3s... +Found and reported 0 problems. + +2.11. Executing OPT pass (performing simple optimizations). + +2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 175 cells. + +2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2009: \pipelinedMemoryBusToApbBridge_1_.state -> 1'1 + Replacing known input bits on port B of cell $flatten\systemDebugger_1_.$procmux$2050: \systemDebugger_1_.dispatcher_headerLoaded -> 1'1 + Replacing known input bits on port A of cell $flatten\systemDebugger_1_.$procmux$2048: \systemDebugger_1_.dispatcher_headerLoaded -> 1'0 + Analyzing evaluation results. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3560. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3685. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3694. + dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697. + dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697. + dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697. + dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3697. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1896. + dead port 1/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706. + dead port 2/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706. + dead port 3/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706. + dead port 4/5 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3706. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1905. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3716. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3718. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3724. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1914. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1923. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3783. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3785. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3792. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1932. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1943. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.$procmux$1962. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2711. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2713. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2722. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2750. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2752. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2761. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2779. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2805. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2808. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2814. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2827. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2829. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2835. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2845. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2847. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2853. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2871. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2884. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2886. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2892. + dead port 1/2 on $mux $flatten\core_cpu.$procmux$2902. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2904. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2910. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$2928. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3109. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3142. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3172. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3184. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3193. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3208. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3240. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3265. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3275. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3277. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3283. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3293. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3295. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3301. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3313. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3319. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3328. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3338. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3340. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3346. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3356. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3358. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3364. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3376. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3382. + dead port 2/2 on $mux $flatten\core_cpu.$procmux$3391. + dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2096. + dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2105. + dead port 2/2 on $mux $flatten\jtagBridge_1_.$procmux$2114. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1719. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1731. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1745. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1768. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1788. + dead port 2/2 on $mux $flatten\muraxApb3Timer_1_.$procmux$1817. + dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2018. + dead port 2/2 on $mux $flatten\pipelinedMemoryBusToApbBridge_1_.$procmux$2027. +Removed 85 multiplexer ports. + + +2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3503: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 + New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] + New connections: $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] } + New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2789: $auto$opt_reduce.cc:134:opt_mux$4129 + New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$2797: { $flatten\core_cpu.$procmux$2800_CMP $auto$opt_reduce.cc:134:opt_mux$4131 } + New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2874: { } + New ctrl vector for $mux cell $flatten\core_cpu.$procmux$2931: { } + New ctrl vector for $pmux cell $flatten\core_cpu.$procmux$3072: $auto$opt_reduce.cc:134:opt_mux$4133 + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3396: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 + New ports: A=1'0, B=1'1, Y=$flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] + New connections: $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [31:1] = { $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] $flatten\core_cpu.$0$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN[31:0]$420 [0] } + New ctrl vector for $pmux cell $flatten\apb3Router_1_.$procmux$1657: { } + Consolidated identical input bits for $mux cell $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3503: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 + New ports: A=1'0, B=1'1, Y=$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] + New connections: $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [7:1] = { $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$0$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN[7:0]$120 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1616: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] + New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1622: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] + New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1628: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] + New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0.$procmux$1634: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] + New connections: $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [7:1] = { $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_0.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3440: + Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0] + New connections: $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [1] = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0] + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1616: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] + New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN[7:0]$1124 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1622: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] + New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN[7:0]$1127 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1628: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] + New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN[7:0]$1130 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1.$procmux$1634: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] + New connections: $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [7:1] = { $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] $flatten\memory_ramBlocks_1.$0$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN[7:0]$1133 [0] } + Consolidated identical input bits for $mux cell $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3440: + Old ports: A=2'00, B=2'11, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 + New ports: A=1'0, B=1'1, Y=$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0] + New connections: $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [1] = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$0$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN[1:0]$204 [0] + New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3727: { $auto$opt_reduce.cc:134:opt_mux$4135 $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP } + New ctrl vector for $mux cell $flatten\io_apb_decoder.$procmux$1664: { } + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 21 changes. + +2.11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 31 cells. + +2.11.6. Executing OPT_DFF pass (perform DFF optimizations). +Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4121 ($dffsr) from module PQVexRiscvUlx3s. +Removing never-active SET on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.\io_rxd_buffercc.$procdff$4114 ($dffsr) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 0 on $flatten\core_cpu.$procdff$4044 ($adff) from module PQVexRiscvUlx3s. + +2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 2 unused cells and 318 unused wires. + + +2.11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.11.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. + New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3593: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP $auto$opt_reduce.cc:134:opt_mux$4137 } + New ctrl vector for $pmux cell $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3744: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP $auto$opt_reduce.cc:134:opt_mux$4139 } + New ctrl vector for $pmux cell $flatten\jtagBridge_1_.$procmux$2124: { $flatten\jtagBridge_1_.$procmux$2138_CMP $auto$opt_reduce.cc:134:opt_mux$4145 $flatten\jtagBridge_1_.$procmux$2135_CMP $flatten\jtagBridge_1_.$procmux$2134_CMP $flatten\jtagBridge_1_.$procmux$2133_CMP $flatten\jtagBridge_1_.$procmux$2131_CMP $auto$opt_reduce.cc:134:opt_mux$4143 $flatten\jtagBridge_1_.$procmux$2128_CMP $flatten\jtagBridge_1_.$procmux$2127_CMP $flatten\jtagBridge_1_.$procmux$2126_CMP $auto$opt_reduce.cc:134:opt_mux$4141 } + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 3 changes. + +2.11.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.11.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 0 unused cells and 4 unused wires. + + +2.11.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.11.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.11.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.11.20. Executing OPT_DFF pass (perform DFF optimizations). + +2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.11.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.11.23. Finished OPT passes. (There is nothing left to do.) + +2.12. Executing FSM pass (extract and optimize FSM). + +2.12.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:970$113_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2698$235_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:1339$198_EN as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s._zz_8_ as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s._zz_9_ as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state. +Found FSM state register PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state. +Not marking PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_code as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register PQVexRiscvUlx3s.core_cpu.CsrPlugin_interrupt_targetPrivilege. +Not marking PQVexRiscvUlx3s.core_cpu._zz_125_ as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking PQVexRiscvUlx3s.jtagBridge_1_.jtag_tap_fsm_state as FSM state register: + Register has an initialization value. + +2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state' from module `\PQVexRiscvUlx3s'. + found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4099 + root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] + found reset state: 3'000 (from async reset) + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ + found state code: 3'100 + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ + found state code: 3'010 + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ + found state code: 3'001 + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP + ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y } + ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP } + transition: 3'000 6'-0---- -> 3'000 7'0000001 + transition: 3'000 6'-1---- -> 3'001 7'0010001 + transition: 3'100 6'----0- -> 3'100 7'1000000 + transition: 3'100 6'---01- -> 3'000 7'0000000 + transition: 3'100 6'---110 -> 3'100 7'1000000 + transition: 3'100 6'---111 -> 3'000 7'0000000 + transition: 3'010 6'----0- -> 3'010 7'0101000 + transition: 3'010 6'--0-1- -> 3'010 7'0101000 + transition: 3'010 6'--1-1- -> 3'100 7'1001000 + transition: 3'001 6'----0- -> 3'001 7'0010010 + transition: 3'001 6'---01- -> 3'010 7'0100010 + transition: 3'001 6'---11- -> 3'000 7'0000010 +Extracting FSM `\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state' from module `\PQVexRiscvUlx3s'. + found $adff cell for state register: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procdff$4110 + root of input selection tree: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] + found reset state: 3'000 (from async reset) + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid + found state code: 3'001 + found state code: 3'100 + found ctrl input: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ + found state code: 3'010 + found ctrl input: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP + found ctrl output: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP + ctrl inputs: { \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y } + ctrl outputs: { $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP } + transition: 3'000 5'---0- -> 3'000 7'0000001 + transition: 3'000 5'---1- -> 3'001 7'0010001 + transition: 3'100 5'--0-- -> 3'100 7'1000000 + transition: 3'100 5'--1-0 -> 3'100 7'1000000 + transition: 3'100 5'0-1-1 -> 3'000 7'0000000 + transition: 3'100 5'1-1-1 -> 3'001 7'0010000 + transition: 3'010 5'--0-- -> 3'010 7'0100010 + transition: 3'010 5'-01-- -> 3'010 7'0100010 + transition: 3'010 5'-11-- -> 3'100 7'1000010 + transition: 3'001 5'--0-- -> 3'001 7'0011000 + transition: 3'001 5'--1-- -> 3'010 7'0101000 +Extracting FSM `\core_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\PQVexRiscvUlx3s'. + found $dff cell for state register: $flatten\core_cpu.$procdff$3934 + root of input selection tree: $flatten\core_cpu.$0\CsrPlugin_interrupt_targetPrivilege[1:0] + found ctrl input: \core_cpu.CsrPlugin_mstatus_MIE + found ctrl input: \core_cpu._zz_164_ + found ctrl input: \core_cpu._zz_163_ + found ctrl input: \core_cpu._zz_162_ + found state code: 2'11 + fsm extraction failed: at least two states are required. + +2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'. +Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'. + Removing unused input signal \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_3_. + +2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 30 unused cells and 30 unused wires. + + +2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [0]. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [1]. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\stateMachine_state[2:0] [2]. +Optimizing FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3776_CMP. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [0]. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [1]. + Removing unused output signal $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$0\stateMachine_state[2:0] [2]. + +2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ---1 + 100 -> --1- + 010 -> -1-- + 001 -> 1--- +Recoding FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ---1 + 100 -> --1- + 010 -> -1-- + 001 -> 1--- + +2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `PQVexRiscvUlx3s': +------------------------------------- + + Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146 (\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state): + + Number of input signals: 5 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$eq$PQVexRiscvUlx3s.v:543$59_Y + 1: \apb3UartCtrl_1_.uartCtrl_1_.rx.bitTimer_tick + 2: \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_value + 3: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_7_ + 4: \apb3UartCtrl_1_.uartCtrl_1_.rx._zz_6_ + + Output signals: + 0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3615_CMP + 1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3603_CMP + 2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3594_CMP + 3: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3561_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'0---- -> 0 4'0001 + 1: 0 5'1---- -> 3 4'0001 + 2: 1 5'--111 -> 0 4'0000 + 3: 1 5'--01- -> 0 4'0000 + 4: 1 5'--110 -> 1 4'0000 + 5: 1 5'---0- -> 1 4'0000 + 6: 2 5'-1-1- -> 1 4'1000 + 7: 2 5'---0- -> 2 4'1000 + 8: 2 5'-0-1- -> 2 4'1000 + 9: 3 5'--11- -> 0 4'0010 + 10: 3 5'--01- -> 2 4'0010 + 11: 3 5'---0- -> 3 4'0010 + +------------------------------------- + +FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `PQVexRiscvUlx3s': +------------------------------------- + + Information on FSM $fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152 (\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state): + + Number of input signals: 5 + Number of output signals: 3 + Number of state bits: 4 + + Input signals: + 0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$eq$PQVexRiscvUlx3s.v:296$19_Y + 1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$logic_and$PQVexRiscvUlx3s.v:269$17_Y + 2: \apb3UartCtrl_1_.uartCtrl_1_.tx.clockDivider_counter_willOverflow + 3: \apb3UartCtrl_1_.uartCtrl_1_.tx._zz_2_ + 4: \apb3UartCtrl_1_.uartCtrl_1_.tx.io_write_valid + + Output signals: + 0: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3750_CMP + 1: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3745_CMP + 2: $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3739_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'---0- -> 0 3'000 + 1: 0 5'---1- -> 3 3'000 + 2: 1 5'0-1-1 -> 0 3'000 + 3: 1 5'--1-0 -> 1 3'000 + 4: 1 5'--0-- -> 1 3'000 + 5: 1 5'1-1-1 -> 3 3'000 + 6: 2 5'-11-- -> 1 3'001 + 7: 2 5'--0-- -> 2 3'001 + 8: 2 5'-01-- -> 2 3'001 + 9: 3 5'--1-- -> 2 3'100 + 10: 3 5'--0-- -> 3 3'100 + +------------------------------------- + +2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_state$4146' from module `\PQVexRiscvUlx3s'. +Mapping FSM `$fsm$\apb3UartCtrl_1_.uartCtrl_1_.tx.stateMachine_state$4152' from module `\PQVexRiscvUlx3s'. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 5 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3627. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3627. + dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3629. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3629. + dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3631. + dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3714. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3714. + dead port 1/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3722. + dead port 2/2 on $mux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3722. + dead port 1/3 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3727. + dead port 1/4 on $pmux $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$procmux$3799. +Removed 11 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$3841 ($dff) from module PQVexRiscvUlx3s (D = \asyncReset_buffercc.buffers_1, Q = \resetCtrl_systemClockReset, rval = 1'1). +Adding EN signal on $procdff$3840 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8180$1255_Y, Q = \_zz_30_). +Adding EN signal on $procdff$3839 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_24_[0:0], Q = \_zz_24_). +Adding EN signal on $procdff$3838 ($adff) from module PQVexRiscvUlx3s (D = $logic_or$PQVexRiscvUlx3s.v:8171$1254_Y, Q = \_zz_11_). +Adding EN signal on $procdff$3837 ($adff) from module PQVexRiscvUlx3s (D = $0\_zz_5_[0:0], Q = \_zz_5_). +Adding EN signal on $procdff$3836 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8208$1264_Y, Q = \_zz_34_). +Adding EN signal on $procdff$3835 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8207$1263_Y, Q = \_zz_33_). +Adding EN signal on $procdff$3834 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8206$1262_Y, Q = \_zz_32_). +Adding EN signal on $procdff$3833 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8205$1261_Y, Q = \_zz_31_). +Adding EN signal on $procdff$3832 ($dff) from module PQVexRiscvUlx3s (D = \_zz_21_, Q = \_zz_28_). +Adding EN signal on $procdff$3831 ($dff) from module PQVexRiscvUlx3s (D = \_zz_20_, Q = \_zz_27_). +Adding EN signal on $procdff$3830 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB, Q = \_zz_26_). +Adding EN signal on $procdff$3829 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \_zz_25_). +Adding EN signal on $procdff$3828 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8196$1260_Y, Q = \_zz_15_). +Adding EN signal on $procdff$3827 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8195$1259_Y, Q = \_zz_14_). +Adding SRST signal on $auto$opt_dff.cc:764:run$4284 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_8_, Q = \_zz_14_, rval = 0). +Adding EN signal on $procdff$3826 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8194$1258_Y, Q = \_zz_13_). +Adding SRST signal on $auto$opt_dff.cc:764:run$4286 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_7_ [1:0], Q = \_zz_13_ [1:0], rval = 2'00). +Adding EN signal on $procdff$3825 ($dff) from module PQVexRiscvUlx3s (D = $ternary$PQVexRiscvUlx3s.v:8193$1257_Y, Q = \_zz_12_). +Adding SRST signal on $auto$opt_dff.cc:764:run$4288 ($dffe) from module PQVexRiscvUlx3s (D = \_zz_6_, Q = \_zz_12_, rval = 1'0). +Adding EN signal on $procdff$3824 ($dff) from module PQVexRiscvUlx3s (D = 4'xxxx, Q = \_zz_9_). +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4290 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $procdff$3823 ($dff) from module PQVexRiscvUlx3s (D = 0, Q = \_zz_8_). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4291 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $procdff$3822 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, Q = \_zz_7_). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4292 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4292 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $procdff$3821 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \_zz_6_). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4293 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\systemDebugger_1_.$procdff$3891 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$procmux$2044_Y, Q = \systemDebugger_1_.dispatcher_counter). +Adding EN signal on $flatten\systemDebugger_1_.$procdff$3890 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_headerLoaded[0:0], Q = \systemDebugger_1_.dispatcher_headerLoaded). +Adding EN signal on $flatten\systemDebugger_1_.$procdff$3889 ($adff) from module PQVexRiscvUlx3s (D = $flatten\systemDebugger_1_.$0\dispatcher_dataLoaded[0:0], Q = \systemDebugger_1_.dispatcher_dataLoaded). +Adding EN signal on $flatten\systemDebugger_1_.$procdff$3888 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_headerShifter [7:1] }, Q = \systemDebugger_1_.dispatcher_headerShifter). +Adding EN signal on $flatten\systemDebugger_1_.$procdff$3887 ($dff) from module PQVexRiscvUlx3s (D = { \jtagBridge_1_.flowCCByToggle_1_.outputArea_flow_regNext_payload_fragment \systemDebugger_1_.dispatcher_dataShifter [66:1] }, Q = \systemDebugger_1_.dispatcher_dataShifter). +Adding EN signal on $flatten\myMem_1_.$procdff$3868 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_, Q = \myMem_1_.myReg). +Adding EN signal on $flatten\muraxApb3Timer_1_.\timerB.$procdff$4072 ($adff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$0\inhibitFull[0:0], Q = \muraxApb3Timer_1_.timerB.inhibitFull). +Adding SRST signal on $flatten\muraxApb3Timer_1_.\timerB.$procdff$4071 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$procmux$3468_Y, Q = \muraxApb3Timer_1_.timerB.counter, rval = 16'0000000000000000). +Adding EN signal on $auto$opt_dff.cc:702:run$4323 ($sdff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165_Y, Q = \muraxApb3Timer_1_.timerB.counter). +Adding EN signal on $flatten\muraxApb3Timer_1_.\timerA.$procdff$4072 ($adff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$0\inhibitFull[0:0], Q = \muraxApb3Timer_1_.timerA.inhibitFull). +Adding SRST signal on $flatten\muraxApb3Timer_1_.\timerA.$procdff$4071 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$procmux$3468_Y, Q = \muraxApb3Timer_1_.timerA.counter, rval = 16'0000000000000000). +Adding EN signal on $auto$opt_dff.cc:702:run$4328 ($sdff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165_Y, Q = \muraxApb3Timer_1_.timerA.counter). +Adding SRST signal on $flatten\muraxApb3Timer_1_.\prescaler_1_.$procdff$4073 ($dff) from module PQVexRiscvUlx3s (D = $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156_Y, Q = \muraxApb3Timer_1_.prescaler_1_.counter, rval = 16'0000000000000000). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3876 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.interruptCtrl_1__io_masks_driver). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3875 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [16], Q = \muraxApb3Timer_1_.timerBBridge_clearsEnable). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3874 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.timerBBridge_ticksEnable). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3873 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [16], Q = \muraxApb3Timer_1_.timerABridge_clearsEnable). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3872 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1:0], Q = \muraxApb3Timer_1_.timerABridge_ticksEnable). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3871 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_.timerB_io_limit_driver). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3870 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_.timerA_io_limit_driver). +Adding EN signal on $flatten\muraxApb3Timer_1_.$procdff$3869 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:0], Q = \muraxApb3Timer_1_._zz_1_). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4059 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4066 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_1_). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procdff$4065 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.streamFork_2_._zz_2_). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4069 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.locked). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4068 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_1). +Adding EN signal on $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procdff$4067 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_1_io_bus_arbiter.logic_arbiter.maskLocked_0). +Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3866 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120_DATA, Q = \memory_ramBlocks_1._zz_8_). +Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3865 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119_DATA, Q = \memory_ramBlocks_1._zz_7_). +Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3864 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118_DATA, Q = \memory_ramBlocks_1._zz_6_). +Adding EN signal on $flatten\memory_ramBlocks_1.$procdff$3863 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117_DATA, Q = \memory_ramBlocks_1._zz_5_). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4059 ($adff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.pushing, Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.risingOccupancy). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4066 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_1_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_1_). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procdff$4065 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$0\_zz_2_[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.streamFork_2_._zz_2_). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4069 ($adff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$0\locked[0:0], Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.locked). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4068 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_1, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_1). +Adding EN signal on $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procdff$4067 ($dff) from module PQVexRiscvUlx3s (D = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskRouted_0, Q = \memory_ramBlocks_0_io_bus_arbiter.logic_arbiter.maskLocked_0). +Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3866 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120_DATA, Q = \memory_ramBlocks_0._zz_8_). +Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3865 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119_DATA, Q = \memory_ramBlocks_0._zz_7_). +Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3864 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118_DATA, Q = \memory_ramBlocks_0._zz_6_). +Adding EN signal on $flatten\memory_ramBlocks_0.$procdff$3863 ($dff) from module PQVexRiscvUlx3s (D = $flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117_DATA, Q = \memory_ramBlocks_0._zz_5_). +Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4089 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tdi, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_fragment). +Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4088 ($dff) from module PQVexRiscvUlx3s (D = \io_jtag_tms, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_data_last). +Adding EN signal on $flatten\jtagBridge_1_.\flowCCByToggle_1_.$procdff$4087 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.\flowCCByToggle_1_.$logic_not$PQVexRiscvUlx3s.v:768$104_Y, Q = \jtagBridge_1_.flowCCByToggle_1_.inputArea_target). +Adding EN signal on $flatten\jtagBridge_1_.$procdff$3901 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.DebugPlugin_busReadDataReg [31:5] \jtagBridge_1_.io_remote_rsp_payload_data [4:0] }, Q = \jtagBridge_1_.system_rsp_payload_data). +Adding EN signal on $flatten\jtagBridge_1_.$procdff$3900 ($dff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_payload_error). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4391 ($dffe) from module PQVexRiscvUlx3s. +Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3899 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2088_Y, Q = \jtagBridge_1_.system_rsp_valid, rval = 1'1). +Adding EN signal on $auto$opt_dff.cc:702:run$4392 ($sdff) from module PQVexRiscvUlx3s (D = 1'0, Q = \jtagBridge_1_.system_rsp_valid). +Adding EN signal on $flatten\jtagBridge_1_.$procdff$3898 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2066_Y, Q = \jtagBridge_1_.jtag_readArea_shifter). +Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3897 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2072_Y, Q = \jtagBridge_1_.jtag_idcodeArea_shifter, rval = 268443647). +Adding EN signal on $auto$opt_dff.cc:702:run$4399 ($sdff) from module PQVexRiscvUlx3s (D = { \io_jtag_tdi \jtagBridge_1_.jtag_idcodeArea_shifter [31:1] }, Q = \jtagBridge_1_.jtag_idcodeArea_shifter). +Adding EN signal on $flatten\jtagBridge_1_.$procdff$3895 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$0\jtag_tap_instructionShift[3:0], Q = \jtagBridge_1_.jtag_tap_instructionShift). +Adding SRST signal on $flatten\jtagBridge_1_.$procdff$3894 ($dff) from module PQVexRiscvUlx3s (D = $flatten\jtagBridge_1_.$procmux$2080_Y, Q = \jtagBridge_1_.jtag_tap_instruction, rval = 4'0001). +Adding EN signal on $auto$opt_dff.cc:702:run$4406 ($sdff) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_tap_instructionShift, Q = \jtagBridge_1_.jtag_tap_instruction). +Adding EN signal on $flatten\core_ibus_decoder.$procdff$3844 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_1, Q = \core_ibus_decoder.logic_rspHits_1). +Adding EN signal on $flatten\core_ibus_decoder.$procdff$3843 ($dff) from module PQVexRiscvUlx3s (D = \core_ibus_decoder.logic_hits_0, Q = \core_ibus_decoder.logic_rspHits_0). +Adding EN signal on $flatten\core_dbus_decoder.$procdff$3848 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_2, Q = \core_dbus_decoder.logic_rspHits_2). +Adding EN signal on $flatten\core_dbus_decoder.$procdff$3847 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_1, Q = \core_dbus_decoder.logic_rspHits_1). +Adding EN signal on $flatten\core_dbus_decoder.$procdff$3846 ($dff) from module PQVexRiscvUlx3s (D = \core_dbus_decoder.logic_hits_0, Q = \core_dbus_decoder.logic_rspHits_0). +Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4091 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.pushing, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.risingOccupancy). +Adding EN signal on $flatten\core_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$procdff$4090 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_payload_inst 1'0 }, Q = \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c._zz_3_). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4414 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\core_cpu.$procdff$4051 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_125_[2:0], Q = \core_cpu._zz_125_). +Adding EN signal on $flatten\core_cpu.$procdff$4043 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_2). +Adding EN signal on $flatten\core_cpu.$procdff$4042 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_1). +Adding EN signal on $flatten\core_cpu.$procdff$4041 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \core_cpu.CsrPlugin_pipelineLiberator_pcValids_0). +Adding EN signal on $flatten\core_cpu.$procdff$4039 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mie_MSIE). +Adding EN signal on $flatten\core_cpu.$procdff$4038 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [7], Q = \core_cpu.CsrPlugin_mie_MTIE). +Adding EN signal on $flatten\core_cpu.$procdff$4037 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [11], Q = \core_cpu.CsrPlugin_mie_MEIE). +Adding EN signal on $flatten\core_cpu.$procdff$4033 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [31:2], Q = \core_cpu.CsrPlugin_mtvec_base). +Adding EN signal on $flatten\core_cpu.$procdff$4032 ($adff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [1:0], Q = \core_cpu.CsrPlugin_mtvec_mode). +Adding EN signal on $flatten\core_cpu.$procdff$4023 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_59_[0:0], Q = \core_cpu._zz_59_). +Adding EN signal on $flatten\core_cpu.$procdff$4022 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_57_[0:0], Q = \core_cpu._zz_57_). +Adding EN signal on $flatten\core_cpu.$procdff$4021 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\_zz_55_[0:0], Q = \core_cpu._zz_55_). +Adding EN signal on $flatten\core_cpu.$procdff$4020 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \core_cpu.IBusSimplePlugin_fetchPc_inc). +Adding EN signal on $flatten\core_cpu.$procdff$4017 ($adff) from module PQVexRiscvUlx3s (D = { \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \core_cpu.IBusSimplePlugin_fetchPc_pcReg). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4468 ($adffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4468 ($adffe) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\core_cpu.$procdff$4015 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_arbitration_isValid[0:0], Q = \core_cpu.memory_arbitration_isValid). +Adding EN signal on $flatten\core_cpu.$procdff$4014 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\execute_arbitration_isValid[0:0], Q = \core_cpu.execute_arbitration_isValid). +Adding EN signal on $flatten\core_cpu.$procdff$4013 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5381$942_Y, Q = \core_cpu.execute_CsrPlugin_csr_2946). +Adding EN signal on $flatten\core_cpu.$procdff$4012 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5378$940_Y, Q = \core_cpu.execute_CsrPlugin_csr_2818). +Adding EN signal on $flatten\core_cpu.$procdff$4011 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5375$938_Y, Q = \core_cpu.execute_CsrPlugin_csr_2944). +Adding EN signal on $flatten\core_cpu.$procdff$4010 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5372$936_Y, Q = \core_cpu.execute_CsrPlugin_csr_2816). +Adding EN signal on $flatten\core_cpu.$procdff$4009 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5369$934_Y, Q = \core_cpu.execute_CsrPlugin_csr_834). +Adding EN signal on $flatten\core_cpu.$procdff$4008 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5366$932_Y, Q = \core_cpu.execute_CsrPlugin_csr_773). +Adding EN signal on $flatten\core_cpu.$procdff$4007 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5363$930_Y, Q = \core_cpu.execute_CsrPlugin_csr_772). +Adding EN signal on $flatten\core_cpu.$procdff$4006 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5360$928_Y, Q = \core_cpu.execute_CsrPlugin_csr_836). +Adding EN signal on $flatten\core_cpu.$procdff$4005 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5357$926_Y, Q = \core_cpu.execute_CsrPlugin_csr_768). +Adding EN signal on $flatten\core_cpu.$procdff$4004 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_29_, Q = \core_cpu.decode_to_execute_RS1). +Adding EN signal on $flatten\core_cpu.$procdff$4002 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_ENABLE, Q = \core_cpu.execute_to_memory_MEMORY_ENABLE). +Adding EN signal on $flatten\core_cpu.$procdff$4001 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_ENABLE, Q = \core_cpu.decode_to_execute_MEMORY_ENABLE). +Adding EN signal on $flatten\core_cpu.$procdff$4000 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_BRANCH_DO, Q = \core_cpu.execute_to_memory_BRANCH_DO). +Adding EN signal on $flatten\core_cpu.$procdff$3999 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS2_SIGNED). +Adding EN signal on $flatten\core_cpu.$procdff$3998 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HH, Q = \core_cpu.execute_to_memory_MUL_HH). +Adding EN signal on $flatten\core_cpu.$procdff$3994 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_252_ \core_cpu._zz_253_ }, Q = \core_cpu.decode_to_execute_ALU_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3993 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_CSR, Q = \core_cpu.decode_to_execute_IS_CSR). +Adding EN signal on $flatten\core_cpu.$procdff$3992 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_387_ \core_cpu._zz_388_ }, Q = \core_cpu.decode_to_execute_ALU_BITWISE_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3991 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2_FORCE_ZERO, Q = \core_cpu.decode_to_execute_SRC2_FORCE_ZERO). +Adding EN signal on $flatten\core_cpu.$procdff$3990 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_DIV, Q = \core_cpu.execute_to_memory_IS_DIV). +Adding EN signal on $flatten\core_cpu.$procdff$3989 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_DIV, Q = \core_cpu.decode_to_execute_IS_DIV). +Adding EN signal on $flatten\core_cpu.$procdff$3988 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LH, Q = \core_cpu.execute_to_memory_MUL_LH). +Adding EN signal on $flatten\core_cpu.$procdff$3986 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_MEMORY_STORE, Q = \core_cpu.execute_to_memory_MEMORY_STORE). +Adding EN signal on $flatten\core_cpu.$procdff$3985 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_MEMORY_STORE, Q = \core_cpu.decode_to_execute_MEMORY_STORE). +Adding EN signal on $flatten\core_cpu.$procdff$3984 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_HL, Q = \core_cpu.execute_to_memory_MUL_HL). +Adding EN signal on $flatten\core_cpu.$procdff$3982 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_VALID). +Adding EN signal on $flatten\core_cpu.$procdff$3981 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_REGFILE_WRITE_VALID, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID). +Adding SRST signal on $auto$opt_dff.cc:764:run$4501 ($dffe) from module PQVexRiscvUlx3s (D = \core_cpu._zz_191_, Q = \core_cpu.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0). +Adding EN signal on $flatten\core_cpu.$procdff$3980 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \core_cpu.execute_to_memory_BRANCH_CALC). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4503 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\core_cpu.$procdff$3979 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_CSR_WRITE_OPCODE, Q = \core_cpu.decode_to_execute_CSR_WRITE_OPCODE). +Adding EN signal on $flatten\core_cpu.$procdff$3978 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_173_ [31:0], Q = \core_cpu.execute_to_memory_SHIFT_RIGHT). +Adding EN signal on $flatten\core_cpu.$procdff$3975 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.decode_to_execute_PC). +Adding EN signal on $flatten\core_cpu.$procdff$3974 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_RS1_SIGNED, Q = \core_cpu.decode_to_execute_IS_RS1_SIGNED). +Adding EN signal on $flatten\core_cpu.$procdff$3973 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_EXECUTE_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_EXECUTE_STAGE). +Adding EN signal on $flatten\core_cpu.$procdff$3972 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_USE_SUB_LESS, Q = \core_cpu.decode_to_execute_SRC_USE_SUB_LESS). +Adding EN signal on $flatten\core_cpu.$procdff$3969 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC2, Q = \core_cpu.execute_to_memory_SRC2). +Adding EN signal on $flatten\core_cpu.$procdff$3968 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC2, Q = \core_cpu.decode_to_execute_SRC2). +Adding EN signal on $flatten\core_cpu.$procdff$3967 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_INSTRUCTION, Q = \core_cpu.execute_to_memory_INSTRUCTION). +Adding EN signal on $flatten\core_cpu.$procdff$3966 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_62_, Q = \core_cpu.decode_to_execute_INSTRUCTION). +Adding EN signal on $flatten\core_cpu.$procdff$3964 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_IS_MUL, Q = \core_cpu.execute_to_memory_IS_MUL). +Adding EN signal on $flatten\core_cpu.$procdff$3963 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_IS_MUL, Q = \core_cpu.decode_to_execute_IS_MUL). +Adding EN signal on $flatten\core_cpu.$procdff$3962 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.execute_to_memory_BYPASSABLE_MEMORY_STAGE). +Adding EN signal on $flatten\core_cpu.$procdff$3961 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_BYPASSABLE_MEMORY_STAGE, Q = \core_cpu.decode_to_execute_BYPASSABLE_MEMORY_STAGE). +Adding EN signal on $flatten\core_cpu.$procdff$3960 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_255_ \core_cpu._zz_256_ }, Q = \core_cpu.decode_to_execute_BRANCH_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3959 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_DO_EBREAK, Q = \core_cpu.decode_to_execute_DO_EBREAK). +Adding EN signal on $flatten\core_cpu.$procdff$3957 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SRC1, Q = \core_cpu.execute_to_memory_SRC1). +Adding EN signal on $flatten\core_cpu.$procdff$3956 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC1, Q = \core_cpu.decode_to_execute_SRC1). +Adding EN signal on $flatten\core_cpu.$procdff$3955 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_SRC_LESS_UNSIGNED, Q = \core_cpu.decode_to_execute_SRC_LESS_UNSIGNED). +Adding EN signal on $flatten\core_cpu.$procdff$3953 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_SRC_ADD_SUB [1:0], Q = \core_cpu.execute_to_memory_MEMORY_ADDRESS_LOW). +Adding EN signal on $flatten\core_cpu.$procdff$3950 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_27_, Q = \core_cpu.decode_to_execute_RS2). +Adding EN signal on $flatten\core_cpu.$procdff$3949 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_43_, Q = \core_cpu.execute_to_memory_REGFILE_WRITE_DATA). +Adding EN signal on $flatten\core_cpu.$procdff$3948 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_SHIFT_CTRL, Q = \core_cpu.execute_to_memory_SHIFT_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3947 ($dff) from module PQVexRiscvUlx3s (D = { \core_cpu._zz_277_ \core_cpu._zz_13_ [0] }, Q = \core_cpu.decode_to_execute_SHIFT_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3945 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.decode_to_execute_ENV_CTRL, Q = \core_cpu.execute_to_memory_ENV_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3944 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_20_, Q = \core_cpu.decode_to_execute_ENV_CTRL). +Adding EN signal on $flatten\core_cpu.$procdff$3943 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_MUL_LL, Q = \core_cpu.execute_to_memory_MUL_LL). +Adding EN signal on $flatten\core_cpu.$procdff$3942 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_228_ [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_div_result). +Adding SRST signal on $flatten\core_cpu.$procdff$3941 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2417_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_done, rval = 1'0). +Adding EN signal on $auto$opt_dff.cc:702:run$4536 ($sdff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.memory_MulDivIterativePlugin_div_done). +Adding EN signal on $flatten\core_cpu.$procdff$3940 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$logic_and$PQVexRiscvUlx3s.v:5165$861_Y, Q = \core_cpu.memory_MulDivIterativePlugin_div_needRevert). +Adding SRST signal on $flatten\core_cpu.$procdff$3939 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2263_Y, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0], rval = 0). +Adding EN signal on $flatten\core_cpu.$procdff$3939 ($dff) from module PQVexRiscvUlx3s (D = 33'000000000000000000000000000000000, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [64:32]). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$4540 ($dffe) from module PQVexRiscvUlx3s. +Adding EN signal on $auto$opt_dff.cc:702:run$4539 ($sdff) from module PQVexRiscvUlx3s (D = \core_cpu.memory_MulDivIterativePlugin_div_stage_0_outRemainder, Q = \core_cpu.memory_MulDivIterativePlugin_accumulator [31:0]). +Adding EN signal on $flatten\core_cpu.$procdff$3938 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852_Y, Q = \core_cpu.memory_MulDivIterativePlugin_rs2). +Adding EN signal on $flatten\core_cpu.$procdff$3937 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849_Y [32], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [32]). +Adding EN signal on $flatten\core_cpu.$procdff$3937 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0] [31:0], Q = \core_cpu.memory_MulDivIterativePlugin_rs1 [31:0]). +Adding EN signal on $flatten\core_cpu.$procdff$3934 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2439_Y, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege). +Adding SRST signal on $auto$opt_dff.cc:764:run$4559 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_targetPrivilege, rval = 2'11). +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4562 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4562 ($sdffce) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\core_cpu.$procdff$3933 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2447_Y, Q = \core_cpu.CsrPlugin_interrupt_code). +Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2445_Y [3], Q = \core_cpu.CsrPlugin_interrupt_code [3], rval = 1'1). +Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2443_Y [2], Q = \core_cpu.CsrPlugin_interrupt_code [2], rval = 1'0). +Adding SRST signal on $auto$opt_dff.cc:764:run$4567 ($dffe) from module PQVexRiscvUlx3s (D = 2'xx, Q = \core_cpu.CsrPlugin_interrupt_code [1:0], rval = 2'11). +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:702:run$4574 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 1 on $auto$opt_dff.cc:702:run$4574 ($sdffce) from module PQVexRiscvUlx3s. +Adding EN signal on $flatten\core_cpu.$procdff$3932 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842_Y, Q = \core_cpu.CsrPlugin_minstret). +Adding EN signal on $flatten\core_cpu.$procdff$3930 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.CsrPlugin_interrupt_code, Q = \core_cpu.CsrPlugin_mcause_exceptionCode). +Adding EN signal on $flatten\core_cpu.$procdff$3929 ($dff) from module PQVexRiscvUlx3s (D = 1'1, Q = \core_cpu.CsrPlugin_mcause_interrupt). +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4581 ($dffe) from module PQVexRiscvUlx3s. +Adding SRST signal on $flatten\core_cpu.$procdff$3928 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.execute_CsrPlugin_writeData [3], Q = \core_cpu.CsrPlugin_mip_MSIP, rval = 1'0). +Adding EN signal on $flatten\core_cpu.$procdff$3925 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_60_, Q = \core_cpu.CsrPlugin_mepc). +Adding EN signal on $flatten\core_cpu.$procdff$3922 ($dff) from module PQVexRiscvUlx3s (D = { $flatten\core_cpu.$0\_zz_62_[31:0] [31:25] $flatten\core_cpu.$0\_zz_62_[31:0] [14:0] }, Q = { \core_cpu._zz_62_ [31:25] \core_cpu._zz_62_ [14:0] }). +Adding EN signal on $flatten\core_cpu.$procdff$3920 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu._zz_58_, Q = \core_cpu._zz_60_). +Adding EN signal on $flatten\core_cpu.$procdff$3919 ($dff) from module PQVexRiscvUlx3s (D = \core_cpu.IBusSimplePlugin_fetchPc_pcReg, Q = \core_cpu._zz_58_). +Adding EN signal on $flatten\core_cpu.$procdff$3916 ($dff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$0\DebugPlugin_busReadDataReg[31:0], Q = \core_cpu.DebugPlugin_busReadDataReg). +Adding EN signal on $flatten\core_cpu.$procdff$3915 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_pc). +Adding EN signal on $flatten\core_cpu.$procdff$3914 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_pc). +Adding EN signal on $flatten\core_cpu.$procdff$3913 ($dff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [63:33], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_pc). +Adding EN signal on $flatten\core_cpu.$procdff$3909 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_2_valid). +Adding EN signal on $flatten\core_cpu.$procdff$3908 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_1_valid). +Adding EN signal on $flatten\core_cpu.$procdff$3907 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [32], Q = \core_cpu.DebugPlugin_hardwareBreakpoints_0_valid). +Adding EN signal on $flatten\core_cpu.$procdff$3904 ($adff) from module PQVexRiscvUlx3s (D = \systemDebugger_1_.dispatcher_dataShifter [36], Q = \core_cpu.DebugPlugin_stepIt). +Adding EN signal on $flatten\core_cpu.$procdff$3902 ($adff) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2224_Y, Q = \core_cpu.DebugPlugin_resetIt). +Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4077 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_risingOccupancy). +Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4105 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$0\break_counter[6:0], Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.break_counter). +Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4102 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_2). +Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4101 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.uartCtrl_1_.rx.io_rxd_buffercc.buffers_1, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.sampler_samples_1). +Adding EN signal on $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procdff$4095 ($dff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$or$PQVexRiscvUlx3s.v:0$80_Y, Q = \apb3UartCtrl_1_.uartCtrl_1_.rx.stateMachine_shifter). +Adding EN signal on $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4077 ($adff) from module PQVexRiscvUlx3s (D = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pushing, Q = \apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_risingOccupancy). +Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3881 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readOverflowError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readOverflowError). +Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3880 ($adff) from module PQVexRiscvUlx3s (D = $flatten\apb3UartCtrl_1_.$0\bridge_misc_readError[0:0], Q = \apb3UartCtrl_1_.bridge_misc_readError). +Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3879 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [1], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_readIntEnable). +Adding EN signal on $flatten\apb3UartCtrl_1_.$procdff$3878 ($adff) from module PQVexRiscvUlx3s (D = \_zz_33_ [0], Q = \apb3UartCtrl_1_.bridge_interruptCtrl_writeIntEnable). + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 230 unused cells and 258 unused wires. + + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 15 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4592 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4592 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4578 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4578 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4289 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4287 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4287 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 30 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 31 on $auto$opt_dff.cc:702:run$4285 ($sdffce) from module PQVexRiscvUlx3s. + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 0 unused cells and 23 unused wires. + + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.13.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.13.20. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4591 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4591 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 1 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 2 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 1-bit at position 3 on $auto$opt_dff.cc:764:run$4283 ($dffe) from module PQVexRiscvUlx3s. + +2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 0 unused cells and 3 unused wires. + + +2.13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.13.23. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.13.27. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4587 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4587 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$4506 ($dffe) from module PQVexRiscvUlx3s. +Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$4506 ($dffe) from module PQVexRiscvUlx3s. + +2.13.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.13.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.13.30. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.13.34. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$opt_dff.cc:764:run$4595 ($dffe) from module PQVexRiscvUlx3s (D = $flatten\core_cpu.$procmux$2234_Y [1:0], Q = \core_cpu.DebugPlugin_busReadDataReg [1:0], rval = 2'00). + +2.13.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.13.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.13.37. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.13.40. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.13.41. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.13.43. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.13.44. Finished OPT passes. (There is nothing left to do.) + +2.14. Executing WREDUCE pass (reducing word size of cells). +Removed cell PQVexRiscvUlx3s.$procmux$1550 ($mux). +Removed cell PQVexRiscvUlx3s.$procmux$1556 ($mux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4551 ($ne). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4457 ($ne). +Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4219 ($eq). +Removed top 31 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4054 ($dff). +Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$flatten\core_cpu.$procdff$4050 ($adff). +Removed top 2 bits (of 32) from FF cell PQVexRiscvUlx3s.$auto$opt_dff.cc:764:run$4512 ($dffe). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3400 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3398 ($mux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3264_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3062_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$3055_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2952_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2948_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2943_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2939_CMP0 ($eq). +Removed top 12 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2793 ($pmux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2787_CMP0 ($eq). +Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2712_CMP0 ($eq). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2645 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2641 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2625 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2617 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2613 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2519 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2517 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2513 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2511 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2507 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2498 ($mux). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2497_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2496_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2495_CMP0 ($eq). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2493 ($mux). +Removed top 7 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2469 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2443 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2425 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2423 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2234 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2222 ($mux). +Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2158_CMP0 ($eq). +Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2150_CMP0 ($eq). +Removed top 1 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$procmux$2143_CMP0 ($eq). +Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5369$934 ($eq). +Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5366$932 ($eq). +Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5363$930 ($eq). +Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5360$928 ($eq). +Removed top 2 bits (of 12) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:5357$926 ($eq). +Removed top 31 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852 ($add). +Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add). +Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add). +Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add). +Removed top 1 bits (of 33) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:5163$848 ($mux). +Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5163$847 ($not). +Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:5163$847 ($not). +Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842 ($add). +Removed top 63 bits (of 64) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813 ($sub). +Removed top 20 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$783 ($or). +Removed top 19 bits (of 32) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or). +Removed top 20 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or). +Removed top 19 bits (of 32) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782 ($or). +Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705 ($sub). +Removed top 5 bits (of 6) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704 ($add). +Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add). +Removed top 1 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4432$677 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4329$661 ($eq). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4147$643 ($eq). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4147$642 ($and). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4146$638 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4146$637 ($and). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4144$634 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4144$633 ($and). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4143$632 ($eq). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4143$631 ($and). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:4142$630 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:4142$629 ($and). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550 ($sub). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518 ($add). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:3294$427 ($eq). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2683$412 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2682$410 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2682$409 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2680$408 ($and). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2678$407 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2672$402 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2670$401 ($eq). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2670$400 ($eq). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2668$399 ($eq). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2667$397 ($eq). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2667$396 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2665$395 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2663$393 ($and). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2662$392 ($eq). +Removed top 28 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2662$391 ($and). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2660$390 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2651$386 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2651$385 ($and). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2648$384 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2647$383 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2647$382 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2645$381 ($and). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2643$380 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2641$379 ($and). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2634$376 ($eq). +Removed top 3 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2634$375 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2632$374 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2630$373 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2628$372 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2627$371 ($eq). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2626$370 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2625$369 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2625$368 ($and). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2618$365 ($eq). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2617$364 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2614$363 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2614$362 ($and). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2611$361 ($and). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2609$360 ($and). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2602$354 ($eq). +Removed top 11 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2602$353 ($and). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2600$352 ($and). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2599$351 ($eq). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2599$350 ($eq). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2598$349 ($eq). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2598$348 ($and). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2597$347 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2597$346 ($and). +Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2595$345 ($and). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2593$344 ($and). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2585$341 ($eq). +Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2582$340 ($eq). +Removed top 18 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2581$339 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2580$338 ($eq). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2579$336 ($eq). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2579$335 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2578$334 ($eq). +Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2576$332 ($and). +Removed top 1 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2569$328 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2568$327 ($eq). +Removed top 6 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2568$326 ($and). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2567$325 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2567$324 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2559$320 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2555$314 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2553$313 ($and). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2548$309 ($eq). +Removed top 26 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2548$308 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2547$307 ($eq). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2547$306 ($and). +Removed top 29 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2546$305 ($eq). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2546$304 ($and). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2544$303 ($and). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2537$299 ($eq). +Removed top 17 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2537$298 ($and). +Removed top 19 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$eq$PQVexRiscvUlx3s.v:2536$297 ($eq). +Removed top 27 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2535$295 ($and). +Removed top 25 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2534$293 ($and). +Removed top 1 bits (of 33) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add). +Removed top 32 bits (of 33) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add). +Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add). +Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 ($add). +Removed top 31 bits (of 32) from mux cell PQVexRiscvUlx3s.$flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:2497$283 ($mux). +Removed top 30 bits (of 32) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 ($add). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub). +Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and). +Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$and$PQVexRiscvUlx3s.v:2477$274 ($and). +Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273 ($not). +Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273 ($not). +Removed top 15 bits (of 48) from port B of cell PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269 ($add). +Removed top 1 bits (of 33) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sshr$PQVexRiscvUlx3s.v:2458$266 ($sshr). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2139_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2138_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2135_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2134_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2133_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2079_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2078_CMP0 ($eq). +Removed cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$procmux$2064 ($mux). +Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5752$976 ($eq). +Removed top 2 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5737$973 ($eq). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$eq$PQVexRiscvUlx3s.v:5736$972 ($eq). +Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5704$970 ($mux). +Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968 ($mux). +Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5695$967 ($mux). +Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966 ($mux). +Removed top 1 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964 ($mux). +Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5674$960 ($mux). +Removed top 3 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5665$957 ($mux). +Removed top 2 bits (of 4) from mux cell PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2060 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2058 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2054 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$procmux$2042 ($mux). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992 ($add). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4418 ($ne). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4376 ($ne). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$opt_dff.cc:218:make_patterns_logic$4360 ($ne). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4245 ($eq). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3505 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procmux$3507 ($mux). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$procdff$4080 ($dff). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add). +Removed top 3 bits (of 4) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3505 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procmux$3507 ($mux). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$procdff$4080 ($dff). +Removed top 19 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4201 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$auto$fsm_map.cc:77:implement_pattern_cache$4197 ($eq). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$procmux$3641 ($mux). +Removed top 7 bits (of 8) from port A of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$shl$PQVexRiscvUlx3s.v:0$77 ($shl). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub). +Removed top 6 bits (of 7) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add). +Removed top 2 bits (of 5) from port B of cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1887_CMP0 ($eq). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1880 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1878 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1874 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\apb3UartCtrl_1_.$procmux$1872 ($mux). +Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerB.$procmux$3472 ($mux). +Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\timerA.$procmux$3472 ($mux). +Removed top 15 bits (of 16) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156 ($add). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1769_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1732_CMP0 ($eq). +Removed top 3 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1720_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1707_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1696_CMP0 ($eq). +Removed top 3 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1691_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1681_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell PQVexRiscvUlx3s.$flatten\muraxApb3Timer_1_.$procmux$1676_CMP0 ($eq). +Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\myMem_1_.$procmux$1669_CMP0 ($eq). +Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6874$1105 ($eq). +Removed top 2 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6873$1102 ($eq). +Removed top 3 bits (of 20) from port B of cell PQVexRiscvUlx3s.$flatten\io_apb_decoder.$eq$PQVexRiscvUlx3s.v:6872$1099 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\apb3Router_1_.$procmux$1654_CMP0 ($eq). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3862 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3859 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3856 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procdff$3853 ($dff). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1638 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1636 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1632 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1630 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1626 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1624 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1620 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0.$procmux$1618 ($mux). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3862 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3859 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3856 ($dff). +Removed top 7 bits (of 8) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procdff$3853 ($dff). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1638 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1636 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1632 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1630 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1626 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1624 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1620 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1.$procmux$1618 ($mux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$procmux$1614_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192 ($sub). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 ($add). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229 ($sub). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3442 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3444 ($mux). +Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4064 ($dff). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3446 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2_.$procmux$3450 ($mux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1196$182 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$procmux$3464 ($mux). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add). +Removed top 2 bits (of 3) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3442 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procmux$3444 ($mux). +Removed top 1 bits (of 2) from FF cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$procdff$4064 ($dff). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3446 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2_.$procmux$3450 ($mux). +Removed top 1 bits (of 2) from port B of cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$ternary$PQVexRiscvUlx3s.v:1196$182 ($mux). +Removed cell PQVexRiscvUlx3s.$flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$procmux$3464 ($mux). +Removed top 1 bits (of 2) from port Y of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub). +Removed top 1 bits (of 2) from port A of cell PQVexRiscvUlx3s.$flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub). +Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$0\memory_MulDivIterativePlugin_rs1[32:0]. +Removed top 1 bits (of 33) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849_Y. +Removed top 1 bits (of 2) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2477$273_Y. +Removed top 19 bits (of 32) from wire PQVexRiscvUlx3s.$flatten\core_cpu.$or$PQVexRiscvUlx3s.v:4815$782_Y. +Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956_Y. +Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5665$957_Y. +Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5674$960_Y. +Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964_Y. +Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966_Y. +Removed top 2 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5695$967_Y. +Removed top 1 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968_Y. +Removed top 3 bits (of 4) from wire PQVexRiscvUlx3s.$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5704$970_Y. +Removed top 3 bits (of 32) from wire PQVexRiscvUlx3s.apb3UartCtrl_1__io_apb_PRDATA. +Removed top 15 bits (of 32) from wire PQVexRiscvUlx3s.muraxApb3Timer_1__io_apb_PRDATA. + +2.15. Executing PEEPOPT pass (run peephole optimizers). + +2.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 1 unused cells and 77 unused wires. + + +2.17. Executing SHARE pass (SAT-based resource sharing). + +2.18. Executing TECHMAP pass (map to technology primitives). + +2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.18.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.19. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.20. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.21. Executing TECHMAP pass (map to technology primitives). + +2.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +2.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL18X18'. +Successfully finished Verilog frontend. + +2.21.3. Continuing TECHMAP pass. +Using template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\_80_mul for cells of type $mul. +Using template $paramod\$__MUL18X18\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=32\A_SIGNED=0\B_SIGNED=0 for cells of type $__MUL18X18. +No more expansions possible. + + +2.22. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module PQVexRiscvUlx3s: + creating $macc model for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008 ($sub). + creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112 ($sub). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65 ($sub). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127 ($add). + creating $macc model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146 ($sub). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2494$280 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2505$286 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849 ($add). + creating $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852 ($add). + creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275 ($sub). + creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550 ($sub). + creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705 ($sub). + creating $macc model for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813 ($sub). + creating $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 ($add). + creating $macc model for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192 ($sub). + creating $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 ($add). + creating $macc model for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229 ($sub). + creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub). + creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add). + creating $macc model for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add). + creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173 ($sub). + creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211 ($add). + creating $macc model for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217 ($add). + creating $macc model for $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156 ($add). + creating $macc model for $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165 ($add). + creating $macc model for $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165 ($add). + creating $macc model for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992 ($add). + merging $macc model for $flatten\core_ibus_decoder.$add$PQVexRiscvUlx3s.v:7250$1195 into $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229. + merging $macc model for $flatten\core_dbus_decoder.$add$PQVexRiscvUlx3s.v:7112$1151 into $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192. + merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2481$276 into $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550. + merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2505$286 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284. + merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2506$288 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284. + merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2494$280 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279. + merging $macc model for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4549$692 into $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269. + creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217. + creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211. + creating $alu model for $macc $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173. + creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173. + creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211. + creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813. + creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705. + creating $alu model for $macc $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704. + creating $alu model for $macc $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518. + creating $alu model for $macc $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292. + creating $alu model for $macc $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165. + creating $alu model for $macc $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156. + creating $alu model for $macc $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165. + creating $alu model for $macc $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133. + creating $alu model for $macc $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008. + creating $macc cell for $flatten\core_dbus_decoder.$sub$PQVexRiscvUlx3s.v:7188$1192: $auto$alumacc.cc:365:replace_macc$4675 + creating $macc cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:3862$550: $auto$alumacc.cc:365:replace_macc$4676 + creating $macc cell for $flatten\core_ibus_decoder.$sub$PQVexRiscvUlx3s.v:7310$1229: $auto$alumacc.cc:365:replace_macc$4677 + creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2493$279: $auto$alumacc.cc:365:replace_macc$4678 + creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2504$284: $auto$alumacc.cc:365:replace_macc$4679 + creating $macc cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2463$269: $auto$alumacc.cc:365:replace_macc$4680 + creating $alu model for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146. + creating $alu model for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134 ($eq): merged with $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146. + creating $alu cell for $flatten\apb3UartCtrl_1_.$sub$PQVexRiscvUlx3s.v:6078$1008: $auto$alumacc.cc:485:replace_alu$4681 + creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4684 + creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4687 + creating $alu cell for $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4690 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.$sub$PQVexRiscvUlx3s.v:903$112: $auto$alumacc.cc:485:replace_alu$4695 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:498$56: $auto$alumacc.cc:485:replace_alu$4698 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$add$PQVexRiscvUlx3s.v:561$66: $auto$alumacc.cc:485:replace_alu$4701 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\rx.$sub$PQVexRiscvUlx3s.v:555$65: $auto$alumacc.cc:485:replace_alu$4704 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:212$10: $auto$alumacc.cc:485:replace_alu$4707 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1_.\tx.$add$PQVexRiscvUlx3s.v:308$24: $auto$alumacc.cc:485:replace_alu$4710 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:1021$133: $auto$alumacc.cc:485:replace_alu$4713 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$add$PQVexRiscvUlx3s.v:998$127: $auto$alumacc.cc:485:replace_alu$4716 + creating $alu cell for $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$sub$PQVexRiscvUlx3s.v:1035$146, $flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$eq$PQVexRiscvUlx3s.v:1027$134: $auto$alumacc.cc:485:replace_alu$4719 + creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217: $auto$alumacc.cc:485:replace_alu$4724 + creating $alu cell for $flatten\muraxApb3Timer_1_.\timerB.$add$PQVexRiscvUlx3s.v:1116$165: $auto$alumacc.cc:485:replace_alu$4727 + creating $alu cell for $flatten\muraxApb3Timer_1_.\prescaler_1_.$add$PQVexRiscvUlx3s.v:1072$156: $auto$alumacc.cc:485:replace_alu$4730 + creating $alu cell for $flatten\muraxApb3Timer_1_.\timerA.$add$PQVexRiscvUlx3s.v:1116$165: $auto$alumacc.cc:485:replace_alu$4733 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:2515$292: $auto$alumacc.cc:485:replace_alu$4736 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518: $auto$alumacc.cc:485:replace_alu$4739 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4536$689: $auto$alumacc.cc:485:replace_alu$4742 + creating $alu cell for $flatten\systemDebugger_1_.$add$PQVexRiscvUlx3s.v:5857$992: $auto$alumacc.cc:485:replace_alu$4745 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:4603$704: $auto$alumacc.cc:485:replace_alu$4748 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5115$841: $auto$alumacc.cc:485:replace_alu$4751 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5117$842: $auto$alumacc.cc:485:replace_alu$4754 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5163$849: $auto$alumacc.cc:485:replace_alu$4757 + creating $alu cell for $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:5164$852: $auto$alumacc.cc:485:replace_alu$4760 + creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:2478$275: $auto$alumacc.cc:485:replace_alu$4763 + creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4612$705: $auto$alumacc.cc:485:replace_alu$4766 + creating $alu cell for $flatten\core_cpu.$sub$PQVexRiscvUlx3s.v:4947$813: $auto$alumacc.cc:485:replace_alu$4769 + creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211: $auto$alumacc.cc:485:replace_alu$4772 + creating $alu cell for $flatten\memory_ramBlocks_1_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173: $auto$alumacc.cc:485:replace_alu$4775 + creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\logic_arbiter.$sub$PQVexRiscvUlx3s.v:1186$173: $auto$alumacc.cc:485:replace_alu$4778 + creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1370$211: $auto$alumacc.cc:485:replace_alu$4781 + creating $alu cell for $flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$add$PQVexRiscvUlx3s.v:1397$217: $auto$alumacc.cc:485:replace_alu$4784 + created 34 $alu and 6 $macc cells. + +2.23. Executing OPT pass (performing simple optimizations). + +2.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 8 cells. + +2.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 5 cells. + +2.23.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3861 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3858 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3855 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_1.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3861 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [31:24], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:7033$1114_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3858 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [23:16], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:7030$1113_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3855 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [15:8], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:7027$1112_DATA, rval = 8'00000000). +Adding SRST signal on $flatten\memory_ramBlocks_0.$procdff$3852 ($dff) from module PQVexRiscvUlx3s (D = \_zz_33_ [7:0], Q = $flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:7024$1111_DATA, rval = 8'00000000). +Adding SRST signal on $auto$opt_dff.cc:764:run$4398 ($dffe) from module PQVexRiscvUlx3s (D = \jtagBridge_1_.jtag_readArea_shifter [2], Q = \jtagBridge_1_.jtag_readArea_shifter [1], rval = 1'0). + +2.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 9 unused cells and 75 unused wires. + + +2.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.23.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.23.16. Finished OPT passes. (There is nothing left to do.) + +2.24. Executing MEMORY pass. + +2.24.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +2.24.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memwr$\logic_ram$PQVexRiscvUlx3s.v:0$153' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\core_cpu.$memwr$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:0$949' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1147' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1148' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1149' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1150' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$233' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol0$PQVexRiscvUlx3s.v:0$1147' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol1$PQVexRiscvUlx3s.v:0$1148' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol2$PQVexRiscvUlx3s.v:0$1149' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memwr$\ram_symbol3$PQVexRiscvUlx3s.v:0$1150' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memwr$\ram$PQVexRiscvUlx3s.v:0$233' in module `\PQVexRiscvUlx3s': merged $dff to cell. +Checking cell `$flatten\apb3UartCtrl_1_.\bridge_write_streamUnbuffered_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\apb3UartCtrl_1_.\uartCtrl_1__io_read_queueWithOccupancy.$memrd$\logic_ram$PQVexRiscvUlx3s.v:964$116' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2686$414' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\core_cpu.$memrd$\RegFilePlugin_regFile$PQVexRiscvUlx3s.v:2692$416' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_0_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1336$200' in module `\PQVexRiscvUlx3s': no (compatible) $dff found. +Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol0$PQVexRiscvUlx3s.v:7015$1117' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol1$PQVexRiscvUlx3s.v:7016$1118' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol2$PQVexRiscvUlx3s.v:7017$1119' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1.$memrd$\ram_symbol3$PQVexRiscvUlx3s.v:7018$1120' in module `\PQVexRiscvUlx3s': merged data $dff to cell. +Checking cell `$flatten\memory_ramBlocks_1_io_bus_arbiter.\streamFork_2__io_outputs_1_translated_thrown_fifo.$memrd$\ram$PQVexRiscvUlx3s.v:1336$200' in module `\PQVexRiscvUlx3s': no (compatible) $dff found. + +2.24.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 43 unused cells and 55 unused wires. + + +2.24.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.24.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.24.6. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.25. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile: + Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol0: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol0.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol0.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol0.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol0.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol0.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol0.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol0.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol0.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol1: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol1.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol1.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol1.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol1.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol1.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol1.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol1.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol1.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol2: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol2.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol2.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol2.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol2.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol2.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol2.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol2.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol2.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_0.ram_symbol3: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_0.ram_symbol3.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_0.ram_symbol3.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_0.ram_symbol3.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_0.ram_symbol3.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_0.ram_symbol3.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_0.ram_symbol3.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_0.ram_symbol3.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_0.ram_symbol3.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram: + Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol0: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol0.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol0.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol0.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol0.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol0.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol0.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol0.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol0.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol1: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol1.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol1.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol1.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol1.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol1.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol1.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol1.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol1.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol2: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol2.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol2.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol2.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol2.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol2.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol2.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol2.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol2.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_1.ram_symbol3: + Properties: ports=2 bits=131072 rports=1 wports=1 dbits=8 abits=14 words=16384 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=100, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=100, cells=8, acells=2 + Efficiency for rule 4.3: efficiency=100, cells=8, acells=4 + Efficiency for rule 4.2: efficiency=88, cells=8, acells=8 + Efficiency for rule 4.1: efficiency=44, cells=16, acells=16 + Efficiency for rule 1.1: efficiency=22, cells=32, acells=32 + Selected rule 4.5 with efficiency 100. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: memory_ramBlocks_1.ram_symbol3.0.0.0 + Creating $__ECP5_DP16KD cell at grid position <1 0 0>: memory_ramBlocks_1.ram_symbol3.1.0.0 + Creating $__ECP5_DP16KD cell at grid position <2 0 0>: memory_ramBlocks_1.ram_symbol3.2.0.0 + Creating $__ECP5_DP16KD cell at grid position <3 0 0>: memory_ramBlocks_1.ram_symbol3.3.0.0 + Creating $__ECP5_DP16KD cell at grid position <4 0 0>: memory_ramBlocks_1.ram_symbol3.4.0.0 + Creating $__ECP5_DP16KD cell at grid position <5 0 0>: memory_ramBlocks_1.ram_symbol3.5.0.0 + Creating $__ECP5_DP16KD cell at grid position <6 0 0>: memory_ramBlocks_1.ram_symbol3.6.0.0 + Creating $__ECP5_DP16KD cell at grid position <7 0 0>: memory_ramBlocks_1.ram_symbol3.7.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram: + Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=505 dwaste=34 bwaste=18418 waste=18418 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1017 dwaste=16 bwaste=18418 waste=18418 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2041 dwaste=7 bwaste=18418 waste=18418 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4089 dwaste=2 bwaste=16370 waste=16370 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8185 dwaste=0 bwaste=16370 waste=16370 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16377 dwaste=0 bwaste=16377 waste=16377 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. + +2.27. Executing TECHMAP pass (map to technology primitives). + +2.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ECP5_DP16KD'. +Generating RTLIL representation for module `\$__ECP5_PDPW16KD'. +Successfully finished Verilog frontend. + +2.27.2. Continuing TECHMAP pass. +Using template $paramod$38262e435a9f54db3b5bdc33b5e39b1fffa1b883\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD. +No more expansions possible. + + +2.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0 +Processing PQVexRiscvUlx3s.apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: apb3UartCtrl_1_.uartCtrl_1__io_read_queueWithOccupancy.logic_ram.1.0.0 +Processing PQVexRiscvUlx3s.core_cpu.RegFilePlugin_regFile: + Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port A1.1. + Read port #1 is in clock domain \io_mainClock. + Failed to map read port #1. + Growing more read ports by duplicating bram cells. + Read port #0 is in clock domain \io_mainClock. + Mapped to bram port A1.1. + Read port #1 is in clock domain \io_mainClock. + Mapped to bram port A1.2. + Updated properties: dups=2 waste=0 efficiency=50 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: core_cpu.RegFilePlugin_regFile.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: core_cpu.RegFilePlugin_regFile.0.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: core_cpu.RegFilePlugin_regFile.0.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: core_cpu.RegFilePlugin_regFile.0.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: core_cpu.RegFilePlugin_regFile.1.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: core_cpu.RegFilePlugin_regFile.1.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: core_cpu.RegFilePlugin_regFile.1.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: core_cpu.RegFilePlugin_regFile.1.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: core_cpu.RegFilePlugin_regFile.2.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: core_cpu.RegFilePlugin_regFile.2.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: core_cpu.RegFilePlugin_regFile.2.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: core_cpu.RegFilePlugin_regFile.2.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: core_cpu.RegFilePlugin_regFile.3.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: core_cpu.RegFilePlugin_regFile.3.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: core_cpu.RegFilePlugin_regFile.3.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: core_cpu.RegFilePlugin_regFile.3.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: core_cpu.RegFilePlugin_regFile.4.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: core_cpu.RegFilePlugin_regFile.4.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: core_cpu.RegFilePlugin_regFile.4.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: core_cpu.RegFilePlugin_regFile.4.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: core_cpu.RegFilePlugin_regFile.5.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: core_cpu.RegFilePlugin_regFile.5.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: core_cpu.RegFilePlugin_regFile.5.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: core_cpu.RegFilePlugin_regFile.5.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: core_cpu.RegFilePlugin_regFile.6.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: core_cpu.RegFilePlugin_regFile.6.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: core_cpu.RegFilePlugin_regFile.6.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: core_cpu.RegFilePlugin_regFile.6.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: core_cpu.RegFilePlugin_regFile.7.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: core_cpu.RegFilePlugin_regFile.7.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: core_cpu.RegFilePlugin_regFile.7.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: core_cpu.RegFilePlugin_regFile.7.1.1 +Processing PQVexRiscvUlx3s.memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram: + Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port B1. + Read port #0 is in clock domain !~async~. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=50 efficiency=21 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_0_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0 +Processing PQVexRiscvUlx3s.memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram: + Properties: ports=2 bits=14 rports=1 wports=1 dbits=2 abits=3 words=7 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=2 bwaste=50 waste=50 efficiency=21 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClock. + Mapped to bram port B1. + Read port #0 is in clock domain !~async~. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=50 efficiency=21 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: memory_ramBlocks_1_io_bus_arbiter.streamFork_2__io_outputs_1_translated_thrown_fifo.ram.0.0.0 + +2.29. Executing TECHMAP pass (map to technology primitives). + +2.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'. +Successfully finished Verilog frontend. + +2.29.2. Continuing TECHMAP pass. +Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4. +No more expansions possible. + + +2.30. Executing OPT pass (performing simple optimizations). + +2.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 91 cells. + +2.30.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 3 unused cells and 1247 unused wires. + + +2.30.5. Finished fast OPT passes. + +2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.32. Executing OPT pass (performing simple optimizations). + +2.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2445: + Old ports: A=4'0111, B=4'0011, Y=$flatten\core_cpu.$procmux$2445_Y + New ports: A=1'1, B=1'0, Y=$flatten\core_cpu.$procmux$2445_Y [2] + New connections: { $flatten\core_cpu.$procmux$2445_Y [3] $flatten\core_cpu.$procmux$2445_Y [1:0] } = 3'011 + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$2662: + Old ports: A=4'0000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3:2] 2'11 }, Y=\core_cpu._zz_130_ [3:0] + New ports: A=3'000, B={ \core_cpu.CsrPlugin_mcause_exceptionCode [3:2] 1'1 }, Y={ \core_cpu._zz_130_ [3:2] \core_cpu._zz_130_ [0] } + New connections: \core_cpu._zz_130_ [1] = \core_cpu._zz_130_ [0] + Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$2793: + Old ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [30:25] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [30:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31:20] }, Y=\core_cpu.execute_BranchPlugin_branch_src2 [19:0] + New ports: A={ \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [7] \core_cpu.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \core_cpu.decode_to_execute_INSTRUCTION [19:12] \core_cpu.decode_to_execute_INSTRUCTION [20] \core_cpu.decode_to_execute_INSTRUCTION [24:21] 1'0 \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [31] \core_cpu.decode_to_execute_INSTRUCTION [24:20] }, Y={ \core_cpu.execute_BranchPlugin_branch_src2 [19:11] \core_cpu.execute_BranchPlugin_branch_src2 [4:0] } + New connections: \core_cpu.execute_BranchPlugin_branch_src2 [10:5] = \core_cpu.decode_to_execute_INSTRUCTION [30:25] + Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3044: + Old ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_69_ [7:0] \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] \core_cpu._zz_69_ [7:0] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated + New ports: A={ \core_cpu.memory_to_writeBack_MEMORY_READ_DATA [31:16] \core_cpu._zz_71_ [15:8] }, B={ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_68_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_70_ \core_cpu._zz_71_ [15:8] }, Y=\core_cpu.writeBack_DBusSimplePlugin_rspFormated [31:8] + New connections: \core_cpu.writeBack_DBusSimplePlugin_rspFormated [7:0] = \core_cpu._zz_69_ [7:0] + Consolidated identical input bits for $pmux cell $flatten\core_cpu.$procmux$3061: + Old ports: A=\core_cpu.decode_to_execute_RS2, B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:0] }, Y=\_zz_20_ + New ports: A=\core_cpu.decode_to_execute_RS2 [31:8], B={ \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [7:0] \core_cpu.decode_to_execute_RS2 [15:0] \core_cpu.decode_to_execute_RS2 [15:8] }, Y=\_zz_20_ [31:8] + New connections: \_zz_20_ [7:0] = \core_cpu.decode_to_execute_RS2 [7:0] + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3115: + Old ports: A=0, B={ \core_cpu.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] + New ports: A=30'000000000000000000000000000000, B=\core_cpu.CsrPlugin_mtvec_base, Y=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2] + New connections: $flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00 + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955: + Old ports: A=4'0001, B=4'1001, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y + New ports: A=1'0, B=1'1, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y [3] + New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5659$955_Y [2:0] = 3'001 + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5662$956: + Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$4657 [1:0] + New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$4657 [0] + New connections: $auto$wreduce.cc:454:run$4657 [1] = $auto$wreduce.cc:454:run$4657 [0] + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959: + Old ports: A=4'0110, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y + New ports: A=2'01, B=2'10, Y={ $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [3] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [1] } + New connections: { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [2] $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [0] } = { $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5671$959_Y [1] 1'0 } + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961: + Old ports: A=4'0100, B=4'1000, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y + New ports: A=2'01, B=2'10, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y [3:2] + New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5677$961_Y [1:0] = 2'00 + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963: + Old ports: A=4'1010, B=4'0010, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y + New ports: A=1'1, B=1'0, Y=$flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y [3] + New connections: $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5683$963_Y [2:0] = 3'010 + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5686$964: + Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$4660 [2:0] + New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$4660 [2] $auto$wreduce.cc:454:run$4660 [0] } + New connections: $auto$wreduce.cc:454:run$4660 [1] = $auto$wreduce.cc:454:run$4660 [0] + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5692$966: + Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:454:run$4661 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4661 [1] + New connections: $auto$wreduce.cc:454:run$4661 [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\jtagBridge_1_.$ternary$PQVexRiscvUlx3s.v:5698$968: + Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:454:run$4663 [2:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$4663 [2] + New connections: $auto$wreduce.cc:454:run$4663 [1:0] = 2'11 + Consolidated identical input bits for $pmux cell $procmux$1563: + Old ports: A=4'1111, B=8'00010011, Y=\_zz_22_ + New ports: A=2'11, B=4'0001, Y=\_zz_22_ [2:1] + New connections: { \_zz_22_ [3] \_zz_22_ [0] } = { \_zz_22_ [2] 1'1 } + Consolidated identical input bits for $mux cell $ternary$PQVexRiscvUlx3s.v:8194$1258: + Old ports: A={ \core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \_zz_7_ [31:2] 2'00 }, Y=$ternary$PQVexRiscvUlx3s.v:8194$1258_Y + New ports: A=\core_cpu.IBusSimplePlugin_fetchPc_pcReg [31:2], B=\_zz_7_ [31:2], Y=$ternary$PQVexRiscvUlx3s.v:8194$1258_Y [31:2] + New connections: $ternary$PQVexRiscvUlx3s.v:8194$1258_Y [1:0] = 2'00 + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3107: + Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B={ \core_cpu.CsrPlugin_mepc [31:2] 2'00 }, Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] + New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=\core_cpu.CsrPlugin_mepc [31:2], Y=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2] + New connections: $flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00 + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3112: + Old ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0], Y=\core_cpu.CsrPlugin_jumpInterface_payload + New ports: A=$flatten\core_cpu.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2], B=$flatten\core_cpu.$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\core_cpu.CsrPlugin_jumpInterface_payload [31:2] + New connections: \core_cpu.CsrPlugin_jumpInterface_payload [1:0] = 2'00 + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\core_cpu.$ternary$PQVexRiscvUlx3s.v:3749$513: + Old ports: A={ \core_cpu.execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\core_cpu.CsrPlugin_jumpInterface_payload, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload + New ports: A=\core_cpu.execute_to_memory_BRANCH_CALC [31:1], B={ \core_cpu.CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1] + New connections: \core_cpu.IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0 + Optimizing cells in module \PQVexRiscvUlx3s. + Consolidated identical input bits for $mux cell $flatten\core_cpu.$procmux$3088: + Old ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518_Y [31:2] 2'00 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload, Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] } + New ports: A={ $flatten\core_cpu.$add$PQVexRiscvUlx3s.v:3766$518_Y [31:2] 1'0 }, B=\core_cpu.IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \core_cpu.IBusSimplePlugin_fetchPc_pc [31:2] $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [1] } + New connections: $flatten\core_cpu.$1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0 + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 20 changes. + +2.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 7 cells. + +2.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 1 unused cells and 8 unused wires. + + +2.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.32.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \PQVexRiscvUlx3s.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \PQVexRiscvUlx3s. +Performed a total of 0 changes. + +2.32.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. +Removed a total of 0 cells. + +2.32.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.32.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + +2.32.16. Finished OPT passes. (There is nothing left to do.) + +2.33. Executing TECHMAP pass (map to technology primitives). + +2.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +2.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ecp5_alu'. +Successfully finished Verilog frontend. + +2.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. +Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl. +Using extmapper simplemap for cells of type $adff. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $adffe. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $sdffce. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $not. +Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=2 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. +Using extmapper maccmap for cells of type $macc. + add \core_ibus_decoder.logic_rspPendingCounter (2 bits, unsigned) + sub \core_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.io_push_valid (1 bits, unsigned) + add bits \core_ibus_decoder._zz_5_ (1 bits) + packed 1 (1) bits / 1 words into adder tree +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. + add { \core_cpu.execute_to_memory_MUL_HH \core_cpu.execute_to_memory_MUL_LL [31:16] } (48 bits, unsigned) + add \core_cpu.execute_to_memory_MUL_LH (32 bits, unsigned) + add \core_cpu.execute_to_memory_MUL_HL (32 bits, unsigned) + add \core_cpu.memory_to_writeBack_MUL [63:32] (32 bits, unsigned) + add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2506$287_Y (32 bits, unsigned) + add $flatten\core_cpu.$not$PQVexRiscvUlx3s.v:2505$285_Y (32 bits, unsigned) + add 2 (32 bits, unsigned) + packed 2 (1) bits / 1 words into adder tree +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=33\B_WIDTH=32\Y_WIDTH=33 for cells of type $alu. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. +Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. +Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=11 for cells of type $pmux. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=1\Y_WIDTH=20 for cells of type $alu. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu. +Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux. +Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr'. + +2.33.77. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +2.33.78. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 8 unused wires. +Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$2c522b46cc21505f45a595eaa4706e490799228e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu. +Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=9 for cells of type $pmux. +Using template $paramod\_90_pmux\WIDTH=14\S_WIDTH=5 for cells of type $pmux. + add \core_dbus_decoder.logic_rspPendingCounter (2 bits, unsigned) + sub \core_cpu.dBus_rsp_ready (1 bits, unsigned) + add bits \core_dbus_decoder._zz_6_ (1 bits) + packed 1 (1) bits / 1 words into adder tree + add \core_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned) + sub \core_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned) + add bits \core_cpu.IBusSimplePlugin_pending_inc (1 bits) + packed 1 (1) bits / 1 words into adder tree + add \core_cpu.decode_to_execute_SRC1 (32 bits, signed) + add { 1'0 \core_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed) + add \core_cpu._zz_211_ (32 bits, signed) + packed 1 (1) bits / 1 words into adder tree +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=48 for cells of type $fa. +Using template $paramod\_80_ecp5_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $alu. +Using template $paramod\_90_fa\WIDTH=2 for cells of type $fa. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. +Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu. +Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa. +Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=3 for cells of type $fa. +Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. +Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. +No more expansions possible. + + +2.34. Executing OPT pass (performing simple optimizations). + +2.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\PQVexRiscvUlx3s'. + +Removed a total of 701 cells. + +2.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 1315 unused cells and 4250 unused wires. + + +2.34.5. Finished fast OPT passes. + +2.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. + +2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.37. Executing TECHMAP pass (map to technology primitives). + +2.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +2.37.2. Continuing TECHMAP pass. +Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. +Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. +Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. +Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. +Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. +Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. +Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. +Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. +Using template \$_SDFFE_PP1N_ for cells of type $_SDFFE_PP1N_. +Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_. +Using template \$_DFFE_PP1N_ for cells of type $_DFFE_PP1N_. +No more expansions possible. + + +2.38. Executing OPT_EXPR pass (perform const folding). +Optimizing module PQVexRiscvUlx3s. + + +2.39. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +2.40. Executing ECP5_GSR pass (implement FF init values). +Handling GSR in PQVexRiscvUlx3s. + +2.41. Executing ATTRMVCP pass (move or copy attributes). + +2.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \PQVexRiscvUlx3s.. +Removed 0 unused cells and 11101 unused wires. + + +2.43. Executing TECHMAP pass (map to technology primitives). + +2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.43.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.44. Executing ABC pass (technology mapping using ABC). + +2.44.1. Extracting gate netlist of module `\PQVexRiscvUlx3s' to `/input.blif'.. +Extracted 6537 gates and 8799 wires to a netlist network with 2260 inputs and 1531 outputs. + +2.44.1.1. Executing ABC. +Running ABC command: /yosys-abc -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lut /lutdefs.txt +ABC: + strash +ABC: + ifraig +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + dch -f +ABC: + if +ABC: + mfs2 +ABC: + dress +ABC: Total number of equiv classes = 2068. +ABC: Participating nodes from both networks = 4475. +ABC: Participating nodes from the first network = 2143. ( 76.62 % of nodes) +ABC: Participating nodes from the second network = 2332. ( 83.38 % of nodes) +ABC: Node pairs (any polarity) = 2143. ( 76.62 % of names can be moved) +ABC: Node pairs (same polarity) = 1679. ( 60.03 % of names can be moved) +ABC: Total runtime = 0.27 sec +ABC: + write_blif /output.blif + +2.44.1.2. Re-integrating ABC results. +ABC RESULTS: $lut cells: 2795 +ABC RESULTS: internal signals: 5008 +ABC RESULTS: input signals: 2260 +ABC RESULTS: output signals: 1531 +Removing temp directory. +Removed 0 unused cells and 5077 unused wires. + +2.45. Executing TECHMAP pass (map to technology primitives). + +2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +2.45.2. Continuing TECHMAP pass. +Using template $paramod\$lut\WIDTH=5\LUT=1429470991 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10111011101100000000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11100000000000001111000011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10110000000010110000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1001010001001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000000000000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101011001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=252663244 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001100110010101010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000011101110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=48911 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111100110011001111000010101010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. +Using template $paramod$33c350b0c33c8d11c06e32a4943a9c25a543a6b7\$lut for cells of type $lut. +Using template $paramod$89dd30d619d00b12368cbcf6b88c08bd89e1c657\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=2147450880 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=386990080 for cells of type $lut. +Using template $paramod$1922694d1ba66dc9e8c99f5f26ba1b86bfc1d372\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. +Using template $paramod$ef003d70d3febf7a5568510cba4a0111646430ac\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1429409791 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1911 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010001111111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. +Using template $paramod$f6783b5b9c23cd67232c94ac1b12661d5b0309d0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000011100001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=196131771 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100110101110001 for cells of type $lut. +Using template $paramod$c708770091716d95e2d30be87305b107dccb9e26\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=16777216 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=65536 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=268500992 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut. +Using template $paramod$b1bd2a921ec0f1ea0cc7578a2bcf32d761c7f62f\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut. +Using template $paramod$f340a7e85fbe3e11c384ecf1cd11a7f6ad674e2c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=218103821 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10111011000010110000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10010000000010010000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=218103808 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=47883 for cells of type $lut. +Using template $paramod$31a944f0c6934f915f24e075bcacadd2906c8e5f\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100000001000000010000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=251986703 for cells of type $lut. +Using template $paramod$078354ad4f08d5c6e8687216ff1586f28ff6611c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001111110000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=285212671 for cells of type $lut. +Using template $paramod$1519fab0160880cb5431b6d4859cd9e32e014092\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11101100111111111010000011110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0101001110101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011110001011010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=2035471 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=252663091 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111100011111111111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001010101000110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011010001001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110100111111110000000011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000101000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=184549387 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011100000 for cells of type $lut. +Using template $paramod$d6a97cece58353cd8de5b6e824f1d055bdb32a45\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111110001111111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=458752 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111110101111000011110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000011101111111111110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111110110000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=3003 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000001000110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0110111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=31 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=7697919 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111110000000001111111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111010011111111111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. +Using template $paramod$1823a31c85f9522086df2e636a0e5ffeb1bbf92b\$lut for cells of type $lut. +Using template $paramod$6e8e9a95aa7012438678197fd66a79121b4bccb4\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=268435456 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=65408 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011011111000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=268398592 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1065336832 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1073709056 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10000000011111110000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10111111001100000001101111000111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1142743210 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1333248160 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11101011011100001111000011100000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=196148992 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10101010110011001111000011110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0101011100110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111000100010000000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=65344 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1099049025 for cells of type $lut. +Using template $paramod$ea79ac074ef5daf30bdd86a73922fd1b4427f4d0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=33488896 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=2004287600 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1065304064 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11001111101011110000111100001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=8355711 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111010011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=267444928 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=125239296 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10100011 for cells of type $lut. +Using template $paramod$fa50846fb39690c96e73e2bf7881b0c024a78beb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000000100010000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000000000010111011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=252641501 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111011100000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. +Using template $paramod$f19bb2391741f41ed6688663c633088d08e018c2\$lut for cells of type $lut. +Using template $paramod$2a0a976802391efa54393fb43c1a1243cd176ffd\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111101001111111100000000 for cells of type $lut. +Using template $paramod$063f7b90c9d87abb5e00dc22f30b48c5d12e80b3\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11101111111111110000000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10111111000000001111111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111111100010001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0010101100100010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100001000100011111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=16639 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110111000010001110111100010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11001100101010101111000011110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10101010001100111111000011110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111110111111100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100110111011101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00011110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11110000111100000101010100110011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011010101010011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=866840816 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11111111000100010000111100001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1429467376 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=252654421 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100111010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10001111111110001000100010001000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111101011111100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. +Using template $paramod$176d9ae664c431997aaa426f223ab1bcc6188d13\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=251723656 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000111111101110 for cells of type $lut. +Using template $paramod$18ef73fafbda5af11588c66ef5f31f738568c5c8\$lut for cells of type $lut. +Using template $paramod$2ff21013616bea2c768a52e378d46babb5d3dc5a\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'11101111010000001100110011001100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=32'10111111111111110100000000000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101110111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111100011100001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0100110110110010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'0000001111111101 for cells of type $lut. +Using template $paramod$c6d51bbba2974d40075f64507965a1fed88c7c87\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=4\LUT=16'1101001010110100 for cells of type $lut. +Using template $paramod$9abd567e56fa5e5fe88aefab580dea7b3d3324a7\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=5\LUT=1431683900 for cells of type $lut. +No more expansions possible. + + +2.46. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in PQVexRiscvUlx3s. + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27959.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27961.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27978.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27965.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27988.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27984.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27976.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27980.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27986.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27990.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27996.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28000.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut2 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut3 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28099.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28096.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28108.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28100.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28103.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28117.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28104.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28105.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28120.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28125.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28135.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28413.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27770.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27794.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26189.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27791.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26128.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27314.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27780.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27768.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27788.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27137.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27138.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27297.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27058.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27280.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28131.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28101.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28097.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28085.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27331.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27790.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27779.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27774.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27769.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27348.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27246.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27631.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27643.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27614.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut2 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut3 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27497.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27501.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26942.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27492.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27493.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27505.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27476.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27439.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26214.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26960.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26964.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26963.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27039.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27060.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27119.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27101.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26905.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26127.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut3 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26926.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26927.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut6 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut7 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26222.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26222.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26016.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26833.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26821.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26820.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26819.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut2 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut4 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut5 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut6 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut7 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26884.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26866.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut3 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut4 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut5 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut7 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut2 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut3 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut4 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut5 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut5 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut6 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut2 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut3 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut4 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut5 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27000.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26982.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25885.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25887.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25889.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25898.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25907.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25912.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25923.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25934.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25939.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25951.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25955.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25961.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25974.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25992.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26011.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26015.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26016.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26824.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26016.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25990.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26042.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26043.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26998.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26052.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25983.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26078.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26073.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26101.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26106.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26120.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26127.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26128.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26129.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26134.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25943.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26132.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26128.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26127.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26146.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26189.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26196.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26199.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26205.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26214.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26216.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26220.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26222.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26223.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26227.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26245.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26244.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26275.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26277.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26300.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26305.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26311.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26320.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26323.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26348.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26348.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26350.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26350.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26354.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26368.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27045.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26175.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26579.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26579.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26664.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26659.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26662.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26665.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27765.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26724.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26725.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27038.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26723.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26757.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$25954.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26978.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26785.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26785.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26799.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26800.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26817.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26818.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26823.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27020.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26817.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26818.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26819.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26820.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26821.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26822.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26823.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26824.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26827.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26829.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26830.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26833.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26837.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26837.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26841.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26829.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26843.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26848.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26827.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26999.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26864.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26864.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26865.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26866.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26869.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26869.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26871.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26855.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26865.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26879.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26881.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26883.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26883.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26884.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26885.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26888.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26890.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26885.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26888.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26901.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26903.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26903.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26904.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26905.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26904.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26908.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26908.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26910.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26923.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26925.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26925.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26926.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26927.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26930.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26930.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26932.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26942.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26944.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26945.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26946.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26945.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26949.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26949.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26951.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26946.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26944.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26960.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26962.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26963.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26964.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26967.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26967.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26969.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26962.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26978.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26980.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26981.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26982.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26985.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26985.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26987.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26981.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26980.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26998.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27000.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27007.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27007.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27010.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27020.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27021.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27022.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27022.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27029.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27038.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27040.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27045.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27048.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27058.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27060.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27040.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27100.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27065.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27068.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27065.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27080.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27081.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27082.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27089.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27082.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27099.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27101.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27106.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27106.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27109.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27119.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27120.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27121.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27080.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27121.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27128.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27137.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27139.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27140.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27144.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27144.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27147.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27157.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27159.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27169.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27181.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27183.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27190.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27201.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27203.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27210.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27221.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27223.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27766.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27230.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27241.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27242.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27243.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27583.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27246.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27248.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27258.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27259.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27260.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27263.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27265.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27263.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27259.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27275.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27276.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27277.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27595.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27280.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27282.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27276.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27292.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27293.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27294.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27297.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27299.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27293.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27309.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27310.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27311.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27314.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27316.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27310.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27326.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27327.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27328.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27331.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27333.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27343.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27344.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27345.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27348.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27350.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27360.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27344.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27362.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27626.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27369.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27380.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27381.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27382.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27385.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27385.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27387.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27397.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27399.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27381.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27406.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27417.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27418.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27419.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27422.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27422.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27424.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$26822.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27418.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27434.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27435.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27436.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27439.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27441.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27448.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27435.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27451.lut1 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27476.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27483.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27483.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27484.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27487.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27513.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27492.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27493.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27494.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27496.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27496.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27497.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27500.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27500.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27501.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27504.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27504.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27505.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27507.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27507.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27509.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27509.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27512.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27512.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27513.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27515.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27515.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27517.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27517.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27518.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27520.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27520.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27522.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27524.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27526.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27528.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27528.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27530.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27532.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27532.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27540.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27544.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27548.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27535.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27551.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27159.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27524.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27558.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27565.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27572.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27580.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27583.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27584.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27963.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27592.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27595.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27596.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27603.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27611.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27614.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27615.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27626.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27631.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27632.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27628.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27640.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27623.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27643.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27644.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27652.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27655.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27664.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27676.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27688.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27059.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27099.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27242.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27674.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27707.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27714.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27139.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27686.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27778.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27745.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27775.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27796.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27786.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27753.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27759.lut0 (4 -> 2) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27787.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27765.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27766.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27767.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27768.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27769.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27770.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27771.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27772.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27773.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27774.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27775.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27776.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27777.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27778.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27779.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27780.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27781.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27782.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27783.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27784.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27785.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27786.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27787.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27788.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27789.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27790.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27791.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27792.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27793.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27794.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27795.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27796.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27789.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27795.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27771.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27793.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27784.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27776.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27767.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27782.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27772.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27773.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27903.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27905.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27781.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27777.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27327.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27783.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27792.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27955.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27952.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27785.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27955.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27973.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27957.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27952.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27959.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27969.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27961.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27957.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27963.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27965.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27967.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27969.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27971.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27967.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27973.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27976.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27978.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27971.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27980.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27998.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27982.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27984.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27994.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27986.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27982.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27988.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27990.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28008.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27992.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27994.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28004.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27996.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27992.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$27998.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28000.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28002.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28004.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28006.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28002.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28008.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28010.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28012.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28006.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28012.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28010.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28098.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28063.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28087.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28102.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28087.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28093.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28107.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28096.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28097.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28098.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28099.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28100.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28101.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28102.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28103.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28104.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28105.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28106.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28107.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28108.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28106.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28111.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28090.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28114.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28111.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28117.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28114.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28137.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28120.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28121.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28142.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28125.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28128.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28138.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28121.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28131.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28128.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28143.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28134.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28135.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28137.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28138.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28139.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28140.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28141.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28142.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28143.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28141.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28139.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28134.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28140.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28237.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28235.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28418.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut1 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28413.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28415.lut0 (4 -> 0) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28417.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28418.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28420.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28420.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28446.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28451.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28451.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28508.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28552.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28480.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28480.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28569.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28565.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28504.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28507.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28508.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28446.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28517.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28517.lut0 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28507.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28534.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28534.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28562.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28540.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28540.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28504.lut1 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28546.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28546.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28567.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28552.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28557.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28560.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28562.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28557.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28565.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28567.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28569.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28571.lut0 (4 -> 3) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28560.lut1 (4 -> 1) + Optimizing lut $abc$25877$auto$blifparse.cc:498:parse_blif$28571.lut1 (4 -> 1) +Removed 0 unused cells and 5990 unused wires. + +2.47. Executing AUTONAME pass. +Renamed 120855 objects in module PQVexRiscvUlx3s (99 iterations). + + +2.48. Executing HIERARCHY pass (managing design hierarchy). + +2.48.1. Analyzing design hierarchy.. +Top module: \PQVexRiscvUlx3s + +2.48.2. Analyzing design hierarchy.. +Top module: \PQVexRiscvUlx3s +Removed 0 unused modules. + +2.49. Printing statistics. + +=== PQVexRiscvUlx3s === + + Number of wires: 4103 + Number of wire bits: 22419 + Number of public wires: 4103 + Number of public wire bits: 22419 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 6522 + CCU2C 260 + DP16KD 64 + L6MUX21 70 + LUT4 3303 + MULT18X18D 4 + PFUMX 512 + TRELLIS_DPR16X4 38 + TRELLIS_FF 2271 + +2.50. Executing CHECK pass (checking for obvious problems). +Checking module PQVexRiscvUlx3s... +Found and reported 0 problems. + +2.51. Executing JSON backend. + +Warnings: 1 unique messages, 2 total +End of script. Logfile hash: 86ff1874c2, CPU: user 11.28s system 0.12s, MEM: 316.02 MB peak +Yosys 0.9+3855 (git sha1 54294957, clang 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 16% 1x abc (2 sec), 15% 28x opt_clean (2 sec), ... diff --git a/ulx3s/ulx3s_v20_constraints.lpf b/ulx3s/ulx3s_v20_constraints.lpf new file mode 100644 index 0000000..0e570d1 --- /dev/null +++ b/ulx3s/ulx3s_v20_constraints.lpf @@ -0,0 +1,452 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.x.x and v3.0.x + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "io_mainClock" SITE "G2"; +IOBUF PORT "io_mainClock" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "io_mainClock" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +# write to FLASH possible any time from JTAG: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; +# write to FLASH possible from user bitstream: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "io_uart_txd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "io_uart_rxd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "io_uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "io_uart_rxd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "io_asyncReset" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "io_asyncReset" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# Output impedance 75 ohm. +# Strong enough to drive 16 ohm earphones. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "io_jtag_tms" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "io_jtag_tdi" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "io_jtag_tdo" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "io_jtag_tck" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "io_jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "io_jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "io_jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "io_jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/vexriscv/PQVexRiscvUlx3s.v b/vexriscv/PQVexRiscvUlx3s.v new file mode 100644 index 0000000..a4af251 --- /dev/null +++ b/vexriscv/PQVexRiscvUlx3s.v @@ -0,0 +1,8225 @@ +// Generator : SpinalHDL v1.4.0 git head : ecb5a80b713566f417ea3ea061f9969e73770a7f +// Date : 27/01/2021, 14:47:17 +// Component : PQVexRiscvUlx3s + + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define JtagState_defaultEncoding_type [3:0] +`define JtagState_defaultEncoding_RESET 4'b0000 +`define JtagState_defaultEncoding_IDLE 4'b0001 +`define JtagState_defaultEncoding_IR_SELECT 4'b0010 +`define JtagState_defaultEncoding_IR_CAPTURE 4'b0011 +`define JtagState_defaultEncoding_IR_SHIFT 4'b0100 +`define JtagState_defaultEncoding_IR_EXIT1 4'b0101 +`define JtagState_defaultEncoding_IR_PAUSE 4'b0110 +`define JtagState_defaultEncoding_IR_EXIT2 4'b0111 +`define JtagState_defaultEncoding_IR_UPDATE 4'b1000 +`define JtagState_defaultEncoding_DR_SELECT 4'b1001 +`define JtagState_defaultEncoding_DR_CAPTURE 4'b1010 +`define JtagState_defaultEncoding_DR_SHIFT 4'b1011 +`define JtagState_defaultEncoding_DR_EXIT1 4'b1100 +`define JtagState_defaultEncoding_DR_PAUSE 4'b1101 +`define JtagState_defaultEncoding_DR_EXIT2 4'b1110 +`define JtagState_defaultEncoding_DR_UPDATE 4'b1111 + +`define UartStopType_defaultEncoding_type [0:0] +`define UartStopType_defaultEncoding_ONE 1'b0 +`define UartStopType_defaultEncoding_TWO 1'b1 + +`define UartParityType_defaultEncoding_type [1:0] +`define UartParityType_defaultEncoding_NONE 2'b00 +`define UartParityType_defaultEncoding_EVEN 2'b01 +`define UartParityType_defaultEncoding_ODD 2'b10 + +`define UartCtrlTxState_defaultEncoding_type [2:0] +`define UartCtrlTxState_defaultEncoding_IDLE 3'b000 +`define UartCtrlTxState_defaultEncoding_START 3'b001 +`define UartCtrlTxState_defaultEncoding_DATA 3'b010 +`define UartCtrlTxState_defaultEncoding_PARITY 3'b011 +`define UartCtrlTxState_defaultEncoding_STOP 3'b100 + +`define UartCtrlRxState_defaultEncoding_type [2:0] +`define UartCtrlRxState_defaultEncoding_IDLE 3'b000 +`define UartCtrlRxState_defaultEncoding_START 3'b001 +`define UartCtrlRxState_defaultEncoding_DATA 3'b010 +`define UartCtrlRxState_defaultEncoding_PARITY 3'b011 +`define UartCtrlRxState_defaultEncoding_STOP 3'b100 + + +module BufferCC ( + input io_initial, + input io_dataIn, + output io_dataOut, + input mainClock, + input resetCtrl_systemClockReset +); + reg buffers_0; + reg buffers_1; + + assign io_dataOut = buffers_1; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + buffers_0 <= io_initial; + buffers_1 <= io_initial; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_1_ ( + input io_dataIn, + output io_dataOut, + input mainClock, + input resetCtrl_mainClockReset +); + reg buffers_0; + reg buffers_1; + + assign io_dataOut = buffers_1; + always @ (posedge mainClock) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module UartCtrlTx ( + input [2:0] io_configFrame_dataLength, + input `UartStopType_defaultEncoding_type io_configFrame_stop, + input `UartParityType_defaultEncoding_type io_configFrame_parity, + input io_samplingTick, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + input io_cts, + output io_txd, + input io_break, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_2_; + wire [0:0] _zz_3_; + wire [2:0] _zz_4_; + wire [0:0] _zz_5_; + wire [2:0] _zz_6_; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg `UartCtrlTxState_defaultEncoding_type stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + reg _zz_1_; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_2_ = (tickCounter_value == io_configFrame_dataLength); + assign _zz_3_ = clockDivider_counter_willIncrement; + assign _zz_4_ = {2'd0, _zz_3_}; + assign _zz_5_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1)); + assign _zz_6_ = {2'd0, _zz_5_}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + `UartStopType_defaultEncoding_ONE : io_configFrame_stop_string = "ONE"; + `UartStopType_defaultEncoding_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + `UartParityType_defaultEncoding_NONE : io_configFrame_parity_string = "NONE"; + `UartParityType_defaultEncoding_EVEN : io_configFrame_parity_string = "EVEN"; + `UartParityType_defaultEncoding_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + `UartCtrlTxState_defaultEncoding_IDLE : stateMachine_state_string = "IDLE "; + `UartCtrlTxState_defaultEncoding_START : stateMachine_state_string = "START "; + `UartCtrlTxState_defaultEncoding_DATA : stateMachine_state_string = "DATA "; + `UartCtrlTxState_defaultEncoding_PARITY : stateMachine_state_string = "PARITY"; + `UartCtrlTxState_defaultEncoding_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @ (*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick)begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == (3'b100)); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @ (*) begin + if(clockDivider_counter_willOverflow)begin + clockDivider_counter_valueNext = (3'b000); + end else begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_4_); + end + if(clockDivider_counter_willClear)begin + clockDivider_counter_valueNext = (3'b000); + end + end + + always @ (*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + `UartCtrlTxState_defaultEncoding_IDLE : begin + end + `UartCtrlTxState_defaultEncoding_START : begin + stateMachine_txd = 1'b0; + end + `UartCtrlTxState_defaultEncoding_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + `UartCtrlTxState_defaultEncoding_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @ (*) begin + io_write_ready = io_break; + case(stateMachine_state) + `UartCtrlTxState_defaultEncoding_IDLE : begin + end + `UartCtrlTxState_defaultEncoding_START : begin + end + `UartCtrlTxState_defaultEncoding_DATA : begin + if(clockDivider_counter_willOverflow)begin + if(_zz_2_)begin + io_write_ready = 1'b1; + end + end + end + `UartCtrlTxState_defaultEncoding_PARITY : begin + end + default : begin + end + endcase + end + + assign io_txd = _zz_1_; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + clockDivider_counter_value <= (3'b000); + stateMachine_state <= `UartCtrlTxState_defaultEncoding_IDLE; + _zz_1_ <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + `UartCtrlTxState_defaultEncoding_IDLE : begin + if(((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow))begin + stateMachine_state <= `UartCtrlTxState_defaultEncoding_START; + end + end + `UartCtrlTxState_defaultEncoding_START : begin + if(clockDivider_counter_willOverflow)begin + stateMachine_state <= `UartCtrlTxState_defaultEncoding_DATA; + end + end + `UartCtrlTxState_defaultEncoding_DATA : begin + if(clockDivider_counter_willOverflow)begin + if(_zz_2_)begin + if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin + stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP; + end else begin + stateMachine_state <= `UartCtrlTxState_defaultEncoding_PARITY; + end + end + end + end + `UartCtrlTxState_defaultEncoding_PARITY : begin + if(clockDivider_counter_willOverflow)begin + stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow)begin + if((tickCounter_value == _zz_6_))begin + stateMachine_state <= (io_write_valid ? `UartCtrlTxState_defaultEncoding_START : `UartCtrlTxState_defaultEncoding_IDLE); + end + end + end + endcase + _zz_1_ <= (stateMachine_txd && (! io_break)); + end + end + + always @ (posedge mainClock) begin + if(clockDivider_counter_willOverflow)begin + tickCounter_value <= (tickCounter_value + (3'b001)); + end + if(clockDivider_counter_willOverflow)begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + `UartCtrlTxState_defaultEncoding_IDLE : begin + end + `UartCtrlTxState_defaultEncoding_START : begin + if(clockDivider_counter_willOverflow)begin + stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD); + tickCounter_value <= (3'b000); + end + end + `UartCtrlTxState_defaultEncoding_DATA : begin + if(clockDivider_counter_willOverflow)begin + if(_zz_2_)begin + tickCounter_value <= (3'b000); + end + end + end + `UartCtrlTxState_defaultEncoding_PARITY : begin + if(clockDivider_counter_willOverflow)begin + tickCounter_value <= (3'b000); + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlRx ( + input [2:0] io_configFrame_dataLength, + input `UartStopType_defaultEncoding_type io_configFrame_stop, + input `UartParityType_defaultEncoding_type io_configFrame_parity, + input io_samplingTick, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + input io_rxd, + output io_rts, + output reg io_error, + output io_break, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_2_; + wire io_rxd_buffercc_io_dataOut; + wire _zz_3_; + wire _zz_4_; + wire _zz_5_; + wire _zz_6_; + wire _zz_7_; + wire [0:0] _zz_8_; + wire [2:0] _zz_9_; + reg _zz_1_; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + reg `UartCtrlRxState_defaultEncoding_type stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_3_ = (stateMachine_parity == sampler_value); + assign _zz_4_ = (! sampler_value); + assign _zz_5_ = (bitTimer_counter == (3'b000)); + assign _zz_6_ = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign _zz_7_ = (bitCounter_value == io_configFrame_dataLength); + assign _zz_8_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1)); + assign _zz_9_ = {2'd0, _zz_8_}; + BufferCC io_rxd_buffercc ( + .io_initial (_zz_2_ ), //i + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + `UartStopType_defaultEncoding_ONE : io_configFrame_stop_string = "ONE"; + `UartStopType_defaultEncoding_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + `UartParityType_defaultEncoding_NONE : io_configFrame_parity_string = "NONE"; + `UartParityType_defaultEncoding_EVEN : io_configFrame_parity_string = "EVEN"; + `UartParityType_defaultEncoding_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + `UartCtrlRxState_defaultEncoding_IDLE : stateMachine_state_string = "IDLE "; + `UartCtrlRxState_defaultEncoding_START : stateMachine_state_string = "START "; + `UartCtrlRxState_defaultEncoding_DATA : stateMachine_state_string = "DATA "; + `UartCtrlRxState_defaultEncoding_PARITY : stateMachine_state_string = "PARITY"; + `UartCtrlRxState_defaultEncoding_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @ (*) begin + io_error = 1'b0; + case(stateMachine_state) + `UartCtrlRxState_defaultEncoding_IDLE : begin + end + `UartCtrlRxState_defaultEncoding_START : begin + end + `UartCtrlRxState_defaultEncoding_DATA : begin + end + `UartCtrlRxState_defaultEncoding_PARITY : begin + if(bitTimer_tick)begin + if(! _zz_3_) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick)begin + if(_zz_4_)begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_1_; + assign _zz_2_ = 1'b0; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @ (*) begin + bitTimer_tick = 1'b0; + if(sampler_tick)begin + if(_zz_5_)begin + bitTimer_tick = 1'b1; + end + end + end + + assign break_valid = (break_counter == 7'h41); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign io_read_payload = stateMachine_shifter; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_1_ <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_1_ <= (! io_read_ready); + if(io_samplingTick)begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick)begin + sampler_samples_2 <= sampler_samples_1; + end + sampler_value <= (((1'b0 || ((1'b1 && sampler_samples_0) && sampler_samples_1)) || ((1'b1 && sampler_samples_0) && sampler_samples_2)) || ((1'b1 && sampler_samples_1) && sampler_samples_2)); + sampler_tick <= io_samplingTick; + if(sampler_value)begin + break_counter <= 7'h0; + end else begin + if((io_samplingTick && (! break_valid)))begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + `UartCtrlRxState_defaultEncoding_IDLE : begin + if(_zz_6_)begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_START; + end + end + `UartCtrlRxState_defaultEncoding_START : begin + if(bitTimer_tick)begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_DATA; + if((sampler_value == 1'b1))begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE; + end + end + end + `UartCtrlRxState_defaultEncoding_DATA : begin + if(bitTimer_tick)begin + if(_zz_7_)begin + if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_PARITY; + end + end + end + end + `UartCtrlRxState_defaultEncoding_PARITY : begin + if(bitTimer_tick)begin + if(_zz_3_)begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE; + end + end + end + default : begin + if(bitTimer_tick)begin + if(_zz_4_)begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE; + end else begin + if((bitCounter_value == _zz_9_))begin + stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE; + end + end + end + end + endcase + end + end + + always @ (posedge mainClock) begin + if(sampler_tick)begin + bitTimer_counter <= (bitTimer_counter - (3'b001)); + if(_zz_5_)begin + bitTimer_counter <= (3'b100); + end + end + if(bitTimer_tick)begin + bitCounter_value <= (bitCounter_value + (3'b001)); + end + if(bitTimer_tick)begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + `UartCtrlRxState_defaultEncoding_IDLE : begin + if(_zz_6_)begin + bitTimer_counter <= (3'b001); + end + end + `UartCtrlRxState_defaultEncoding_START : begin + if(bitTimer_tick)begin + bitCounter_value <= (3'b000); + stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD); + end + end + `UartCtrlRxState_defaultEncoding_DATA : begin + if(bitTimer_tick)begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(_zz_7_)begin + bitCounter_value <= (3'b000); + end + end + end + `UartCtrlRxState_defaultEncoding_PARITY : begin + if(bitTimer_tick)begin + bitCounter_value <= (3'b000); + end + end + default : begin + end + endcase + end + + +endmodule + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_4_; + wire [0:0] _zz_5_; + reg _zz_1_; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2_; + reg [32:0] _zz_3_; + + assign _zz_4_ = (! empty); + assign _zz_5_ = _zz_2_[0 : 0]; + always @ (*) begin + _zz_1_ = 1'b0; + if(pushing)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4_)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2_ = _zz_3_; + always @ (*) begin + if(_zz_4_)begin + io_pop_payload_error = _zz_5_[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4_)begin + io_pop_payload_inst = _zz_2_[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge mainClock) begin + if(_zz_1_)begin + _zz_3_ <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule + +module FlowCCByToggle ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input io_jtag_tck, + input mainClock, + input resetCtrl_mainClockReset +); + wire inputArea_target_buffercc_io_dataOut; + wire outHitSignal; + reg inputArea_target = 0; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_regNext_valid; + reg outputArea_flow_regNext_payload_last; + reg [0:0] outputArea_flow_regNext_payload_fragment; + + BufferCC_1_ inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut ), //o + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_regNext_valid; + assign io_output_payload_last = outputArea_flow_regNext_payload_last; + assign io_output_payload_fragment = outputArea_flow_regNext_payload_fragment; + always @ (posedge io_jtag_tck) begin + if(io_input_valid)begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @ (posedge mainClock) begin + outputArea_hit <= outputArea_target; + outputArea_flow_regNext_payload_last <= outputArea_flow_payload_last; + outputArea_flow_regNext_payload_fragment <= outputArea_flow_payload_fragment; + end + + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + outputArea_flow_regNext_valid <= 1'b0; + end else begin + outputArea_flow_regNext_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module UartCtrl ( + input [2:0] io_config_frame_dataLength, + input `UartStopType_defaultEncoding_type io_config_frame_stop, + input `UartParityType_defaultEncoding_type io_config_frame_parity, + input [19:0] io_config_clockDivider, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + output io_uart_txd, + input io_uart_rxd, + output io_readError, + input io_writeBreak, + output io_readBreak, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_1_; + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0] ), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tick ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (_zz_1_ ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + UartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0] ), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tick ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + `UartStopType_defaultEncoding_ONE : io_config_frame_stop_string = "ONE"; + `UartStopType_defaultEncoding_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + `UartParityType_defaultEncoding_NONE : io_config_frame_parity_string = "NONE"; + `UartParityType_defaultEncoding_EVEN : io_config_frame_parity_string = "EVEN"; + `UartParityType_defaultEncoding_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @ (*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break)begin + io_write_thrown_valid = 1'b0; + end + end + + always @ (*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break)begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign _zz_1_ = 1'b0; + assign io_readBreak = rx_io_break; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + clockDivider_counter <= 20'h0; + end else begin + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick)begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module StreamFifo ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input mainClock, + input resetCtrl_systemClockReset +); + reg [7:0] _zz_3_; + wire [0:0] _zz_4_; + wire [3:0] _zz_5_; + wire [0:0] _zz_6_; + wire [3:0] _zz_7_; + wire [3:0] _zz_8_; + wire _zz_9_; + reg _zz_1_; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_2_; + wire [3:0] logic_ptrDif; + reg [7:0] logic_ram [0:15]; + + assign _zz_4_ = logic_pushPtr_willIncrement; + assign _zz_5_ = {3'd0, _zz_4_}; + assign _zz_6_ = logic_popPtr_willIncrement; + assign _zz_7_ = {3'd0, _zz_6_}; + assign _zz_8_ = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_9_ = 1'b1; + always @ (posedge mainClock) begin + if(_zz_9_) begin + _zz_3_ <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @ (posedge mainClock) begin + if(_zz_1_) begin + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(logic_pushing)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing)begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush)begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == (4'b1111)); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @ (*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_5_); + if(logic_pushPtr_willClear)begin + logic_pushPtr_valueNext = (4'b0000); + end + end + + always @ (*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping)begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush)begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == (4'b1111)); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @ (*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_7_); + if(logic_popPtr_willClear)begin + logic_popPtr_valueNext = (4'b0000); + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_2_ && (! logic_full)))); + assign io_pop_payload = _zz_3_; + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_8_}; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + logic_pushPtr_value <= (4'b0000); + logic_popPtr_value <= (4'b0000); + logic_risingOccupancy <= 1'b0; + _zz_2_ <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_2_ <= (logic_popPtr_valueNext == logic_pushPtr_value); + if((logic_pushing != logic_popping))begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush)begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule +//StreamFifo_1_ replaced by StreamFifo + +module Prescaler ( + input io_clear, + input [15:0] io_limit, + output io_overflow, + input mainClock, + input resetCtrl_systemClockReset +); + reg [15:0] counter; + + assign io_overflow = (counter == io_limit); + always @ (posedge mainClock) begin + counter <= (counter + 16'h0001); + if((io_clear || io_overflow))begin + counter <= 16'h0; + end + end + + +endmodule + +module Timer ( + input io_tick, + input io_clear, + input [15:0] io_limit, + output io_full, + output [15:0] io_value, + input mainClock, + input resetCtrl_systemClockReset +); + wire [0:0] _zz_1_; + wire [15:0] _zz_2_; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_1_ = (! limitHit); + assign _zz_2_ = {15'd0, _zz_1_}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick)begin + inhibitFull <= limitHit; + end + if(io_clear)begin + inhibitFull <= 1'b0; + end + end + end + + always @ (posedge mainClock) begin + if(io_tick)begin + counter <= (counter + _zz_2_); + end + if(io_clear)begin + counter <= 16'h0; + end + end + + +endmodule +//Timer_1_ replaced by Timer + +module InterruptCtrl ( + input [1:0] io_inputs, + input [1:0] io_clears, + input [1:0] io_masks, + output [1:0] io_pendings, + input mainClock, + input resetCtrl_systemClockReset +); + reg [1:0] pendings; + + assign io_pendings = (pendings & io_masks); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + pendings <= (2'b00); + end else begin + pendings <= ((pendings & (~ io_clears)) | io_inputs); + end + end + + +endmodule + +module StreamArbiter ( + input io_inputs_0_valid, + output io_inputs_0_ready, + input io_inputs_0_payload_write, + input [15:0] io_inputs_0_payload_address, + input [31:0] io_inputs_0_payload_data, + input [3:0] io_inputs_0_payload_mask, + input io_inputs_1_valid, + output io_inputs_1_ready, + input io_inputs_1_payload_write, + input [15:0] io_inputs_1_payload_address, + input [31:0] io_inputs_1_payload_data, + input [3:0] io_inputs_1_payload_mask, + output io_output_valid, + input io_output_ready, + output io_output_payload_write, + output [15:0] io_output_payload_address, + output [31:0] io_output_payload_data, + output [3:0] io_output_payload_mask, + output [0:0] io_chosen, + output [1:0] io_chosenOH, + input mainClock, + input resetCtrl_systemClockReset +); + wire [1:0] _zz_3_; + wire [1:0] _zz_4_; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_1_; + wire _zz_2_; + + assign _zz_3_ = (_zz_1_ & (~ _zz_4_)); + assign _zz_4_ = (_zz_1_ - (2'b01)); + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_1_ = {io_inputs_1_valid,io_inputs_0_valid}; + assign maskProposal_0 = io_inputs_0_valid; + assign maskProposal_1 = _zz_3_[1]; + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_write = (maskRouted_0 ? io_inputs_0_payload_write : io_inputs_1_payload_write); + assign io_output_payload_address = (maskRouted_0 ? io_inputs_0_payload_address : io_inputs_1_payload_address); + assign io_output_payload_data = (maskRouted_0 ? io_inputs_0_payload_data : io_inputs_1_payload_data); + assign io_output_payload_mask = (maskRouted_0 ? io_inputs_0_payload_mask : io_inputs_1_payload_mask); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_2_ = io_chosenOH[1]; + assign io_chosen = _zz_2_; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + locked <= 1'b0; + end else begin + if(io_output_valid)begin + locked <= 1'b1; + end + if((io_output_valid && io_output_ready))begin + locked <= 1'b0; + end + end + end + + always @ (posedge mainClock) begin + if(io_output_valid)begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + end + + +endmodule + +module StreamFork ( + input io_input_valid, + output reg io_input_ready, + input io_input_payload_write, + input [15:0] io_input_payload_address, + input [31:0] io_input_payload_data, + input [3:0] io_input_payload_mask, + output io_outputs_0_valid, + input io_outputs_0_ready, + output io_outputs_0_payload_write, + output [15:0] io_outputs_0_payload_address, + output [31:0] io_outputs_0_payload_data, + output [3:0] io_outputs_0_payload_mask, + output io_outputs_1_valid, + input io_outputs_1_ready, + output io_outputs_1_payload_write, + output [15:0] io_outputs_1_payload_address, + output [31:0] io_outputs_1_payload_data, + output [3:0] io_outputs_1_payload_mask, + input mainClock, + input resetCtrl_systemClockReset +); + reg _zz_1_; + reg _zz_2_; + + always @ (*) begin + io_input_ready = 1'b1; + if(((! io_outputs_0_ready) && _zz_1_))begin + io_input_ready = 1'b0; + end + if(((! io_outputs_1_ready) && _zz_2_))begin + io_input_ready = 1'b0; + end + end + + assign io_outputs_0_valid = (io_input_valid && _zz_1_); + assign io_outputs_0_payload_write = io_input_payload_write; + assign io_outputs_0_payload_address = io_input_payload_address; + assign io_outputs_0_payload_data = io_input_payload_data; + assign io_outputs_0_payload_mask = io_input_payload_mask; + assign io_outputs_1_valid = (io_input_valid && _zz_2_); + assign io_outputs_1_payload_write = io_input_payload_write; + assign io_outputs_1_payload_address = io_input_payload_address; + assign io_outputs_1_payload_data = io_input_payload_data; + assign io_outputs_1_payload_mask = io_input_payload_mask; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_1_ <= 1'b1; + _zz_2_ <= 1'b1; + end else begin + if((io_outputs_0_valid && io_outputs_0_ready))begin + _zz_1_ <= 1'b0; + end + if((io_outputs_1_valid && io_outputs_1_ready))begin + _zz_2_ <= 1'b0; + end + if(io_input_ready)begin + _zz_1_ <= 1'b1; + _zz_2_ <= 1'b1; + end + end + end + + +endmodule + +module StreamFifoLowLatency_1_ ( + input io_push_valid, + output io_push_ready, + input [1:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [1:0] io_pop_payload, + input io_flush, + output reg [2:0] io_occupancy, + input mainClock, + input resetCtrl_systemClockReset +); + wire [1:0] _zz_2_; + wire [0:0] _zz_3_; + wire [2:0] _zz_4_; + wire [0:0] _zz_5_; + wire [2:0] _zz_6_; + wire [2:0] _zz_7_; + reg _zz_1_; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + reg [2:0] pushPtr_valueNext; + reg [2:0] pushPtr_value; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + reg [2:0] popPtr_valueNext; + reg [2:0] popPtr_value; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [2:0] ptrDif; + reg [1:0] ram [0:6]; + + assign _zz_3_ = pushPtr_willIncrement; + assign _zz_4_ = {2'd0, _zz_3_}; + assign _zz_5_ = popPtr_willIncrement; + assign _zz_6_ = {2'd0, _zz_5_}; + assign _zz_7_ = ((3'b111) + ptrDif); + assign _zz_2_ = ram[popPtr_value]; + always @ (posedge mainClock) begin + if(_zz_1_) begin + ram[pushPtr_value] <= io_push_payload; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(pushing)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = (pushPtr_value == (3'b110)); + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + if(pushPtr_willOverflow)begin + pushPtr_valueNext = (3'b000); + end else begin + pushPtr_valueNext = (pushPtr_value + _zz_4_); + end + if(pushPtr_willClear)begin + pushPtr_valueNext = (3'b000); + end + end + + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = (popPtr_value == (3'b110)); + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + always @ (*) begin + if(popPtr_willOverflow)begin + popPtr_valueNext = (3'b000); + end else begin + popPtr_valueNext = (popPtr_value + _zz_6_); + end + if(popPtr_willClear)begin + popPtr_valueNext = (3'b000); + end + end + + assign ptrMatch = (pushPtr_value == popPtr_value); + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + assign io_pop_valid = (! empty); + assign io_pop_payload = _zz_2_; + assign ptrDif = (pushPtr_value - popPtr_value); + always @ (*) begin + if(ptrMatch)begin + io_occupancy = (risingOccupancy ? (3'b111) : (3'b000)); + end else begin + io_occupancy = ((popPtr_value < pushPtr_value) ? ptrDif : _zz_7_); + end + end + + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + pushPtr_value <= (3'b000); + popPtr_value <= (3'b000); + risingOccupancy <= 1'b0; + end else begin + pushPtr_value <= pushPtr_valueNext; + popPtr_value <= popPtr_valueNext; + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + +endmodule +//StreamArbiter_1_ replaced by StreamArbiter +//StreamFork_1_ replaced by StreamFork +//StreamFifoLowLatency_2_ replaced by StreamFifoLowLatency_1_ + +module BufferCC_2_ ( + input io_dataIn, + output io_dataOut, + input mainClock +); + reg buffers_0; + reg buffers_1; + + assign io_dataOut = buffers_1; + always @ (posedge mainClock) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module VexRiscv ( + output iBus_cmd_valid, + input iBus_cmd_ready, + output [31:0] iBus_cmd_payload_pc, + input iBus_rsp_valid, + input iBus_rsp_payload_error, + input [31:0] iBus_rsp_payload_inst, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [1:0] dBus_cmd_payload_size, + input dBus_rsp_ready, + input dBus_rsp_error, + input [31:0] dBus_rsp_data, + input mainClock, + input resetCtrl_systemClockReset, + input resetCtrl_mainClockReset +); + wire _zz_135_; + wire _zz_136_; + reg [31:0] _zz_137_; + reg [31:0] _zz_138_; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_139_; + wire _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire _zz_146_; + wire _zz_147_; + wire _zz_148_; + wire _zz_149_; + wire [1:0] _zz_150_; + wire _zz_151_; + wire _zz_152_; + wire _zz_153_; + wire _zz_154_; + wire _zz_155_; + wire _zz_156_; + wire [1:0] _zz_157_; + wire _zz_158_; + wire _zz_159_; + wire [5:0] _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire _zz_163_; + wire _zz_164_; + wire [1:0] _zz_165_; + wire _zz_166_; + wire [1:0] _zz_167_; + wire [0:0] _zz_168_; + wire [0:0] _zz_169_; + wire [0:0] _zz_170_; + wire [0:0] _zz_171_; + wire [0:0] _zz_172_; + wire [32:0] _zz_173_; + wire [31:0] _zz_174_; + wire [32:0] _zz_175_; + wire [0:0] _zz_176_; + wire [0:0] _zz_177_; + wire [47:0] _zz_178_; + wire [47:0] _zz_179_; + wire [0:0] _zz_180_; + wire [0:0] _zz_181_; + wire [30:0] _zz_182_; + wire [30:0] _zz_183_; + wire [30:0] _zz_184_; + wire [0:0] _zz_185_; + wire [0:0] _zz_186_; + wire [0:0] _zz_187_; + wire [0:0] _zz_188_; + wire [0:0] _zz_189_; + wire [0:0] _zz_190_; + wire [0:0] _zz_191_; + wire [1:0] _zz_192_; + wire [1:0] _zz_193_; + wire [2:0] _zz_194_; + wire [31:0] _zz_195_; + wire [2:0] _zz_196_; + wire [0:0] _zz_197_; + wire [2:0] _zz_198_; + wire [0:0] _zz_199_; + wire [2:0] _zz_200_; + wire [0:0] _zz_201_; + wire [2:0] _zz_202_; + wire [0:0] _zz_203_; + wire [2:0] _zz_204_; + wire [4:0] _zz_205_; + wire [11:0] _zz_206_; + wire [11:0] _zz_207_; + wire [31:0] _zz_208_; + wire [31:0] _zz_209_; + wire [31:0] _zz_210_; + wire [31:0] _zz_211_; + wire [31:0] _zz_212_; + wire [31:0] _zz_213_; + wire [31:0] _zz_214_; + wire [19:0] _zz_215_; + wire [11:0] _zz_216_; + wire [11:0] _zz_217_; + wire [32:0] _zz_218_; + wire [31:0] _zz_219_; + wire [31:0] _zz_220_; + wire [31:0] _zz_221_; + wire [0:0] _zz_222_; + wire [5:0] _zz_223_; + wire [32:0] _zz_224_; + wire [31:0] _zz_225_; + wire [31:0] _zz_226_; + wire [32:0] _zz_227_; + wire [32:0] _zz_228_; + wire [32:0] _zz_229_; + wire [32:0] _zz_230_; + wire [0:0] _zz_231_; + wire [32:0] _zz_232_; + wire [0:0] _zz_233_; + wire [32:0] _zz_234_; + wire [0:0] _zz_235_; + wire [31:0] _zz_236_; + wire [0:0] _zz_237_; + wire [0:0] _zz_238_; + wire [0:0] _zz_239_; + wire [0:0] _zz_240_; + wire [0:0] _zz_241_; + wire [0:0] _zz_242_; + wire [0:0] _zz_243_; + wire [0:0] _zz_244_; + wire [0:0] _zz_245_; + wire _zz_246_; + wire _zz_247_; + wire [31:0] _zz_248_; + wire _zz_249_; + wire [0:0] _zz_250_; + wire [1:0] _zz_251_; + wire _zz_252_; + wire [0:0] _zz_253_; + wire [0:0] _zz_254_; + wire _zz_255_; + wire [0:0] _zz_256_; + wire [23:0] _zz_257_; + wire [31:0] _zz_258_; + wire [31:0] _zz_259_; + wire [31:0] _zz_260_; + wire _zz_261_; + wire _zz_262_; + wire [1:0] _zz_263_; + wire [1:0] _zz_264_; + wire _zz_265_; + wire [0:0] _zz_266_; + wire [20:0] _zz_267_; + wire [31:0] _zz_268_; + wire [31:0] _zz_269_; + wire [31:0] _zz_270_; + wire [31:0] _zz_271_; + wire [0:0] _zz_272_; + wire [0:0] _zz_273_; + wire [0:0] _zz_274_; + wire [0:0] _zz_275_; + wire _zz_276_; + wire [0:0] _zz_277_; + wire [17:0] _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [2:0] _zz_284_; + wire [2:0] _zz_285_; + wire _zz_286_; + wire [0:0] _zz_287_; + wire [14:0] _zz_288_; + wire [31:0] _zz_289_; + wire [31:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire _zz_293_; + wire _zz_294_; + wire _zz_295_; + wire [0:0] _zz_296_; + wire [0:0] _zz_297_; + wire [0:0] _zz_298_; + wire [3:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire _zz_302_; + wire [0:0] _zz_303_; + wire [11:0] _zz_304_; + wire [31:0] _zz_305_; + wire [31:0] _zz_306_; + wire [31:0] _zz_307_; + wire [31:0] _zz_308_; + wire [31:0] _zz_309_; + wire [31:0] _zz_310_; + wire [31:0] _zz_311_; + wire _zz_312_; + wire [0:0] _zz_313_; + wire [1:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire _zz_317_; + wire [0:0] _zz_318_; + wire [0:0] _zz_319_; + wire _zz_320_; + wire [0:0] _zz_321_; + wire [9:0] _zz_322_; + wire [31:0] _zz_323_; + wire [31:0] _zz_324_; + wire [31:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire _zz_329_; + wire [0:0] _zz_330_; + wire [2:0] _zz_331_; + wire [0:0] _zz_332_; + wire [0:0] _zz_333_; + wire [5:0] _zz_334_; + wire [5:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [6:0] _zz_338_; + wire [31:0] _zz_339_; + wire _zz_340_; + wire [0:0] _zz_341_; + wire [0:0] _zz_342_; + wire [31:0] _zz_343_; + wire [31:0] _zz_344_; + wire [31:0] _zz_345_; + wire [31:0] _zz_346_; + wire [0:0] _zz_347_; + wire [3:0] _zz_348_; + wire _zz_349_; + wire [1:0] _zz_350_; + wire [1:0] _zz_351_; + wire _zz_352_; + wire [0:0] _zz_353_; + wire [4:0] _zz_354_; + wire [31:0] _zz_355_; + wire [31:0] _zz_356_; + wire [31:0] _zz_357_; + wire [31:0] _zz_358_; + wire [31:0] _zz_359_; + wire [31:0] _zz_360_; + wire [31:0] _zz_361_; + wire _zz_362_; + wire [0:0] _zz_363_; + wire [1:0] _zz_364_; + wire [31:0] _zz_365_; + wire _zz_366_; + wire [0:0] _zz_367_; + wire [0:0] _zz_368_; + wire [1:0] _zz_369_; + wire [1:0] _zz_370_; + wire _zz_371_; + wire [0:0] _zz_372_; + wire [2:0] _zz_373_; + wire [31:0] _zz_374_; + wire [31:0] _zz_375_; + wire [31:0] _zz_376_; + wire _zz_377_; + wire _zz_378_; + wire [31:0] _zz_379_; + wire [31:0] _zz_380_; + wire [31:0] _zz_381_; + wire _zz_382_; + wire [0:0] _zz_383_; + wire [0:0] _zz_384_; + wire [1:0] _zz_385_; + wire [1:0] _zz_386_; + wire _zz_387_; + wire [0:0] _zz_388_; + wire [0:0] _zz_389_; + wire [31:0] _zz_390_; + wire [31:0] _zz_391_; + wire [31:0] _zz_392_; + wire [31:0] _zz_393_; + wire [31:0] _zz_394_; + wire [31:0] _zz_395_; + wire [31:0] _zz_396_; + wire _zz_397_; + wire _zz_398_; + wire decode_MEMORY_ENABLE; + wire execute_BRANCH_DO; + wire decode_IS_RS2_SIGNED; + wire [31:0] execute_MUL_HH; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_1_; + wire `AluCtrlEnum_defaultEncoding_type _zz_2_; + wire `AluCtrlEnum_defaultEncoding_type _zz_3_; + wire decode_IS_CSR; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_DIV; + wire [31:0] execute_MUL_LH; + wire decode_MEMORY_STORE; + wire [31:0] execute_MUL_HL; + wire [31:0] execute_BRANCH_CALC; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] memory_PC; + wire decode_IS_RS1_SIGNED; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [63:0] memory_MUL; + wire [31:0] memory_SRC2; + wire [31:0] decode_SRC2; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_7_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_DO_EBREAK; + wire [31:0] memory_SRC1; + wire [31:0] decode_SRC1; + wire decode_SRC_LESS_UNSIGNED; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_19_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] execute_MUL_LL; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire [63:0] writeBack_MUL; + wire writeBack_IS_MUL; + wire [31:0] writeBack_SRC2; + wire [31:0] writeBack_SRC1; + wire [31:0] memory_MUL_HH; + wire [31:0] memory_MUL_HL; + wire [31:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_22_; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_23_; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_25_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_26_; + wire [31:0] _zz_27_; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_28_; + wire [31:0] _zz_29_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_30_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_31_; + wire [31:0] execute_SRC2; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32_; + wire [31:0] _zz_33_; + wire _zz_34_; + reg _zz_35_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire `AluCtrlEnum_defaultEncoding_type _zz_36_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_37_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_39_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_41_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_42_; + reg [31:0] _zz_43_; + wire [31:0] execute_SRC1; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_44_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_45_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_46_; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_47_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + reg [31:0] _zz_48_; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg IBusSimplePlugin_injectionPort_valid; + reg IBusSimplePlugin_injectionPort_ready; + wire [31:0] IBusSimplePlugin_injectionPort_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [1:0] _zz_49_; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_fetchPc_flushed; + wire IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_1_halt; + wire IBusSimplePlugin_iBusRsp_stages_2_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_halt; + wire _zz_50_; + wire _zz_51_; + wire _zz_52_; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_53_; + wire _zz_54_; + reg _zz_55_; + wire _zz_56_; + reg _zz_57_; + reg [31:0] _zz_58_; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_59_; + reg [31:0] _zz_60_; + reg _zz_61_; + reg [31:0] _zz_62_; + reg _zz_63_; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg IBusSimplePlugin_injector_nextPcCalc_valids_5; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_64_; + wire _zz_65_; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_66_; + reg [3:0] _zz_67_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_68_; + reg [31:0] _zz_69_; + wire _zz_70_; + reg [31:0] _zz_71_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_72_; + wire _zz_73_; + wire _zz_74_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + wire [1:0] CsrPlugin_targetPrivilege; + wire [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire [29:0] _zz_75_; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_81_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_82_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_83_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_84_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_85_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_86_; + wire `AluCtrlEnum_defaultEncoding_type _zz_87_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_88_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_89_; + reg [31:0] _zz_90_; + wire _zz_91_; + reg [19:0] _zz_92_; + wire _zz_93_; + reg [19:0] _zz_94_; + reg [31:0] _zz_95_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_96_; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_97_; + reg _zz_98_; + reg _zz_99_; + reg _zz_100_; + reg [4:0] _zz_101_; + reg [31:0] _zz_102_; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire _zz_107_; + wire _zz_108_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_109_; + reg _zz_110_; + reg _zz_111_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_112_; + reg [10:0] _zz_113_; + wire _zz_114_; + reg [19:0] _zz_115_; + wire _zz_116_; + reg [18:0] _zz_117_; + reg [31:0] _zz_118_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [31:0] execute_Mul16Plugin_a; + wire [31:0] execute_Mul16Plugin_b; + wire [15:0] execute_Mul16Plugin_aLow; + wire [15:0] execute_Mul16Plugin_bLow; + wire [15:0] execute_Mul16Plugin_aHigh; + wire [15:0] execute_Mul16Plugin_bHigh; + wire [31:0] memory_Mul16Plugin_ll; + wire [32:0] memory_Mul16Plugin_lh; + wire [31:0] memory_Mul16Plugin_hl; + wire [31:0] memory_Mul16Plugin_hh; + wire [32:0] memory_Mul16Plugin_hllh; + reg writeBack_Mul16Plugin_aSigned; + reg writeBack_Mul16Plugin_bSigned; + wire [31:0] writeBack_Mul16Plugin_a; + wire [31:0] writeBack_Mul16Plugin_b; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_119_; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_120_; + wire _zz_121_; + wire _zz_122_; + reg [32:0] _zz_123_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_124_; + reg DebugPlugin_resetIt_regNext; + reg [31:0] execute_to_memory_MUL_LL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] decode_to_execute_RS2; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] execute_to_memory_SRC1; + reg [31:0] memory_to_writeBack_SRC1; + reg decode_to_execute_DO_EBREAK; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_SRC2; + reg [31:0] execute_to_memory_SRC2; + reg [31:0] memory_to_writeBack_SRC2; + reg [63:0] memory_to_writeBack_MUL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_IS_RS1_SIGNED; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg [31:0] execute_to_memory_MUL_HL; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg [31:0] execute_to_memory_MUL_LH; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg decode_to_execute_IS_CSR; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_MUL_HH; + reg decode_to_execute_IS_RS2_SIGNED; + reg execute_to_memory_BRANCH_DO; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg [31:0] decode_to_execute_RS1; + reg [2:0] _zz_125_; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg [31:0] _zz_126_; + reg [31:0] _zz_127_; + reg [31:0] _zz_128_; + reg [31:0] _zz_129_; + reg [31:0] _zz_130_; + reg [31:0] _zz_131_; + reg [31:0] _zz_132_; + reg [31:0] _zz_133_; + reg [31:0] _zz_134_; + `ifndef SYNTHESIS + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_1__string; + reg [63:0] _zz_2__string; + reg [63:0] _zz_3__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_7__string; + reg [31:0] _zz_8__string; + reg [31:0] _zz_9__string; + reg [71:0] _zz_10__string; + reg [71:0] _zz_11__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12__string; + reg [71:0] _zz_13__string; + reg [71:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [31:0] _zz_16__string; + reg [31:0] _zz_17__string; + reg [31:0] _zz_18__string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_19__string; + reg [31:0] _zz_20__string; + reg [31:0] _zz_21__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_22__string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_24__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_25__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_28__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_30__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_31__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_32__string; + reg [63:0] _zz_36__string; + reg [31:0] _zz_37__string; + reg [71:0] _zz_38__string; + reg [31:0] _zz_39__string; + reg [23:0] _zz_40__string; + reg [95:0] _zz_41__string; + reg [39:0] _zz_42__string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_44__string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_45__string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_46__string; + reg [39:0] _zz_81__string; + reg [95:0] _zz_82__string; + reg [23:0] _zz_83__string; + reg [31:0] _zz_84__string; + reg [71:0] _zz_85__string; + reg [31:0] _zz_86__string; + reg [63:0] _zz_87__string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_139_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_140_ = 1'b1; + assign _zz_141_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_142_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_143_ = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_144_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_145_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_146_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); + assign _zz_147_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_148_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_149_ = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign _zz_150_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_151_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_152_ = (1'b0 || (! 1'b1)); + assign _zz_153_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_154_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_155_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_156_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_157_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_158_ = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_159_ = (! memory_arbitration_isStuck); + assign _zz_160_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_161_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_162_ = ((_zz_72_ && 1'b1) && (! 1'b0)); + assign _zz_163_ = ((_zz_73_ && 1'b1) && (! 1'b0)); + assign _zz_164_ = ((_zz_74_ && 1'b1) && (! 1'b0)); + assign _zz_165_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_166_ = execute_INSTRUCTION[13]; + assign _zz_167_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_168_ = _zz_75_[12 : 12]; + assign _zz_169_ = _zz_75_[19 : 19]; + assign _zz_170_ = _zz_75_[10 : 10]; + assign _zz_171_ = _zz_75_[29 : 29]; + assign _zz_172_ = _zz_75_[0 : 0]; + assign _zz_173_ = ($signed(_zz_175_) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_174_ = _zz_173_[31 : 0]; + assign _zz_175_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_176_ = _zz_75_[22 : 22]; + assign _zz_177_ = _zz_75_[15 : 15]; + assign _zz_178_ = ({memory_Mul16Plugin_hh,memory_Mul16Plugin_ll[31 : 16]} + _zz_179_); + assign _zz_179_ = {15'd0, memory_Mul16Plugin_hllh}; + assign _zz_180_ = _zz_75_[14 : 14]; + assign _zz_181_ = _zz_75_[11 : 11]; + assign _zz_182_ = (decode_PC >>> 1); + assign _zz_183_ = (decode_PC >>> 1); + assign _zz_184_ = (decode_PC >>> 1); + assign _zz_185_ = _zz_75_[3 : 3]; + assign _zz_186_ = _zz_75_[8 : 8]; + assign _zz_187_ = _zz_75_[23 : 23]; + assign _zz_188_ = _zz_75_[28 : 28]; + assign _zz_189_ = _zz_75_[16 : 16]; + assign _zz_190_ = _zz_75_[20 : 20]; + assign _zz_191_ = _zz_75_[9 : 9]; + assign _zz_192_ = (_zz_49_ & (~ _zz_193_)); + assign _zz_193_ = (_zz_49_ - (2'b01)); + assign _zz_194_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; + assign _zz_195_ = {29'd0, _zz_194_}; + assign _zz_196_ = (IBusSimplePlugin_pending_value + _zz_198_); + assign _zz_197_ = IBusSimplePlugin_pending_inc; + assign _zz_198_ = {2'd0, _zz_197_}; + assign _zz_199_ = IBusSimplePlugin_pending_dec; + assign _zz_200_ = {2'd0, _zz_199_}; + assign _zz_201_ = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000))); + assign _zz_202_ = {2'd0, _zz_201_}; + assign _zz_203_ = execute_SRC_LESS; + assign _zz_204_ = (3'b100); + assign _zz_205_ = decode_INSTRUCTION[19 : 15]; + assign _zz_206_ = decode_INSTRUCTION[31 : 20]; + assign _zz_207_ = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_208_ = ($signed(_zz_209_) + $signed(_zz_212_)); + assign _zz_209_ = ($signed(_zz_210_) + $signed(_zz_211_)); + assign _zz_210_ = execute_SRC1; + assign _zz_211_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_212_ = (execute_SRC_USE_SUB_LESS ? _zz_213_ : _zz_214_); + assign _zz_213_ = 32'h00000001; + assign _zz_214_ = 32'h0; + assign _zz_215_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_216_ = execute_INSTRUCTION[31 : 20]; + assign _zz_217_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_218_ = {1'd0, memory_Mul16Plugin_hl}; + assign _zz_219_ = (_zz_220_ + _zz_221_); + assign _zz_220_ = (writeBack_MUL[63 : 32] + (~ writeBack_Mul16Plugin_a)); + assign _zz_221_ = ((~ writeBack_Mul16Plugin_b) + 32'h00000002); + assign _zz_222_ = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_223_ = {5'd0, _zz_222_}; + assign _zz_224_ = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_225_ = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_226_ = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_227_ = {_zz_119_,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_228_ = _zz_229_; + assign _zz_229_ = _zz_230_; + assign _zz_230_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_120_) : _zz_120_)} + _zz_232_); + assign _zz_231_ = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_232_ = {32'd0, _zz_231_}; + assign _zz_233_ = _zz_122_; + assign _zz_234_ = {32'd0, _zz_233_}; + assign _zz_235_ = _zz_121_; + assign _zz_236_ = {31'd0, _zz_235_}; + assign _zz_237_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_238_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_239_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_240_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_241_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_242_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_243_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_244_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_245_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_246_ = 1'b1; + assign _zz_247_ = 1'b1; + assign _zz_248_ = 32'h02004064; + assign _zz_249_ = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_250_ = ((decode_INSTRUCTION & _zz_258_) == 32'h0); + assign _zz_251_ = {_zz_80_,(_zz_259_ == _zz_260_)}; + assign _zz_252_ = ((decode_INSTRUCTION & 32'h00004004) == 32'h00004000); + assign _zz_253_ = _zz_80_; + assign _zz_254_ = (1'b0); + assign _zz_255_ = ({_zz_78_,_zz_261_} != (2'b00)); + assign _zz_256_ = (_zz_262_ != (1'b0)); + assign _zz_257_ = {(_zz_263_ != _zz_264_),{_zz_265_,{_zz_266_,_zz_267_}}}; + assign _zz_258_ = 32'h00000018; + assign _zz_259_ = (decode_INSTRUCTION & 32'h00005004); + assign _zz_260_ = 32'h00001000; + assign _zz_261_ = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_262_ = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_263_ = {(_zz_268_ == _zz_269_),(_zz_270_ == _zz_271_)}; + assign _zz_264_ = (2'b00); + assign _zz_265_ = (_zz_79_ != (1'b0)); + assign _zz_266_ = ({_zz_272_,_zz_273_} != (2'b00)); + assign _zz_267_ = {(_zz_274_ != _zz_275_),{_zz_276_,{_zz_277_,_zz_278_}}}; + assign _zz_268_ = (decode_INSTRUCTION & 32'h00000034); + assign _zz_269_ = 32'h00000020; + assign _zz_270_ = (decode_INSTRUCTION & 32'h00000064); + assign _zz_271_ = 32'h00000020; + assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == 32'h00000040); + assign _zz_273_ = ((decode_INSTRUCTION & _zz_280_) == 32'h00000040); + assign _zz_274_ = ((decode_INSTRUCTION & _zz_281_) == 32'h00000024); + assign _zz_275_ = (1'b0); + assign _zz_276_ = (_zz_79_ != (1'b0)); + assign _zz_277_ = ({_zz_282_,_zz_283_} != (2'b00)); + assign _zz_278_ = {(_zz_284_ != _zz_285_),{_zz_286_,{_zz_287_,_zz_288_}}}; + assign _zz_279_ = 32'h00000050; + assign _zz_280_ = 32'h00103040; + assign _zz_281_ = 32'h00000064; + assign _zz_282_ = ((decode_INSTRUCTION & _zz_289_) == 32'h00005010); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_290_) == 32'h00005020); + assign _zz_284_ = {(_zz_291_ == _zz_292_),{_zz_293_,_zz_294_}}; + assign _zz_285_ = (3'b000); + assign _zz_286_ = ({_zz_295_,{_zz_296_,_zz_297_}} != (3'b000)); + assign _zz_287_ = ({_zz_298_,_zz_299_} != 5'h0); + assign _zz_288_ = {(_zz_300_ != _zz_301_),{_zz_302_,{_zz_303_,_zz_304_}}}; + assign _zz_289_ = 32'h00007034; + assign _zz_290_ = 32'h02007064; + assign _zz_291_ = (decode_INSTRUCTION & 32'h40003054); + assign _zz_292_ = 32'h40001010; + assign _zz_293_ = ((decode_INSTRUCTION & _zz_305_) == 32'h00001010); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_306_) == 32'h00001010); + assign _zz_295_ = ((decode_INSTRUCTION & _zz_307_) == 32'h00000040); + assign _zz_296_ = (_zz_308_ == _zz_309_); + assign _zz_297_ = (_zz_310_ == _zz_311_); + assign _zz_298_ = _zz_77_; + assign _zz_299_ = {_zz_312_,{_zz_313_,_zz_314_}}; + assign _zz_300_ = (_zz_315_ == _zz_316_); + assign _zz_301_ = (1'b0); + assign _zz_302_ = (_zz_317_ != (1'b0)); + assign _zz_303_ = (_zz_318_ != _zz_319_); + assign _zz_304_ = {_zz_320_,{_zz_321_,_zz_322_}}; + assign _zz_305_ = 32'h00007034; + assign _zz_306_ = 32'h02007054; + assign _zz_307_ = 32'h00000044; + assign _zz_308_ = (decode_INSTRUCTION & 32'h00002014); + assign _zz_309_ = 32'h00002010; + assign _zz_310_ = (decode_INSTRUCTION & 32'h40000034); + assign _zz_311_ = 32'h40000030; + assign _zz_312_ = ((decode_INSTRUCTION & 32'h00002030) == 32'h00002010); + assign _zz_313_ = ((decode_INSTRUCTION & _zz_323_) == 32'h00000010); + assign _zz_314_ = {(_zz_324_ == _zz_325_),(_zz_326_ == _zz_327_)}; + assign _zz_315_ = (decode_INSTRUCTION & 32'h02004074); + assign _zz_316_ = 32'h02000030; + assign _zz_317_ = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_318_ = ((decode_INSTRUCTION & _zz_328_) == 32'h0); + assign _zz_319_ = (1'b0); + assign _zz_320_ = ({_zz_329_,{_zz_330_,_zz_331_}} != 5'h0); + assign _zz_321_ = ({_zz_332_,_zz_333_} != (2'b00)); + assign _zz_322_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_323_ = 32'h00001030; + assign _zz_324_ = (decode_INSTRUCTION & 32'h02002060); + assign _zz_325_ = 32'h00002020; + assign _zz_326_ = (decode_INSTRUCTION & 32'h02003020); + assign _zz_327_ = 32'h00000020; + assign _zz_328_ = 32'h00000058; + assign _zz_329_ = ((decode_INSTRUCTION & _zz_339_) == 32'h00000040); + assign _zz_330_ = _zz_77_; + assign _zz_331_ = {_zz_340_,{_zz_341_,_zz_342_}}; + assign _zz_332_ = (_zz_343_ == _zz_344_); + assign _zz_333_ = (_zz_345_ == _zz_346_); + assign _zz_334_ = {_zz_78_,{_zz_347_,_zz_348_}}; + assign _zz_335_ = 6'h0; + assign _zz_336_ = (_zz_349_ != (1'b0)); + assign _zz_337_ = (_zz_350_ != _zz_351_); + assign _zz_338_ = {_zz_352_,{_zz_353_,_zz_354_}}; + assign _zz_339_ = 32'h00000040; + assign _zz_340_ = ((decode_INSTRUCTION & _zz_355_) == 32'h00004020); + assign _zz_341_ = (_zz_356_ == _zz_357_); + assign _zz_342_ = (_zz_358_ == _zz_359_); + assign _zz_343_ = (decode_INSTRUCTION & 32'h00001050); + assign _zz_344_ = 32'h00001050; + assign _zz_345_ = (decode_INSTRUCTION & 32'h00002050); + assign _zz_346_ = 32'h00002050; + assign _zz_347_ = (_zz_360_ == _zz_361_); + assign _zz_348_ = {_zz_362_,{_zz_363_,_zz_364_}}; + assign _zz_349_ = ((decode_INSTRUCTION & _zz_365_) == 32'h00000050); + assign _zz_350_ = {_zz_77_,_zz_366_}; + assign _zz_351_ = (2'b00); + assign _zz_352_ = ({_zz_367_,_zz_368_} != (2'b00)); + assign _zz_353_ = (_zz_369_ != _zz_370_); + assign _zz_354_ = {_zz_371_,{_zz_372_,_zz_373_}}; + assign _zz_355_ = 32'h00004020; + assign _zz_356_ = (decode_INSTRUCTION & 32'h00000030); + assign _zz_357_ = 32'h00000010; + assign _zz_358_ = (decode_INSTRUCTION & 32'h02000020); + assign _zz_359_ = 32'h00000020; + assign _zz_360_ = (decode_INSTRUCTION & 32'h00001010); + assign _zz_361_ = 32'h00001010; + assign _zz_362_ = ((decode_INSTRUCTION & _zz_374_) == 32'h00002010); + assign _zz_363_ = (_zz_375_ == _zz_376_); + assign _zz_364_ = {_zz_377_,_zz_378_}; + assign _zz_365_ = 32'h10003050; + assign _zz_366_ = ((decode_INSTRUCTION & _zz_379_) == 32'h00000020); + assign _zz_367_ = _zz_77_; + assign _zz_368_ = (_zz_380_ == _zz_381_); + assign _zz_369_ = {_zz_382_,_zz_76_}; + assign _zz_370_ = (2'b00); + assign _zz_371_ = ({_zz_383_,_zz_384_} != (2'b00)); + assign _zz_372_ = (_zz_385_ != _zz_386_); + assign _zz_373_ = {_zz_387_,{_zz_388_,_zz_389_}}; + assign _zz_374_ = 32'h00002010; + assign _zz_375_ = (decode_INSTRUCTION & 32'h00000050); + assign _zz_376_ = 32'h00000010; + assign _zz_377_ = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_378_ = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_379_ = 32'h00000070; + assign _zz_380_ = (decode_INSTRUCTION & 32'h00000020); + assign _zz_381_ = 32'h0; + assign _zz_382_ = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_383_ = ((decode_INSTRUCTION & _zz_390_) == 32'h00000004); + assign _zz_384_ = _zz_76_; + assign _zz_385_ = {(_zz_391_ == _zz_392_),(_zz_393_ == _zz_394_)}; + assign _zz_386_ = (2'b00); + assign _zz_387_ = ((_zz_395_ == _zz_396_) != (1'b0)); + assign _zz_388_ = (_zz_397_ != (1'b0)); + assign _zz_389_ = (_zz_398_ != (1'b0)); + assign _zz_390_ = 32'h00000044; + assign _zz_391_ = (decode_INSTRUCTION & 32'h00002010); + assign _zz_392_ = 32'h00002000; + assign _zz_393_ = (decode_INSTRUCTION & 32'h00005000); + assign _zz_394_ = 32'h00001000; + assign _zz_395_ = (decode_INSTRUCTION & 32'h00001000); + assign _zz_396_ = 32'h00001000; + assign _zz_397_ = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_398_ = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + always @ (posedge mainClock) begin + if(_zz_246_) begin + _zz_137_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge mainClock) begin + if(_zz_247_) begin + _zz_138_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge mainClock) begin + if(_zz_35_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_135_ ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_136_ ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE "; + default : _zz_1__string = "????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE "; + default : _zz_2__string = "????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE "; + default : _zz_3__string = "????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_7_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_7__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_7__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_7__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_7__string = "JALR"; + default : _zz_7__string = "????"; + endcase + end + always @(*) begin + case(_zz_8_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8__string = "JALR"; + default : _zz_8__string = "????"; + endcase + end + always @(*) begin + case(_zz_9_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9__string = "JALR"; + default : _zz_9__string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 "; + default : _zz_10__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; + default : _zz_11__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; + default : _zz_12__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14__string = "SRA_1 "; + default : _zz_14__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET"; + default : _zz_16__string = "????"; + endcase + end + always @(*) begin + case(_zz_17_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET"; + default : _zz_17__string = "????"; + endcase + end + always @(*) begin + case(_zz_18_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET"; + default : _zz_18__string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_19_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET"; + default : _zz_19__string = "????"; + endcase + end + always @(*) begin + case(_zz_20_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET"; + default : _zz_20__string = "????"; + endcase + end + always @(*) begin + case(_zz_21_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET"; + default : _zz_21__string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_22_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_22__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_22__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_22__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_22__string = "JALR"; + default : _zz_22__string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_24_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; + default : _zz_24__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_25_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_25__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_25__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_25__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_25__string = "SRA_1 "; + default : _zz_25__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_28_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_28__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_28__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_28__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_28__string = "PC "; + default : _zz_28__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_30_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_30__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_30__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_30__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_30__string = "URS1 "; + default : _zz_30__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_31_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_31__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_31__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_31__string = "BITWISE "; + default : _zz_31__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32__string = "AND_1"; + default : _zz_32__string = "?????"; + endcase + end + always @(*) begin + case(_zz_36_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36__string = "BITWISE "; + default : _zz_36__string = "????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_37__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_37__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_37__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_37__string = "JALR"; + default : _zz_37__string = "????"; + endcase + end + always @(*) begin + case(_zz_38_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1 "; + default : _zz_38__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_39__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_39__string = "XRET"; + default : _zz_39__string = "????"; + endcase + end + always @(*) begin + case(_zz_40_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; + default : _zz_40__string = "???"; + endcase + end + always @(*) begin + case(_zz_41_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41__string = "URS1 "; + default : _zz_41__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_42_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_42__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_42__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_42__string = "AND_1"; + default : _zz_42__string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_44_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_44__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_44__string = "XRET"; + default : _zz_44__string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_45_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_45__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_45__string = "XRET"; + default : _zz_45__string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_46_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_46__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_46__string = "XRET"; + default : _zz_46__string = "????"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81__string = "AND_1"; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(_zz_82_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_82__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_82__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_82__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_82__string = "URS1 "; + default : _zz_82__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_83_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_83__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_83__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_83__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_83__string = "PC "; + default : _zz_83__string = "???"; + endcase + end + always @(*) begin + case(_zz_84_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_84__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_84__string = "XRET"; + default : _zz_84__string = "????"; + endcase + end + always @(*) begin + case(_zz_85_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_85__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_85__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_85__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_85__string = "SRA_1 "; + default : _zz_85__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_86_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_86__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_86__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_86__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_86__string = "JALR"; + default : _zz_86__string = "????"; + endcase + end + always @(*) begin + case(_zz_87_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_87__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_87__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_87__string = "BITWISE "; + default : _zz_87__string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + `endif + + assign decode_MEMORY_ENABLE = _zz_168_[0]; + assign execute_BRANCH_DO = _zz_111_; + assign decode_IS_RS2_SIGNED = _zz_169_[0]; + assign execute_MUL_HH = (execute_Mul16Plugin_aHigh * execute_Mul16Plugin_bHigh); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign decode_ALU_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_IS_CSR = _zz_170_[0]; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_DIV = _zz_171_[0]; + assign execute_MUL_LH = (execute_Mul16Plugin_aLow * execute_Mul16Plugin_bHigh); + assign decode_MEMORY_STORE = _zz_172_[0]; + assign execute_MUL_HL = (execute_Mul16Plugin_aHigh * execute_Mul16Plugin_bLow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign execute_SHIFT_RIGHT = _zz_174_; + assign memory_PC = execute_to_memory_PC; + assign decode_IS_RS1_SIGNED = _zz_176_[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_177_[0]; + assign memory_MUL = {_zz_178_,memory_Mul16Plugin_ll[15 : 0]}; + assign memory_SRC2 = execute_to_memory_SRC2; + assign decode_SRC2 = _zz_95_; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_180_[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_181_[0]; + assign decode_BRANCH_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || (((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_182_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_183_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_184_))))); + assign memory_SRC1 = execute_to_memory_SRC1; + assign decode_SRC1 = _zz_90_; + assign decode_SRC_LESS_UNSIGNED = _zz_185_[0]; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_89_; + assign _zz_10_ = _zz_11_; + assign decode_SHIFT_CTRL = _zz_12_; + assign _zz_13_ = _zz_14_; + assign _zz_15_ = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ENV_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_MUL_LL = (execute_Mul16Plugin_aLow * execute_Mul16Plugin_bLow); + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_186_[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_MUL = memory_to_writeBack_MUL; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_SRC2 = memory_to_writeBack_SRC2; + assign writeBack_SRC1 = memory_to_writeBack_SRC1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_22_; + assign decode_RS2_USE = _zz_187_[0]; + assign decode_RS1_USE = _zz_188_[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_100_)begin + if((_zz_101_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_102_; + end + end + if(_zz_139_)begin + if(_zz_140_)begin + if(_zz_104_)begin + decode_RS2 = _zz_47_; + end + end + end + if(_zz_141_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_106_)begin + decode_RS2 = _zz_23_; + end + end + end + if(_zz_142_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_108_)begin + decode_RS2 = _zz_43_; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_100_)begin + if((_zz_101_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_102_; + end + end + if(_zz_139_)begin + if(_zz_140_)begin + if(_zz_103_)begin + decode_RS1 = _zz_47_; + end + end + end + if(_zz_141_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_105_)begin + decode_RS1 = _zz_23_; + end + end + end + if(_zz_142_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_107_)begin + decode_RS1 = _zz_43_; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_23_ = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_23_ = _zz_97_; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_23_ = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_143_)begin + _zz_23_ = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_24_; + assign execute_SHIFT_CTRL = _zz_25_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_26_ = decode_PC; + assign _zz_27_ = decode_RS2; + assign decode_SRC2_CTRL = _zz_28_; + assign _zz_29_ = decode_RS1; + assign decode_SRC1_CTRL = _zz_30_; + assign decode_SRC_USE_SUB_LESS = _zz_189_[0]; + assign decode_SRC_ADD_ZERO = _zz_190_[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_31_; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_ALU_BITWISE_CTRL = _zz_32_; + assign _zz_33_ = writeBack_INSTRUCTION; + assign _zz_34_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_35_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_35_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_191_[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_43_ = execute_REGFILE_WRITE_DATA; + if(_zz_144_)begin + _zz_43_ = execute_CsrPlugin_readData; + end + end + + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_44_; + assign execute_ENV_CTRL = _zz_45_; + assign writeBack_ENV_CTRL = _zz_46_; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_47_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_47_ = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_167_) + 2'b00 : begin + _zz_47_ = writeBack_MUL[31 : 0]; + end + default : begin + _zz_47_ = _zz_219_; + end + endcase + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = 1'b0; + always @ (*) begin + _zz_48_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_48_ = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + end + 3'b100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_98_ || _zz_99_)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65_)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_144_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if(_zz_145_)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_145_)begin + if(_zz_146_)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(_zz_145_)begin + if(_zz_146_)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_143_)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_147_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_148_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(_zz_147_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_148_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_145_)begin + if(_zz_146_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_149_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid || IBusSimplePlugin_iBusRsp_stages_2_input_valid))begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_147_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_148_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_147_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_148_)begin + case(_zz_150_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)); + assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid} != (2'b00)); + assign _zz_49_ = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_192_[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_195_); + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + assign _zz_50_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_50_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_50_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_51_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_51_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_51_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'b0; + assign _zz_52_ = (! IBusSimplePlugin_iBusRsp_stages_2_halt); + assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_ready && _zz_52_); + assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = (IBusSimplePlugin_iBusRsp_stages_2_input_valid && _zz_52_); + assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = IBusSimplePlugin_iBusRsp_stages_2_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_53_; + assign _zz_53_ = ((1'b0 && (! _zz_54_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_54_ = _zz_55_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_54_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_56_)) || IBusSimplePlugin_iBusRsp_stages_2_input_ready); + assign _zz_56_ = _zz_57_; + assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = _zz_56_; + assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = _zz_58_; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_59_; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_60_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_61_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_62_; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_63_; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_5; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + end + default : begin + end + endcase + end + + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_196_ - _zz_200_); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && (IBusSimplePlugin_pending_value != (3'b111))); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_1_input_payload[31 : 2],(2'b00)}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000)) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == (3'b000))); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_135_ = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_135_); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_2_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_2_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_64_ = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_64_); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_64_); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign _zz_65_ = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65_)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_66_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_66_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_66_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_66_; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_67_ = (4'b0001); + end + 2'b01 : begin + _zz_67_ = (4'b0011); + end + default : begin + _zz_67_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_67_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_68_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_69_[31] = _zz_68_; + _zz_69_[30] = _zz_68_; + _zz_69_[29] = _zz_68_; + _zz_69_[28] = _zz_68_; + _zz_69_[27] = _zz_68_; + _zz_69_[26] = _zz_68_; + _zz_69_[25] = _zz_68_; + _zz_69_[24] = _zz_68_; + _zz_69_[23] = _zz_68_; + _zz_69_[22] = _zz_68_; + _zz_69_[21] = _zz_68_; + _zz_69_[20] = _zz_68_; + _zz_69_[19] = _zz_68_; + _zz_69_[18] = _zz_68_; + _zz_69_[17] = _zz_68_; + _zz_69_[16] = _zz_68_; + _zz_69_[15] = _zz_68_; + _zz_69_[14] = _zz_68_; + _zz_69_[13] = _zz_68_; + _zz_69_[12] = _zz_68_; + _zz_69_[11] = _zz_68_; + _zz_69_[10] = _zz_68_; + _zz_69_[9] = _zz_68_; + _zz_69_[8] = _zz_68_; + _zz_69_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_70_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_71_[31] = _zz_70_; + _zz_71_[30] = _zz_70_; + _zz_71_[29] = _zz_70_; + _zz_71_[28] = _zz_70_; + _zz_71_[27] = _zz_70_; + _zz_71_[26] = _zz_70_; + _zz_71_[25] = _zz_70_; + _zz_71_[24] = _zz_70_; + _zz_71_[23] = _zz_70_; + _zz_71_[22] = _zz_70_; + _zz_71_[21] = _zz_70_; + _zz_71_[20] = _zz_70_; + _zz_71_[19] = _zz_70_; + _zz_71_[18] = _zz_70_; + _zz_71_[17] = _zz_70_; + _zz_71_[16] = _zz_70_; + _zz_71_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_165_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_69_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_71_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_72_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_73_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_74_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exception = 1'b0; + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + assign CsrPlugin_trapCause = CsrPlugin_interrupt_code; + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_166_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_76_ = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_77_ = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_78_ = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_79_ = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_80_ = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_75_ = {(((decode_INSTRUCTION & _zz_248_) == 32'h02004020) != (1'b0)),{({_zz_249_,{_zz_250_,_zz_251_}} != (4'b0000)),{(_zz_252_ != (1'b0)),{(_zz_253_ != _zz_254_),{_zz_255_,{_zz_256_,_zz_257_}}}}}}; + assign _zz_81_ = _zz_75_[2 : 1]; + assign _zz_42_ = _zz_81_; + assign _zz_82_ = _zz_75_[5 : 4]; + assign _zz_41_ = _zz_82_; + assign _zz_83_ = _zz_75_[7 : 6]; + assign _zz_40_ = _zz_83_; + assign _zz_84_ = _zz_75_[13 : 13]; + assign _zz_39_ = _zz_84_; + assign _zz_85_ = _zz_75_[18 : 17]; + assign _zz_38_ = _zz_85_; + assign _zz_86_ = _zz_75_[25 : 24]; + assign _zz_37_ = _zz_86_; + assign _zz_87_ = _zz_75_[27 : 26]; + assign _zz_36_ = _zz_87_; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_137_; + assign decode_RegFilePlugin_rs2Data = _zz_138_; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_34_ && writeBack_arbitration_isFiring); + if(_zz_88_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_33_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_47_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_89_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_89_ = {31'd0, _zz_203_}; + end + default : begin + _zz_89_ = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_90_ = _zz_29_; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_90_ = {29'd0, _zz_204_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_90_ = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_90_ = {27'd0, _zz_205_}; + end + endcase + end + + assign _zz_91_ = _zz_206_[11]; + always @ (*) begin + _zz_92_[19] = _zz_91_; + _zz_92_[18] = _zz_91_; + _zz_92_[17] = _zz_91_; + _zz_92_[16] = _zz_91_; + _zz_92_[15] = _zz_91_; + _zz_92_[14] = _zz_91_; + _zz_92_[13] = _zz_91_; + _zz_92_[12] = _zz_91_; + _zz_92_[11] = _zz_91_; + _zz_92_[10] = _zz_91_; + _zz_92_[9] = _zz_91_; + _zz_92_[8] = _zz_91_; + _zz_92_[7] = _zz_91_; + _zz_92_[6] = _zz_91_; + _zz_92_[5] = _zz_91_; + _zz_92_[4] = _zz_91_; + _zz_92_[3] = _zz_91_; + _zz_92_[2] = _zz_91_; + _zz_92_[1] = _zz_91_; + _zz_92_[0] = _zz_91_; + end + + assign _zz_93_ = _zz_207_[11]; + always @ (*) begin + _zz_94_[19] = _zz_93_; + _zz_94_[18] = _zz_93_; + _zz_94_[17] = _zz_93_; + _zz_94_[16] = _zz_93_; + _zz_94_[15] = _zz_93_; + _zz_94_[14] = _zz_93_; + _zz_94_[13] = _zz_93_; + _zz_94_[12] = _zz_93_; + _zz_94_[11] = _zz_93_; + _zz_94_[10] = _zz_93_; + _zz_94_[9] = _zz_93_; + _zz_94_[8] = _zz_93_; + _zz_94_[7] = _zz_93_; + _zz_94_[6] = _zz_93_; + _zz_94_[5] = _zz_93_; + _zz_94_[4] = _zz_93_; + _zz_94_[3] = _zz_93_; + _zz_94_[2] = _zz_93_; + _zz_94_[1] = _zz_93_; + _zz_94_[0] = _zz_93_; + end + + always @ (*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_95_ = _zz_27_; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_95_ = {_zz_92_,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_95_ = {_zz_94_,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_95_ = _zz_26_; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_208_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_96_[0] = execute_SRC1[31]; + _zz_96_[1] = execute_SRC1[30]; + _zz_96_[2] = execute_SRC1[29]; + _zz_96_[3] = execute_SRC1[28]; + _zz_96_[4] = execute_SRC1[27]; + _zz_96_[5] = execute_SRC1[26]; + _zz_96_[6] = execute_SRC1[25]; + _zz_96_[7] = execute_SRC1[24]; + _zz_96_[8] = execute_SRC1[23]; + _zz_96_[9] = execute_SRC1[22]; + _zz_96_[10] = execute_SRC1[21]; + _zz_96_[11] = execute_SRC1[20]; + _zz_96_[12] = execute_SRC1[19]; + _zz_96_[13] = execute_SRC1[18]; + _zz_96_[14] = execute_SRC1[17]; + _zz_96_[15] = execute_SRC1[16]; + _zz_96_[16] = execute_SRC1[15]; + _zz_96_[17] = execute_SRC1[14]; + _zz_96_[18] = execute_SRC1[13]; + _zz_96_[19] = execute_SRC1[12]; + _zz_96_[20] = execute_SRC1[11]; + _zz_96_[21] = execute_SRC1[10]; + _zz_96_[22] = execute_SRC1[9]; + _zz_96_[23] = execute_SRC1[8]; + _zz_96_[24] = execute_SRC1[7]; + _zz_96_[25] = execute_SRC1[6]; + _zz_96_[26] = execute_SRC1[5]; + _zz_96_[27] = execute_SRC1[4]; + _zz_96_[28] = execute_SRC1[3]; + _zz_96_[29] = execute_SRC1[2]; + _zz_96_[30] = execute_SRC1[1]; + _zz_96_[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_96_ : execute_SRC1); + always @ (*) begin + _zz_97_[0] = memory_SHIFT_RIGHT[31]; + _zz_97_[1] = memory_SHIFT_RIGHT[30]; + _zz_97_[2] = memory_SHIFT_RIGHT[29]; + _zz_97_[3] = memory_SHIFT_RIGHT[28]; + _zz_97_[4] = memory_SHIFT_RIGHT[27]; + _zz_97_[5] = memory_SHIFT_RIGHT[26]; + _zz_97_[6] = memory_SHIFT_RIGHT[25]; + _zz_97_[7] = memory_SHIFT_RIGHT[24]; + _zz_97_[8] = memory_SHIFT_RIGHT[23]; + _zz_97_[9] = memory_SHIFT_RIGHT[22]; + _zz_97_[10] = memory_SHIFT_RIGHT[21]; + _zz_97_[11] = memory_SHIFT_RIGHT[20]; + _zz_97_[12] = memory_SHIFT_RIGHT[19]; + _zz_97_[13] = memory_SHIFT_RIGHT[18]; + _zz_97_[14] = memory_SHIFT_RIGHT[17]; + _zz_97_[15] = memory_SHIFT_RIGHT[16]; + _zz_97_[16] = memory_SHIFT_RIGHT[15]; + _zz_97_[17] = memory_SHIFT_RIGHT[14]; + _zz_97_[18] = memory_SHIFT_RIGHT[13]; + _zz_97_[19] = memory_SHIFT_RIGHT[12]; + _zz_97_[20] = memory_SHIFT_RIGHT[11]; + _zz_97_[21] = memory_SHIFT_RIGHT[10]; + _zz_97_[22] = memory_SHIFT_RIGHT[9]; + _zz_97_[23] = memory_SHIFT_RIGHT[8]; + _zz_97_[24] = memory_SHIFT_RIGHT[7]; + _zz_97_[25] = memory_SHIFT_RIGHT[6]; + _zz_97_[26] = memory_SHIFT_RIGHT[5]; + _zz_97_[27] = memory_SHIFT_RIGHT[4]; + _zz_97_[28] = memory_SHIFT_RIGHT[3]; + _zz_97_[29] = memory_SHIFT_RIGHT[2]; + _zz_97_[30] = memory_SHIFT_RIGHT[1]; + _zz_97_[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_98_ = 1'b0; + if(_zz_151_)begin + if(_zz_152_)begin + if(_zz_103_)begin + _zz_98_ = 1'b1; + end + end + end + if(_zz_153_)begin + if(_zz_154_)begin + if(_zz_105_)begin + _zz_98_ = 1'b1; + end + end + end + if(_zz_155_)begin + if(_zz_156_)begin + if(_zz_107_)begin + _zz_98_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_98_ = 1'b0; + end + end + + always @ (*) begin + _zz_99_ = 1'b0; + if(_zz_151_)begin + if(_zz_152_)begin + if(_zz_104_)begin + _zz_99_ = 1'b1; + end + end + end + if(_zz_153_)begin + if(_zz_154_)begin + if(_zz_106_)begin + _zz_99_ = 1'b1; + end + end + end + if(_zz_155_)begin + if(_zz_156_)begin + if(_zz_108_)begin + _zz_99_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_99_ = 1'b0; + end + end + + assign _zz_103_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_104_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_105_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_106_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_107_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_108_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_109_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_109_ == (3'b000))) begin + _zz_110_ = execute_BranchPlugin_eq; + end else if((_zz_109_ == (3'b001))) begin + _zz_110_ = (! execute_BranchPlugin_eq); + end else if((((_zz_109_ & (3'b101)) == (3'b101)))) begin + _zz_110_ = (! execute_SRC_LESS); + end else begin + _zz_110_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_111_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_111_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_111_ = 1'b1; + end + default : begin + _zz_111_ = _zz_110_; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_112_ = _zz_215_[19]; + always @ (*) begin + _zz_113_[10] = _zz_112_; + _zz_113_[9] = _zz_112_; + _zz_113_[8] = _zz_112_; + _zz_113_[7] = _zz_112_; + _zz_113_[6] = _zz_112_; + _zz_113_[5] = _zz_112_; + _zz_113_[4] = _zz_112_; + _zz_113_[3] = _zz_112_; + _zz_113_[2] = _zz_112_; + _zz_113_[1] = _zz_112_; + _zz_113_[0] = _zz_112_; + end + + assign _zz_114_ = _zz_216_[11]; + always @ (*) begin + _zz_115_[19] = _zz_114_; + _zz_115_[18] = _zz_114_; + _zz_115_[17] = _zz_114_; + _zz_115_[16] = _zz_114_; + _zz_115_[15] = _zz_114_; + _zz_115_[14] = _zz_114_; + _zz_115_[13] = _zz_114_; + _zz_115_[12] = _zz_114_; + _zz_115_[11] = _zz_114_; + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_217_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_118_ = {{_zz_113_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_118_ = {_zz_115_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_118_ = {{_zz_117_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_118_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign execute_Mul16Plugin_a = execute_SRC1; + assign execute_Mul16Plugin_b = execute_SRC2; + assign execute_Mul16Plugin_aLow = execute_Mul16Plugin_a[15 : 0]; + assign execute_Mul16Plugin_bLow = execute_Mul16Plugin_b[15 : 0]; + assign execute_Mul16Plugin_aHigh = execute_Mul16Plugin_a[31 : 16]; + assign execute_Mul16Plugin_bHigh = execute_Mul16Plugin_b[31 : 16]; + assign memory_Mul16Plugin_ll = memory_MUL_LL; + assign memory_Mul16Plugin_lh = {1'd0, memory_MUL_LH}; + assign memory_Mul16Plugin_hl = memory_MUL_HL; + assign memory_Mul16Plugin_hh = memory_MUL_HH; + assign memory_Mul16Plugin_hllh = (memory_Mul16Plugin_lh + _zz_218_); + always @ (*) begin + case(_zz_157_) + 2'b01 : begin + writeBack_Mul16Plugin_aSigned = 1'b1; + end + 2'b10 : begin + writeBack_Mul16Plugin_aSigned = 1'b1; + end + default : begin + writeBack_Mul16Plugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_157_) + 2'b01 : begin + writeBack_Mul16Plugin_bSigned = 1'b1; + end + 2'b10 : begin + writeBack_Mul16Plugin_bSigned = 1'b0; + end + default : begin + writeBack_Mul16Plugin_bSigned = 1'b0; + end + endcase + end + + assign writeBack_Mul16Plugin_a = ((writeBack_Mul16Plugin_aSigned && writeBack_SRC1[31]) ? writeBack_SRC2 : 32'h0); + assign writeBack_Mul16Plugin_b = ((writeBack_Mul16Plugin_bSigned && writeBack_SRC2[31]) ? writeBack_SRC1 : 32'h0); + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_143_)begin + if(_zz_158_)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_159_)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_223_); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_119_ = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_119_[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_224_); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_225_ : _zz_226_); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_227_[31:0]; + assign _zz_120_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_121_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_122_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_123_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_123_[31 : 0] = execute_RS1; + end + + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_124_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusSimplePlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + IBusSimplePlugin_injectionPort_valid = 1'b1; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + default : begin + end + endcase + end + end + + assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_21_ = decode_ENV_CTRL; + assign _zz_18_ = execute_ENV_CTRL; + assign _zz_16_ = memory_ENV_CTRL; + assign _zz_19_ = _zz_39_; + assign _zz_45_ = decode_to_execute_ENV_CTRL; + assign _zz_44_ = execute_to_memory_ENV_CTRL; + assign _zz_46_ = memory_to_writeBack_ENV_CTRL; + assign _zz_14_ = decode_SHIFT_CTRL; + assign _zz_11_ = execute_SHIFT_CTRL; + assign _zz_12_ = _zz_38_; + assign _zz_25_ = decode_to_execute_SHIFT_CTRL; + assign _zz_24_ = execute_to_memory_SHIFT_CTRL; + assign _zz_30_ = _zz_41_; + assign _zz_9_ = decode_BRANCH_CTRL; + assign _zz_7_ = _zz_37_; + assign _zz_22_ = decode_to_execute_BRANCH_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_42_; + assign _zz_32_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_28_ = _zz_40_; + assign _zz_3_ = decode_ALU_CTRL; + assign _zz_1_ = _zz_36_; + assign _zz_31_ = decode_to_execute_ALU_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusSimplePlugin_injectionPort_ready = 1'b0; + case(_zz_125_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + end + 3'b011 : begin + end + 3'b100 : begin + IBusSimplePlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_126_ = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_126_[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_126_[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_126_[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_127_ = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_127_[11 : 11] = CsrPlugin_mip_MEIP; + _zz_127_[7 : 7] = CsrPlugin_mip_MTIP; + _zz_127_[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_128_ = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_128_[11 : 11] = CsrPlugin_mie_MEIE; + _zz_128_[7 : 7] = CsrPlugin_mie_MTIE; + _zz_128_[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_129_ = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_129_[31 : 2] = CsrPlugin_mtvec_base; + _zz_129_[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_130_ = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_130_[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_130_[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_131_ = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_131_[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_132_ = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_132_[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_133_ = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_133_[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_134_ = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_134_[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + assign execute_CsrPlugin_readData = ((((_zz_126_ | _zz_127_) | (_zz_128_ | _zz_129_)) | ((_zz_130_ | _zz_131_) | (_zz_132_ | _zz_133_))) | _zz_134_); + assign _zz_136_ = 1'b0; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + IBusSimplePlugin_fetchPc_pcReg <= 32'h80000000; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_55_ <= 1'b0; + _zz_57_ <= 1'b0; + _zz_59_ <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusSimplePlugin_pending_value <= (3'b000); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (3'b000); + CsrPlugin_mtvec_mode <= (2'b00); + CsrPlugin_mtvec_base <= 30'h20000000; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_88_ <= 1'b1; + _zz_100_ <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_125_ <= (3'b000); + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_55_ <= 1'b0; + end + if(_zz_53_)begin + _zz_55_ <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_57_ <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + _zz_57_ <= (IBusSimplePlugin_iBusRsp_stages_1_output_valid && (! IBusSimplePlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt)begin + _zz_59_ <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_59_ <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_2_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= IBusSimplePlugin_injector_nextPcCalc_valids_4; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_202_); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= IBusSimplePlugin_pending_next; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_161_)begin + if(_zz_162_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_163_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_164_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_147_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_148_)begin + case(_zz_150_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_74_,{_zz_73_,_zz_72_}} != (3'b000)) || CsrPlugin_thirdPartyWake); + _zz_88_ <= 1'b0; + _zz_100_ <= (_zz_34_ && writeBack_arbitration_isFiring); + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_23_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_125_) + 3'b000 : begin + if(IBusSimplePlugin_injectionPort_valid)begin + _zz_125_ <= (3'b001); + end + end + 3'b001 : begin + _zz_125_ <= (3'b010); + end + 3'b010 : begin + _zz_125_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_125_ <= (3'b100); + end + end + 3'b100 : begin + _zz_125_ <= (3'b000); + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_240_[0]; + CsrPlugin_mstatus_MIE <= _zz_241_[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_243_[0]; + CsrPlugin_mie_MTIE <= _zz_244_[0]; + CsrPlugin_mie_MSIE <= _zz_245_[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + end + end + + always @ (posedge mainClock) begin + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + _zz_58_ <= IBusSimplePlugin_iBusRsp_stages_1_output_payload; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_60_ <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_61_ <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_62_ <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_63_ <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_161_)begin + if(_zz_162_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_163_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_164_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_147_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + end + default : begin + end + endcase + end + _zz_101_ <= _zz_33_[11 : 7]; + _zz_102_ <= _zz_47_; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_143_)begin + if(_zz_158_)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_228_[31:0]; + end + end + end + if(_zz_159_)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_122_ ? (~ _zz_123_) : _zz_123_) + _zz_234_); + memory_MulDivIterativePlugin_rs2 <= ((_zz_121_ ? (~ execute_RS2) : execute_RS2) + _zz_236_); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_122_ ^ (_zz_121_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_20_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_17_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_15_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_27_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC1 <= execute_SRC1; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC1 <= memory_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC2 <= execute_SRC2; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC2 <= memory_SRC2; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL <= memory_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= _zz_26_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= execute_PC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= _zz_29_; + end + if((_zz_125_ != (3'b000)))begin + _zz_62_ <= IBusSimplePlugin_injectionPort_payload; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_242_[0]; + end + end + end + + always @ (posedge mainClock) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusSimplePlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_47_; + end + _zz_124_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_145_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_160_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_237_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_238_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_239_[0]; + end + end + default : begin + end + endcase + end + if(_zz_145_)begin + if(_zz_146_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_149_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module JtagBridge ( + input io_jtag_tms, + input io_jtag_tdi, + output io_jtag_tdo, + input io_jtag_tck, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input mainClock, + input resetCtrl_mainClockReset +); + wire flowCCByToggle_1__io_output_valid; + wire flowCCByToggle_1__io_output_payload_last; + wire [0:0] flowCCByToggle_1__io_output_payload_fragment; + wire _zz_2_; + wire _zz_3_; + wire [0:0] _zz_4_; + wire [3:0] _zz_5_; + wire [1:0] _zz_6_; + wire [3:0] _zz_7_; + wire [1:0] _zz_8_; + wire [3:0] _zz_9_; + wire [0:0] _zz_10_; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + reg system_rsp_valid; + reg system_rsp_payload_error; + reg [31:0] system_rsp_payload_data; + wire `JtagState_defaultEncoding_type jtag_tap_fsm_stateNext; + reg `JtagState_defaultEncoding_type jtag_tap_fsm_state = `JtagState_defaultEncoding_RESET; + reg `JtagState_defaultEncoding_type _zz_1_; + reg [3:0] jtag_tap_instruction; + reg [3:0] jtag_tap_instructionShift; + reg jtag_tap_bypass; + reg jtag_tap_tdoUnbufferd; + reg jtag_tap_tdoUnbufferd_regNext; + wire jtag_idcodeArea_instructionHit; + reg [31:0] jtag_idcodeArea_shifter; + wire jtag_writeArea_instructionHit; + reg jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + wire jtag_readArea_instructionHit; + reg [33:0] jtag_readArea_shifter; + `ifndef SYNTHESIS + reg [79:0] jtag_tap_fsm_stateNext_string; + reg [79:0] jtag_tap_fsm_state_string; + reg [79:0] _zz_1__string; + `endif + + + assign _zz_2_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT); + assign _zz_3_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT); + assign _zz_4_ = (1'b1); + assign _zz_5_ = {3'd0, _zz_4_}; + assign _zz_6_ = (2'b10); + assign _zz_7_ = {2'd0, _zz_6_}; + assign _zz_8_ = (2'b11); + assign _zz_9_ = {2'd0, _zz_8_}; + assign _zz_10_ = (1'b1); + FlowCCByToggle flowCCByToggle_1_ ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1__io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1__io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1__io_output_payload_fragment ), //o + .io_jtag_tck (io_jtag_tck ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(jtag_tap_fsm_stateNext) + `JtagState_defaultEncoding_RESET : jtag_tap_fsm_stateNext_string = "RESET "; + `JtagState_defaultEncoding_IDLE : jtag_tap_fsm_stateNext_string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : jtag_tap_fsm_stateNext_string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : jtag_tap_fsm_stateNext_string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_RESET : jtag_tap_fsm_state_string = "RESET "; + `JtagState_defaultEncoding_IDLE : jtag_tap_fsm_state_string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : jtag_tap_fsm_state_string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : jtag_tap_fsm_state_string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : jtag_tap_fsm_state_string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : jtag_tap_fsm_state_string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : jtag_tap_fsm_state_string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : jtag_tap_fsm_state_string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : jtag_tap_fsm_state_string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : jtag_tap_fsm_state_string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : jtag_tap_fsm_state_string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : jtag_tap_fsm_state_string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : jtag_tap_fsm_state_string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : jtag_tap_fsm_state_string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : jtag_tap_fsm_state_string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : jtag_tap_fsm_state_string = "DR_UPDATE "; + default : jtag_tap_fsm_state_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `JtagState_defaultEncoding_RESET : _zz_1__string = "RESET "; + `JtagState_defaultEncoding_IDLE : _zz_1__string = "IDLE "; + `JtagState_defaultEncoding_IR_SELECT : _zz_1__string = "IR_SELECT "; + `JtagState_defaultEncoding_IR_CAPTURE : _zz_1__string = "IR_CAPTURE"; + `JtagState_defaultEncoding_IR_SHIFT : _zz_1__string = "IR_SHIFT "; + `JtagState_defaultEncoding_IR_EXIT1 : _zz_1__string = "IR_EXIT1 "; + `JtagState_defaultEncoding_IR_PAUSE : _zz_1__string = "IR_PAUSE "; + `JtagState_defaultEncoding_IR_EXIT2 : _zz_1__string = "IR_EXIT2 "; + `JtagState_defaultEncoding_IR_UPDATE : _zz_1__string = "IR_UPDATE "; + `JtagState_defaultEncoding_DR_SELECT : _zz_1__string = "DR_SELECT "; + `JtagState_defaultEncoding_DR_CAPTURE : _zz_1__string = "DR_CAPTURE"; + `JtagState_defaultEncoding_DR_SHIFT : _zz_1__string = "DR_SHIFT "; + `JtagState_defaultEncoding_DR_EXIT1 : _zz_1__string = "DR_EXIT1 "; + `JtagState_defaultEncoding_DR_PAUSE : _zz_1__string = "DR_PAUSE "; + `JtagState_defaultEncoding_DR_EXIT2 : _zz_1__string = "DR_EXIT2 "; + `JtagState_defaultEncoding_DR_UPDATE : _zz_1__string = "DR_UPDATE "; + default : _zz_1__string = "??????????"; + endcase + end + `endif + + assign io_remote_cmd_valid = system_cmd_valid; + assign io_remote_cmd_payload_last = system_cmd_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_payload_fragment; + assign io_remote_rsp_ready = 1'b1; + always @ (*) begin + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IDLE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + `JtagState_defaultEncoding_IR_SELECT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IR_CAPTURE); + end + `JtagState_defaultEncoding_IR_CAPTURE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_SHIFT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_EXIT1 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_PAUSE); + end + `JtagState_defaultEncoding_IR_PAUSE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT2 : `JtagState_defaultEncoding_IR_PAUSE); + end + `JtagState_defaultEncoding_IR_EXIT2 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_SHIFT); + end + `JtagState_defaultEncoding_IR_UPDATE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + `JtagState_defaultEncoding_DR_SELECT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_SELECT : `JtagState_defaultEncoding_DR_CAPTURE); + end + `JtagState_defaultEncoding_DR_CAPTURE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_SHIFT : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_EXIT1 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_PAUSE); + end + `JtagState_defaultEncoding_DR_PAUSE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT2 : `JtagState_defaultEncoding_DR_PAUSE); + end + `JtagState_defaultEncoding_DR_EXIT2 : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_SHIFT); + end + `JtagState_defaultEncoding_DR_UPDATE : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE); + end + default : begin + _zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IDLE); + end + endcase + end + + assign jtag_tap_fsm_stateNext = _zz_1_; + always @ (*) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IR_CAPTURE : begin + end + `JtagState_defaultEncoding_IR_SHIFT : begin + jtag_tap_tdoUnbufferd = jtag_tap_instructionShift[0]; + end + `JtagState_defaultEncoding_IR_UPDATE : begin + end + default : begin + end + endcase + if(jtag_idcodeArea_instructionHit)begin + if(_zz_2_)begin + jtag_tap_tdoUnbufferd = jtag_idcodeArea_shifter[0]; + end + end + if(jtag_readArea_instructionHit)begin + if(_zz_3_)begin + jtag_tap_tdoUnbufferd = jtag_readArea_shifter[0]; + end + end + end + + assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; + assign jtag_idcodeArea_instructionHit = (jtag_tap_instruction == _zz_5_); + assign jtag_writeArea_instructionHit = (jtag_tap_instruction == _zz_7_); + always @ (*) begin + jtag_writeArea_source_valid = 1'b0; + if(jtag_writeArea_instructionHit)begin + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT))begin + jtag_writeArea_source_valid = 1'b1; + end + end + end + + assign jtag_writeArea_source_payload_last = io_jtag_tms; + assign jtag_writeArea_source_payload_fragment[0] = io_jtag_tdi; + assign system_cmd_valid = flowCCByToggle_1__io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1__io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1__io_output_payload_fragment; + assign jtag_readArea_instructionHit = (jtag_tap_instruction == _zz_9_); + always @ (posedge mainClock) begin + if(io_remote_cmd_valid)begin + system_rsp_valid <= 1'b0; + end + if((io_remote_rsp_valid && io_remote_rsp_ready))begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @ (posedge io_jtag_tck) begin + jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; + jtag_tap_bypass <= io_jtag_tdi; + case(jtag_tap_fsm_state) + `JtagState_defaultEncoding_IR_CAPTURE : begin + jtag_tap_instructionShift <= jtag_tap_instruction; + end + `JtagState_defaultEncoding_IR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); + end + `JtagState_defaultEncoding_IR_UPDATE : begin + jtag_tap_instruction <= jtag_tap_instructionShift; + end + default : begin + end + endcase + if(jtag_idcodeArea_instructionHit)begin + if(_zz_2_)begin + jtag_idcodeArea_shifter <= ({io_jtag_tdi,jtag_idcodeArea_shifter} >>> 1); + end + end + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_RESET))begin + jtag_idcodeArea_shifter <= 32'h10001fff; + jtag_tap_instruction <= {3'd0, _zz_10_}; + end + if(jtag_readArea_instructionHit)begin + if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_CAPTURE))begin + jtag_readArea_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(_zz_3_)begin + jtag_readArea_shifter <= ({io_jtag_tdi,jtag_readArea_shifter} >>> 1); + end + end + end + + always @ (negedge io_jtag_tck) begin + jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; + end + + +endmodule + +module SystemDebugger ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input mainClock, + input resetCtrl_mainClockReset +); + wire _zz_2_; + wire [0:0] _zz_3_; + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire [66:0] _zz_1_; + + assign _zz_2_ = (dispatcher_headerLoaded == 1'b0); + assign _zz_3_ = _zz_1_[64 : 64]; + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_1_ = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_1_[31 : 0]; + assign io_mem_cmd_payload_data = _zz_1_[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_3_[0]; + assign io_mem_cmd_payload_size = _zz_1_[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= (3'b000); + end else begin + if(io_remote_cmd_valid)begin + if(_zz_2_)begin + dispatcher_counter <= (dispatcher_counter + (3'b001)); + if((dispatcher_counter == (3'b111)))begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last)begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= (3'b000); + end + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @ (posedge mainClock) begin + if(io_remote_cmd_valid)begin + if(_zz_2_)begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module PipelinedMemoryBusToApbBridge ( + input io_pipelinedMemoryBus_cmd_valid, + output io_pipelinedMemoryBus_cmd_ready, + input io_pipelinedMemoryBus_cmd_payload_write, + input [31:0] io_pipelinedMemoryBus_cmd_payload_address, + input [31:0] io_pipelinedMemoryBus_cmd_payload_data, + input [3:0] io_pipelinedMemoryBus_cmd_payload_mask, + output io_pipelinedMemoryBus_rsp_valid, + output [31:0] io_pipelinedMemoryBus_rsp_payload_data, + output [19:0] io_apb_PADDR, + output [0:0] io_apb_PSEL, + output io_apb_PENABLE, + input io_apb_PREADY, + output io_apb_PWRITE, + output [31:0] io_apb_PWDATA, + input [31:0] io_apb_PRDATA, + input io_apb_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_1_; + wire pipelinedMemoryBusStage_cmd_valid; + reg pipelinedMemoryBusStage_cmd_ready; + wire pipelinedMemoryBusStage_cmd_payload_write; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_address; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_data; + wire [3:0] pipelinedMemoryBusStage_cmd_payload_mask; + reg pipelinedMemoryBusStage_rsp_valid; + wire [31:0] pipelinedMemoryBusStage_rsp_payload_data; + reg pipelinedMemoryBusStage_rsp_regNext_valid; + reg [31:0] pipelinedMemoryBusStage_rsp_regNext_payload_data; + reg state; + + assign _zz_1_ = (! state); + assign pipelinedMemoryBusStage_cmd_valid = io_pipelinedMemoryBus_cmd_valid; + assign io_pipelinedMemoryBus_cmd_ready = pipelinedMemoryBusStage_cmd_ready; + assign pipelinedMemoryBusStage_cmd_payload_write = io_pipelinedMemoryBus_cmd_payload_write; + assign pipelinedMemoryBusStage_cmd_payload_address = io_pipelinedMemoryBus_cmd_payload_address; + assign pipelinedMemoryBusStage_cmd_payload_data = io_pipelinedMemoryBus_cmd_payload_data; + assign pipelinedMemoryBusStage_cmd_payload_mask = io_pipelinedMemoryBus_cmd_payload_mask; + assign io_pipelinedMemoryBus_rsp_valid = pipelinedMemoryBusStage_rsp_regNext_valid; + assign io_pipelinedMemoryBus_rsp_payload_data = pipelinedMemoryBusStage_rsp_regNext_payload_data; + always @ (*) begin + pipelinedMemoryBusStage_cmd_ready = 1'b0; + if(! _zz_1_) begin + if(io_apb_PREADY)begin + pipelinedMemoryBusStage_cmd_ready = 1'b1; + end + end + end + + assign io_apb_PSEL[0] = pipelinedMemoryBusStage_cmd_valid; + assign io_apb_PENABLE = state; + assign io_apb_PWRITE = pipelinedMemoryBusStage_cmd_payload_write; + assign io_apb_PADDR = pipelinedMemoryBusStage_cmd_payload_address[19:0]; + assign io_apb_PWDATA = pipelinedMemoryBusStage_cmd_payload_data; + always @ (*) begin + pipelinedMemoryBusStage_rsp_valid = 1'b0; + if(! _zz_1_) begin + if(io_apb_PREADY)begin + pipelinedMemoryBusStage_rsp_valid = (! pipelinedMemoryBusStage_cmd_payload_write); + end + end + end + + assign pipelinedMemoryBusStage_rsp_payload_data = io_apb_PRDATA; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + pipelinedMemoryBusStage_rsp_regNext_valid <= 1'b0; + state <= 1'b0; + end else begin + pipelinedMemoryBusStage_rsp_regNext_valid <= pipelinedMemoryBusStage_rsp_valid; + if(_zz_1_)begin + state <= pipelinedMemoryBusStage_cmd_valid; + end else begin + if(io_apb_PREADY)begin + state <= 1'b0; + end + end + end + end + + always @ (posedge mainClock) begin + pipelinedMemoryBusStage_rsp_regNext_payload_data <= pipelinedMemoryBusStage_rsp_payload_data; + end + + +endmodule + +module Apb3UartCtrl ( + input [4:0] io_apb_PADDR, + input [0:0] io_apb_PSEL, + input io_apb_PENABLE, + output io_apb_PREADY, + input io_apb_PWRITE, + input [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_7_; + reg _zz_8_; + wire _zz_9_; + wire uartCtrl_1__io_write_ready; + wire uartCtrl_1__io_read_valid; + wire [7:0] uartCtrl_1__io_read_payload; + wire uartCtrl_1__io_uart_txd; + wire uartCtrl_1__io_readError; + wire uartCtrl_1__io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1__io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload; + wire [4:0] uartCtrl_1__io_read_queueWithOccupancy_io_occupancy; + wire [4:0] uartCtrl_1__io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_10_; + wire [0:0] _zz_11_; + wire [0:0] _zz_12_; + wire [0:0] _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [0:0] _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [0:0] _zz_20_; + wire [0:0] _zz_21_; + wire [4:0] _zz_22_; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire [2:0] bridge_uartConfigReg_frame_dataLength; + wire `UartStopType_defaultEncoding_type bridge_uartConfigReg_frame_stop; + wire `UartParityType_defaultEncoding_type bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_1_; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg _zz_2_; + reg bridge_misc_readOverflowError; + reg _zz_3_; + reg bridge_misc_breakDetected; + reg uartCtrl_1__io_readBreak_regNext; + reg _zz_4_; + reg bridge_misc_doBreak; + reg _zz_5_; + reg _zz_6_; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + `endif + + function [19:0] zz_bridge_uartConfigReg_clockDivider(input dummy); + begin + zz_bridge_uartConfigReg_clockDivider = 20'h0; + zz_bridge_uartConfigReg_clockDivider = 20'h0002a; + end + endfunction + wire [19:0] _zz_23_; + + assign _zz_10_ = io_apb_PWDATA[0 : 0]; + assign _zz_11_ = (1'b0); + assign _zz_12_ = io_apb_PWDATA[1 : 1]; + assign _zz_13_ = (1'b0); + assign _zz_14_ = io_apb_PWDATA[9 : 9]; + assign _zz_15_ = (1'b0); + assign _zz_16_ = io_apb_PWDATA[10 : 10]; + assign _zz_17_ = (1'b1); + assign _zz_18_ = io_apb_PWDATA[11 : 11]; + assign _zz_19_ = (1'b0); + assign _zz_20_ = io_apb_PWDATA[0 : 0]; + assign _zz_21_ = io_apb_PWDATA[1 : 1]; + assign _zz_22_ = (5'h10 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + UartCtrl uartCtrl_1_ ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1__io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //i + .io_read_valid (uartCtrl_1__io_read_valid ), //o + .io_read_ready (uartCtrl_1__io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1__io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1__io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1__io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1__io_readBreak ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1__io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (_zz_7_ ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[4:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifo uartCtrl_1__io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1__io_read_valid ), //i + .io_push_ready (uartCtrl_1__io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1__io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (_zz_8_ ), //i + .io_pop_payload (uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (_zz_9_ ), //i + .io_occupancy (uartCtrl_1__io_read_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (uartCtrl_1__io_read_queueWithOccupancy_io_availability[4:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + `UartStopType_defaultEncoding_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + `UartStopType_defaultEncoding_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + `UartParityType_defaultEncoding_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + `UartParityType_defaultEncoding_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + `UartParityType_defaultEncoding_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1__io_uart_txd; + assign io_apb_PREADY = 1'b1; + always @ (*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 5'b00000 : begin + io_apb_PRDATA[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + io_apb_PRDATA[7 : 0] = bridge_read_streamBreaked_payload; + end + 5'b00100 : begin + io_apb_PRDATA[20 : 16] = _zz_22_; + io_apb_PRDATA[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + io_apb_PRDATA[28 : 24] = uartCtrl_1__io_read_queueWithOccupancy_io_occupancy; + io_apb_PRDATA[0 : 0] = bridge_interruptCtrl_writeIntEnable; + io_apb_PRDATA[1 : 1] = bridge_interruptCtrl_readIntEnable; + io_apb_PRDATA[8 : 8] = bridge_interruptCtrl_writeInt; + io_apb_PRDATA[9 : 9] = bridge_interruptCtrl_readInt; + end + 5'b10000 : begin + io_apb_PRDATA[0 : 0] = bridge_misc_readError; + io_apb_PRDATA[1 : 1] = bridge_misc_readOverflowError; + io_apb_PRDATA[8 : 8] = uartCtrl_1__io_readBreak; + io_apb_PRDATA[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + assign _zz_23_ = zz_bridge_uartConfigReg_clockDivider(1'b0); + always @ (*) bridge_uartConfigReg_clockDivider = _zz_23_; + assign bridge_uartConfigReg_frame_dataLength = (3'b111); + assign bridge_uartConfigReg_frame_parity = `UartParityType_defaultEncoding_NONE; + assign bridge_uartConfigReg_frame_stop = `UartStopType_defaultEncoding_ONE; + always @ (*) begin + _zz_1_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + if(busCtrl_doWrite)begin + _zz_1_ = 1'b1; + end + end + 5'b00100 : begin + end + 5'b10000 : begin + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_1_; + assign bridge_write_streamUnbuffered_payload = io_apb_PWDATA[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @ (*) begin + bridge_read_streamBreaked_valid = uartCtrl_1__io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1__io_readBreak)begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @ (*) begin + _zz_8_ = bridge_read_streamBreaked_ready; + if(uartCtrl_1__io_readBreak)begin + _zz_8_ = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1__io_read_queueWithOccupancy_io_pop_payload; + always @ (*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + if(busCtrl_doRead)begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + 5'b00100 : begin + end + 5'b10000 : begin + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @ (*) begin + _zz_2_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_2_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_3_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_3_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_4_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_4_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_5_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_5_ = 1'b1; + end + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_6_ = 1'b0; + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + end + 5'b10000 : begin + if(busCtrl_doWrite)begin + _zz_6_ = 1'b1; + end + end + default : begin + end + endcase + end + + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_7_ = 1'b0; + assign _zz_9_ = 1'b0; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_2_)begin + if(_zz_10_[0])begin + bridge_misc_readError <= _zz_11_[0]; + end + end + if(uartCtrl_1__io_readError)begin + bridge_misc_readError <= 1'b1; + end + if(_zz_3_)begin + if(_zz_12_[0])begin + bridge_misc_readOverflowError <= _zz_13_[0]; + end + end + if((uartCtrl_1__io_read_valid && (! uartCtrl_1__io_read_queueWithOccupancy_io_push_ready)))begin + bridge_misc_readOverflowError <= 1'b1; + end + if((uartCtrl_1__io_readBreak && (! uartCtrl_1__io_readBreak_regNext)))begin + bridge_misc_breakDetected <= 1'b1; + end + if(_zz_4_)begin + if(_zz_14_[0])begin + bridge_misc_breakDetected <= _zz_15_[0]; + end + end + if(_zz_5_)begin + if(_zz_16_[0])begin + bridge_misc_doBreak <= _zz_17_[0]; + end + end + if(_zz_6_)begin + if(_zz_18_[0])begin + bridge_misc_doBreak <= _zz_19_[0]; + end + end + case(io_apb_PADDR) + 5'b00000 : begin + end + 5'b00100 : begin + if(busCtrl_doWrite)begin + bridge_interruptCtrl_writeIntEnable <= _zz_20_[0]; + bridge_interruptCtrl_readIntEnable <= _zz_21_[0]; + end + end + 5'b10000 : begin + end + default : begin + end + endcase + end + end + + always @ (posedge mainClock) begin + uartCtrl_1__io_readBreak_regNext <= uartCtrl_1__io_readBreak; + end + + +endmodule + +module MuraxApb3Timer ( + input [7:0] io_apb_PADDR, + input [0:0] io_apb_PSEL, + input io_apb_PENABLE, + output io_apb_PREADY, + input io_apb_PWRITE, + input [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output io_apb_PSLVERROR, + output io_interrupt, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_7_; + wire _zz_8_; + wire _zz_9_; + wire _zz_10_; + reg [1:0] _zz_11_; + reg [1:0] _zz_12_; + wire prescaler_1__io_overflow; + wire timerA_io_full; + wire [15:0] timerA_io_value; + wire timerB_io_full; + wire [15:0] timerB_io_value; + wire [1:0] interruptCtrl_1__io_pendings; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + reg [15:0] _zz_1_; + reg _zz_2_; + reg [1:0] timerABridge_ticksEnable; + reg [0:0] timerABridge_clearsEnable; + reg timerABridge_busClearing; + reg [15:0] timerA_io_limit_driver; + reg _zz_3_; + reg _zz_4_; + reg [1:0] timerBBridge_ticksEnable; + reg [0:0] timerBBridge_clearsEnable; + reg timerBBridge_busClearing; + reg [15:0] timerB_io_limit_driver; + reg _zz_5_; + reg _zz_6_; + reg [1:0] interruptCtrl_1__io_masks_driver; + + Prescaler prescaler_1_ ( + .io_clear (_zz_2_ ), //i + .io_limit (_zz_1_[15:0] ), //i + .io_overflow (prescaler_1__io_overflow ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Timer timerA ( + .io_tick (_zz_7_ ), //i + .io_clear (_zz_8_ ), //i + .io_limit (timerA_io_limit_driver[15:0] ), //i + .io_full (timerA_io_full ), //o + .io_value (timerA_io_value[15:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Timer timerB ( + .io_tick (_zz_9_ ), //i + .io_clear (_zz_10_ ), //i + .io_limit (timerB_io_limit_driver[15:0] ), //i + .io_full (timerB_io_full ), //o + .io_value (timerB_io_value[15:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + InterruptCtrl interruptCtrl_1_ ( + .io_inputs (_zz_11_[1:0] ), //i + .io_clears (_zz_12_[1:0] ), //i + .io_masks (interruptCtrl_1__io_masks_driver[1:0] ), //i + .io_pendings (interruptCtrl_1__io_pendings[1:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign io_apb_PREADY = 1'b1; + always @ (*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 8'b00000000 : begin + io_apb_PRDATA[15 : 0] = _zz_1_; + end + 8'b01000000 : begin + io_apb_PRDATA[1 : 0] = timerABridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerABridge_clearsEnable; + end + 8'b01000100 : begin + io_apb_PRDATA[15 : 0] = timerA_io_limit_driver; + end + 8'b01001000 : begin + io_apb_PRDATA[15 : 0] = timerA_io_value; + end + 8'b01010000 : begin + io_apb_PRDATA[1 : 0] = timerBBridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerBBridge_clearsEnable; + end + 8'b01010100 : begin + io_apb_PRDATA[15 : 0] = timerB_io_limit_driver; + end + 8'b01011000 : begin + io_apb_PRDATA[15 : 0] = timerB_io_value; + end + 8'b00010000 : begin + io_apb_PRDATA[1 : 0] = interruptCtrl_1__io_pendings; + end + 8'b00010100 : begin + io_apb_PRDATA[1 : 0] = interruptCtrl_1__io_masks_driver; + end + default : begin + end + endcase + end + + assign io_apb_PSLVERROR = 1'b0; + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + always @ (*) begin + _zz_2_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + if(busCtrl_doWrite)begin + _zz_2_ = 1'b1; + end + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + timerABridge_busClearing = 1'b0; + if(_zz_3_)begin + timerABridge_busClearing = 1'b1; + end + if(_zz_4_)begin + timerABridge_busClearing = 1'b1; + end + end + + always @ (*) begin + _zz_3_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + if(busCtrl_doWrite)begin + _zz_3_ = 1'b1; + end + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_4_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + if(busCtrl_doWrite)begin + _zz_4_ = 1'b1; + end + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + assign _zz_8_ = (((timerABridge_clearsEnable & timerA_io_full) != (1'b0)) || timerABridge_busClearing); + assign _zz_7_ = ((timerABridge_ticksEnable & {prescaler_1__io_overflow,1'b1}) != (2'b00)); + always @ (*) begin + timerBBridge_busClearing = 1'b0; + if(_zz_5_)begin + timerBBridge_busClearing = 1'b1; + end + if(_zz_6_)begin + timerBBridge_busClearing = 1'b1; + end + end + + always @ (*) begin + _zz_5_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + if(busCtrl_doWrite)begin + _zz_5_ = 1'b1; + end + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_6_ = 1'b0; + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + if(busCtrl_doWrite)begin + _zz_6_ = 1'b1; + end + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + assign _zz_10_ = (((timerBBridge_clearsEnable & timerB_io_full) != (1'b0)) || timerBBridge_busClearing); + assign _zz_9_ = ((timerBBridge_ticksEnable & {prescaler_1__io_overflow,1'b1}) != (2'b00)); + always @ (*) begin + _zz_12_ = (2'b00); + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + if(busCtrl_doWrite)begin + _zz_12_ = io_apb_PWDATA[1 : 0]; + end + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_11_[0] = timerA_io_full; + _zz_11_[1] = timerB_io_full; + end + + assign io_interrupt = (interruptCtrl_1__io_pendings != (2'b00)); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + timerABridge_ticksEnable <= (2'b00); + timerABridge_clearsEnable <= (1'b0); + timerBBridge_ticksEnable <= (2'b00); + timerBBridge_clearsEnable <= (1'b0); + interruptCtrl_1__io_masks_driver <= (2'b00); + end else begin + case(io_apb_PADDR) + 8'b00000000 : begin + end + 8'b01000000 : begin + if(busCtrl_doWrite)begin + timerABridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerABridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'b01000100 : begin + end + 8'b01001000 : begin + end + 8'b01010000 : begin + if(busCtrl_doWrite)begin + timerBBridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerBBridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'b01010100 : begin + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + if(busCtrl_doWrite)begin + interruptCtrl_1__io_masks_driver <= io_apb_PWDATA[1 : 0]; + end + end + default : begin + end + endcase + end + end + + always @ (posedge mainClock) begin + case(io_apb_PADDR) + 8'b00000000 : begin + if(busCtrl_doWrite)begin + _zz_1_ <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01000000 : begin + end + 8'b01000100 : begin + if(busCtrl_doWrite)begin + timerA_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01001000 : begin + end + 8'b01010000 : begin + end + 8'b01010100 : begin + if(busCtrl_doWrite)begin + timerB_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + 8'b01011000 : begin + end + 8'b00010000 : begin + end + 8'b00010100 : begin + end + default : begin + end + endcase + end + + +endmodule + +module MyMem ( + input [19:0] io_bus_PADDR, + input [0:0] io_bus_PSEL, + input io_bus_PENABLE, + output io_bus_PREADY, + input io_bus_PWRITE, + input [31:0] io_bus_PWDATA, + output reg [31:0] io_bus_PRDATA, + output io_bus_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] myReg; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + + assign io_bus_PREADY = 1'b1; + always @ (*) begin + io_bus_PRDATA = 32'h0; + case(io_bus_PADDR) + 20'b00110000000000000000 : begin + io_bus_PRDATA[31 : 0] = myReg; + end + default : begin + end + endcase + end + + assign io_bus_PSLVERROR = 1'b0; + assign busCtrl_askWrite = ((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PWRITE); + assign busCtrl_askRead = ((io_bus_PSEL[0] && io_bus_PENABLE) && (! io_bus_PWRITE)); + assign busCtrl_doWrite = (((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PREADY) && io_bus_PWRITE); + assign busCtrl_doRead = (((io_bus_PSEL[0] && io_bus_PENABLE) && io_bus_PREADY) && (! io_bus_PWRITE)); + always @ (posedge mainClock) begin + case(io_bus_PADDR) + 20'b00110000000000000000 : begin + if(busCtrl_doWrite)begin + myReg <= io_bus_PWDATA[31 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Apb3Decoder ( + input [19:0] io_input_PADDR, + input [0:0] io_input_PSEL, + input io_input_PENABLE, + output reg io_input_PREADY, + input io_input_PWRITE, + input [31:0] io_input_PWDATA, + output [31:0] io_input_PRDATA, + output reg io_input_PSLVERROR, + output [19:0] io_output_PADDR, + output reg [2:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR +); + wire _zz_1_; + + assign _zz_1_ = (io_input_PSEL[0] && (io_output_PSEL == (3'b000))); + assign io_output_PADDR = io_input_PADDR; + assign io_output_PENABLE = io_input_PENABLE; + assign io_output_PWRITE = io_input_PWRITE; + assign io_output_PWDATA = io_input_PWDATA; + always @ (*) begin + io_output_PSEL[0] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h10000) && io_input_PSEL[0]); + io_output_PSEL[1] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h20000) && io_input_PSEL[0]); + io_output_PSEL[2] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h30000) && io_input_PSEL[0]); + end + + always @ (*) begin + io_input_PREADY = io_output_PREADY; + if(_zz_1_)begin + io_input_PREADY = 1'b1; + end + end + + assign io_input_PRDATA = io_output_PRDATA; + always @ (*) begin + io_input_PSLVERROR = io_output_PSLVERROR; + if(_zz_1_)begin + io_input_PSLVERROR = 1'b1; + end + end + + +endmodule + +module Apb3Router ( + input [19:0] io_input_PADDR, + input [2:0] io_input_PSEL, + input io_input_PENABLE, + output io_input_PREADY, + input io_input_PWRITE, + input [31:0] io_input_PWDATA, + output [31:0] io_input_PRDATA, + output io_input_PSLVERROR, + output [19:0] io_outputs_0_PADDR, + output [0:0] io_outputs_0_PSEL, + output io_outputs_0_PENABLE, + input io_outputs_0_PREADY, + output io_outputs_0_PWRITE, + output [31:0] io_outputs_0_PWDATA, + input [31:0] io_outputs_0_PRDATA, + input io_outputs_0_PSLVERROR, + output [19:0] io_outputs_1_PADDR, + output [0:0] io_outputs_1_PSEL, + output io_outputs_1_PENABLE, + input io_outputs_1_PREADY, + output io_outputs_1_PWRITE, + output [31:0] io_outputs_1_PWDATA, + input [31:0] io_outputs_1_PRDATA, + input io_outputs_1_PSLVERROR, + output [19:0] io_outputs_2_PADDR, + output [0:0] io_outputs_2_PSEL, + output io_outputs_2_PENABLE, + input io_outputs_2_PREADY, + output io_outputs_2_PWRITE, + output [31:0] io_outputs_2_PWDATA, + input [31:0] io_outputs_2_PRDATA, + input io_outputs_2_PSLVERROR, + input mainClock, + input resetCtrl_systemClockReset +); + reg _zz_3_; + reg [31:0] _zz_4_; + reg _zz_5_; + wire _zz_1_; + wire _zz_2_; + reg [1:0] selIndex; + + always @(*) begin + case(selIndex) + 2'b00 : begin + _zz_3_ = io_outputs_0_PREADY; + _zz_4_ = io_outputs_0_PRDATA; + _zz_5_ = io_outputs_0_PSLVERROR; + end + 2'b01 : begin + _zz_3_ = io_outputs_1_PREADY; + _zz_4_ = io_outputs_1_PRDATA; + _zz_5_ = io_outputs_1_PSLVERROR; + end + default : begin + _zz_3_ = io_outputs_2_PREADY; + _zz_4_ = io_outputs_2_PRDATA; + _zz_5_ = io_outputs_2_PSLVERROR; + end + endcase + end + + assign io_outputs_0_PADDR = io_input_PADDR; + assign io_outputs_0_PENABLE = io_input_PENABLE; + assign io_outputs_0_PSEL[0] = io_input_PSEL[0]; + assign io_outputs_0_PWRITE = io_input_PWRITE; + assign io_outputs_0_PWDATA = io_input_PWDATA; + assign io_outputs_1_PADDR = io_input_PADDR; + assign io_outputs_1_PENABLE = io_input_PENABLE; + assign io_outputs_1_PSEL[0] = io_input_PSEL[1]; + assign io_outputs_1_PWRITE = io_input_PWRITE; + assign io_outputs_1_PWDATA = io_input_PWDATA; + assign io_outputs_2_PADDR = io_input_PADDR; + assign io_outputs_2_PENABLE = io_input_PENABLE; + assign io_outputs_2_PSEL[0] = io_input_PSEL[2]; + assign io_outputs_2_PWRITE = io_input_PWRITE; + assign io_outputs_2_PWDATA = io_input_PWDATA; + assign _zz_1_ = io_input_PSEL[1]; + assign _zz_2_ = io_input_PSEL[2]; + assign io_input_PREADY = _zz_3_; + assign io_input_PRDATA = _zz_4_; + assign io_input_PSLVERROR = _zz_5_; + always @ (posedge mainClock) begin + selIndex <= {_zz_2_,_zz_1_}; + end + + +endmodule + +module PipelinedMemoryBusRamUlx3s ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_write, + input [15:0] io_bus_cmd_payload_address, + input [31:0] io_bus_cmd_payload_data, + input [3:0] io_bus_cmd_payload_mask, + output io_bus_rsp_valid, + output [31:0] io_bus_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_4_; + reg _zz_1_; + wire [13:0] _zz_2_; + wire [31:0] _zz_3_; + reg [7:0] ram_symbol0 [0:16383]; + reg [7:0] ram_symbol1 [0:16383]; + reg [7:0] ram_symbol2 [0:16383]; + reg [7:0] ram_symbol3 [0:16383]; + reg [7:0] _zz_5_; + reg [7:0] _zz_6_; + reg [7:0] _zz_7_; + reg [7:0] _zz_8_; + + always @ (*) begin + _zz_4_ = {_zz_8_, _zz_7_, _zz_6_, _zz_5_}; + end + always @ (posedge mainClock) begin + if(io_bus_cmd_valid) begin + _zz_5_ <= ram_symbol0[_zz_2_]; + _zz_6_ <= ram_symbol1[_zz_2_]; + _zz_7_ <= ram_symbol2[_zz_2_]; + _zz_8_ <= ram_symbol3[_zz_2_]; + end + end + + always @ (posedge mainClock) begin + if(io_bus_cmd_payload_mask[0] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol0[_zz_2_] <= _zz_3_[7 : 0]; + end + if(io_bus_cmd_payload_mask[1] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol1[_zz_2_] <= _zz_3_[15 : 8]; + end + if(io_bus_cmd_payload_mask[2] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol2[_zz_2_] <= _zz_3_[23 : 16]; + end + if(io_bus_cmd_payload_mask[3] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol3[_zz_2_] <= _zz_3_[31 : 24]; + end + end + + assign io_bus_rsp_valid = _zz_1_; + assign _zz_2_ = (io_bus_cmd_payload_address >>> 2); + assign _zz_3_ = io_bus_cmd_payload_data; + assign io_bus_rsp_payload_data = _zz_4_; + assign io_bus_cmd_ready = 1'b1; + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_1_ <= 1'b0; + end else begin + _zz_1_ <= ((io_bus_cmd_valid && io_bus_cmd_ready) && (! io_bus_cmd_payload_write)); + end + end + + +endmodule +//PipelinedMemoryBusRamUlx3s_1_ replaced by PipelinedMemoryBusRamUlx3s + +module PipelinedMemoryBusDecoder ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_write, + input [31:0] io_input_cmd_payload_address, + input [31:0] io_input_cmd_payload_data, + input [3:0] io_input_cmd_payload_mask, + output io_input_rsp_valid, + output [31:0] io_input_rsp_payload_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_write, + output [31:0] io_outputs_0_cmd_payload_address, + output [31:0] io_outputs_0_cmd_payload_data, + output [3:0] io_outputs_0_cmd_payload_mask, + input io_outputs_0_rsp_valid, + input [31:0] io_outputs_0_rsp_payload_data, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_write, + output [31:0] io_outputs_1_cmd_payload_address, + output [31:0] io_outputs_1_cmd_payload_data, + output [3:0] io_outputs_1_cmd_payload_mask, + input io_outputs_1_rsp_valid, + input [31:0] io_outputs_1_rsp_payload_data, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_write, + output [31:0] io_outputs_2_cmd_payload_address, + output [31:0] io_outputs_2_cmd_payload_data, + output [3:0] io_outputs_2_cmd_payload_mask, + input io_outputs_2_rsp_valid, + input [31:0] io_outputs_2_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_4_; + wire [1:0] _zz_5_; + wire [0:0] _zz_6_; + wire [1:0] _zz_7_; + wire [0:0] _zz_8_; + wire [1:0] _zz_9_; + wire [1:0] _zz_10_; + wire logic_hits_0; + wire logic_hits_1; + wire logic_hits_2; + wire _zz_1_; + wire _zz_2_; + wire _zz_3_; + wire logic_noHit; + reg [1:0] logic_rspPendingCounter; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + wire logic_rspPending; + wire logic_rspNoHit; + wire logic_cmdWait; + + assign _zz_5_ = (logic_rspPendingCounter + _zz_7_); + assign _zz_6_ = ((io_input_cmd_valid && io_input_cmd_ready) && (! io_input_cmd_payload_write)); + assign _zz_7_ = {1'd0, _zz_6_}; + assign _zz_8_ = io_input_rsp_valid; + assign _zz_9_ = {1'd0, _zz_8_}; + assign _zz_10_ = {logic_rspHits_2,logic_rspHits_1}; + always @(*) begin + case(_zz_10_) + 2'b00 : begin + _zz_4_ = io_outputs_0_rsp_payload_data; + end + 2'b01 : begin + _zz_4_ = io_outputs_1_rsp_payload_data; + end + default : begin + _zz_4_ = io_outputs_2_rsp_payload_data; + end + endcase + end + + assign logic_hits_0 = ((io_input_cmd_payload_address & (~ 32'h000fffff)) == 32'hf0000000); + always @ (*) begin + io_outputs_0_cmd_valid = (io_input_cmd_valid && logic_hits_0); + if(logic_cmdWait)begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_1_ = io_input_cmd_payload_write; + assign io_outputs_0_cmd_payload_write = _zz_1_; + assign io_outputs_0_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_0_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_0_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_1 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80000000); + always @ (*) begin + io_outputs_1_cmd_valid = (io_input_cmd_valid && logic_hits_1); + if(logic_cmdWait)begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_2_ = io_input_cmd_payload_write; + assign io_outputs_1_cmd_payload_write = _zz_2_; + assign io_outputs_1_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_1_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_1_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_2 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80010000); + always @ (*) begin + io_outputs_2_cmd_valid = (io_input_cmd_valid && logic_hits_2); + if(logic_cmdWait)begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_3_ = io_input_cmd_payload_write; + assign io_outputs_2_cmd_payload_write = _zz_3_; + assign io_outputs_2_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_2_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_2_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_noHit = (! ({logic_hits_2,{logic_hits_1,logic_hits_0}} != (3'b000))); + always @ (*) begin + io_input_cmd_ready = (({(logic_hits_2 && io_outputs_2_cmd_ready),{(logic_hits_1 && io_outputs_1_cmd_ready),(logic_hits_0 && io_outputs_0_cmd_ready)}} != (3'b000)) || logic_noHit); + if(logic_cmdWait)begin + io_input_cmd_ready = 1'b0; + end + end + + assign logic_rspPending = (logic_rspPendingCounter != (2'b00)); + assign logic_rspNoHit = (! ({logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}} != (3'b000))); + assign io_input_rsp_valid = (({io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}} != (3'b000)) || (logic_rspPending && logic_rspNoHit)); + assign io_input_rsp_payload_data = _zz_4_; + assign logic_cmdWait = (((io_input_cmd_valid && logic_rspPending) && (((logic_hits_0 != logic_rspHits_0) || (logic_hits_1 != logic_rspHits_1)) || (logic_hits_2 != logic_rspHits_2))) || (logic_rspPendingCounter == (2'b11))); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + logic_rspPendingCounter <= (2'b00); + end else begin + logic_rspPendingCounter <= (_zz_5_ - _zz_9_); + end + end + + always @ (posedge mainClock) begin + if((io_input_cmd_valid && io_input_cmd_ready))begin + logic_rspHits_0 <= logic_hits_0; + logic_rspHits_1 <= logic_hits_1; + logic_rspHits_2 <= logic_hits_2; + end + end + + +endmodule + +module PipelinedMemoryBusDecoder_1_ ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_write, + input [31:0] io_input_cmd_payload_address, + input [31:0] io_input_cmd_payload_data, + input [3:0] io_input_cmd_payload_mask, + output io_input_rsp_valid, + output [31:0] io_input_rsp_payload_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_write, + output [31:0] io_outputs_0_cmd_payload_address, + output [31:0] io_outputs_0_cmd_payload_data, + output [3:0] io_outputs_0_cmd_payload_mask, + input io_outputs_0_rsp_valid, + input [31:0] io_outputs_0_rsp_payload_data, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_write, + output [31:0] io_outputs_1_cmd_payload_address, + output [31:0] io_outputs_1_cmd_payload_data, + output [3:0] io_outputs_1_cmd_payload_mask, + input io_outputs_1_rsp_valid, + input [31:0] io_outputs_1_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + reg [31:0] _zz_3_; + wire [1:0] _zz_4_; + wire [0:0] _zz_5_; + wire [1:0] _zz_6_; + wire [0:0] _zz_7_; + wire [1:0] _zz_8_; + wire [0:0] _zz_9_; + wire logic_hits_0; + wire logic_hits_1; + wire _zz_1_; + wire _zz_2_; + wire logic_noHit; + reg [1:0] logic_rspPendingCounter; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHit; + wire logic_cmdWait; + + assign _zz_4_ = (logic_rspPendingCounter + _zz_6_); + assign _zz_5_ = ((io_input_cmd_valid && io_input_cmd_ready) && (! io_input_cmd_payload_write)); + assign _zz_6_ = {1'd0, _zz_5_}; + assign _zz_7_ = io_input_rsp_valid; + assign _zz_8_ = {1'd0, _zz_7_}; + assign _zz_9_ = logic_rspHits_1; + always @(*) begin + case(_zz_9_) + 1'b0 : begin + _zz_3_ = io_outputs_0_rsp_payload_data; + end + default : begin + _zz_3_ = io_outputs_1_rsp_payload_data; + end + endcase + end + + assign logic_hits_0 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80000000); + always @ (*) begin + io_outputs_0_cmd_valid = (io_input_cmd_valid && logic_hits_0); + if(logic_cmdWait)begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_1_ = io_input_cmd_payload_write; + assign io_outputs_0_cmd_payload_write = _zz_1_; + assign io_outputs_0_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_0_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_0_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_hits_1 = ((io_input_cmd_payload_address & (~ 32'h0000ffff)) == 32'h80010000); + always @ (*) begin + io_outputs_1_cmd_valid = (io_input_cmd_valid && logic_hits_1); + if(logic_cmdWait)begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_2_ = io_input_cmd_payload_write; + assign io_outputs_1_cmd_payload_write = _zz_2_; + assign io_outputs_1_cmd_payload_address = io_input_cmd_payload_address; + assign io_outputs_1_cmd_payload_data = io_input_cmd_payload_data; + assign io_outputs_1_cmd_payload_mask = io_input_cmd_payload_mask; + assign logic_noHit = (! ({logic_hits_1,logic_hits_0} != (2'b00))); + always @ (*) begin + io_input_cmd_ready = (({(logic_hits_1 && io_outputs_1_cmd_ready),(logic_hits_0 && io_outputs_0_cmd_ready)} != (2'b00)) || logic_noHit); + if(logic_cmdWait)begin + io_input_cmd_ready = 1'b0; + end + end + + assign logic_rspPending = (logic_rspPendingCounter != (2'b00)); + assign logic_rspNoHit = (! ({logic_rspHits_1,logic_rspHits_0} != (2'b00))); + assign io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != (2'b00)) || (logic_rspPending && logic_rspNoHit)); + assign io_input_rsp_payload_data = _zz_3_; + assign logic_cmdWait = (((io_input_cmd_valid && logic_rspPending) && ((logic_hits_0 != logic_rspHits_0) || (logic_hits_1 != logic_rspHits_1))) || (logic_rspPendingCounter == (2'b11))); + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + logic_rspPendingCounter <= (2'b00); + end else begin + logic_rspPendingCounter <= (_zz_4_ - _zz_8_); + end + end + + always @ (posedge mainClock) begin + if((io_input_cmd_valid && io_input_cmd_ready))begin + logic_rspHits_0 <= logic_hits_0; + logic_rspHits_1 <= logic_hits_1; + end + end + + +endmodule + +module PipelinedMemoryBusArbiter ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_write, + input [31:0] io_inputs_0_cmd_payload_address, + input [31:0] io_inputs_0_cmd_payload_data, + input [3:0] io_inputs_0_cmd_payload_mask, + output io_inputs_0_rsp_valid, + output [31:0] io_inputs_0_rsp_payload_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_write, + output [31:0] io_output_cmd_payload_address, + output [31:0] io_output_cmd_payload_data, + output [3:0] io_output_cmd_payload_mask, + input io_output_rsp_valid, + input [31:0] io_output_rsp_payload_data +); + + assign io_output_cmd_valid = io_inputs_0_cmd_valid; + assign io_output_cmd_payload_write = io_inputs_0_cmd_payload_write; + assign io_output_cmd_payload_address = io_inputs_0_cmd_payload_address; + assign io_output_cmd_payload_data = io_inputs_0_cmd_payload_data; + assign io_output_cmd_payload_mask = io_inputs_0_cmd_payload_mask; + assign io_inputs_0_cmd_ready = io_output_cmd_ready; + assign io_inputs_0_rsp_valid = io_output_rsp_valid; + assign io_inputs_0_rsp_payload_data = io_output_rsp_payload_data; + +endmodule + +module PipelinedMemoryBusArbiter_1_ ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_write, + input [15:0] io_inputs_0_cmd_payload_address, + input [31:0] io_inputs_0_cmd_payload_data, + input [3:0] io_inputs_0_cmd_payload_mask, + output io_inputs_0_rsp_valid, + output [31:0] io_inputs_0_rsp_payload_data, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_write, + input [15:0] io_inputs_1_cmd_payload_address, + input [31:0] io_inputs_1_cmd_payload_data, + input [3:0] io_inputs_1_cmd_payload_mask, + output io_inputs_1_rsp_valid, + output [31:0] io_inputs_1_rsp_payload_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_write, + output [15:0] io_output_cmd_payload_address, + output [31:0] io_output_cmd_payload_data, + output [3:0] io_output_cmd_payload_mask, + input io_output_rsp_valid, + input [31:0] io_output_rsp_payload_data, + input mainClock, + input resetCtrl_systemClockReset +); + wire _zz_1_; + wire logic_arbiter_io_inputs_0_ready; + wire logic_arbiter_io_inputs_1_ready; + wire logic_arbiter_io_output_valid; + wire logic_arbiter_io_output_payload_write; + wire [15:0] logic_arbiter_io_output_payload_address; + wire [31:0] logic_arbiter_io_output_payload_data; + wire [3:0] logic_arbiter_io_output_payload_mask; + wire [0:0] logic_arbiter_io_chosen; + wire [1:0] logic_arbiter_io_chosenOH; + wire streamFork_2__io_input_ready; + wire streamFork_2__io_outputs_0_valid; + wire streamFork_2__io_outputs_0_payload_write; + wire [15:0] streamFork_2__io_outputs_0_payload_address; + wire [31:0] streamFork_2__io_outputs_0_payload_data; + wire [3:0] streamFork_2__io_outputs_0_payload_mask; + wire streamFork_2__io_outputs_1_valid; + wire streamFork_2__io_outputs_1_payload_write; + wire [15:0] streamFork_2__io_outputs_1_payload_address; + wire [31:0] streamFork_2__io_outputs_1_payload_data; + wire [3:0] streamFork_2__io_outputs_1_payload_mask; + wire streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready; + wire streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_valid; + wire [1:0] streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload; + wire [2:0] streamFork_2__io_outputs_1_translated_thrown_fifo_io_occupancy; + wire [1:0] logic_rspRouteOh; + wire streamFork_2__io_outputs_1_translated_valid; + reg streamFork_2__io_outputs_1_translated_ready; + wire [1:0] streamFork_2__io_outputs_1_translated_payload; + reg streamFork_2__io_outputs_1_translated_thrown_valid; + wire streamFork_2__io_outputs_1_translated_thrown_ready; + wire [1:0] streamFork_2__io_outputs_1_translated_thrown_payload; + + StreamArbiter logic_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (logic_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_write (io_inputs_0_cmd_payload_write ), //i + .io_inputs_0_payload_address (io_inputs_0_cmd_payload_address[15:0] ), //i + .io_inputs_0_payload_data (io_inputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_0_payload_mask (io_inputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (logic_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_write (io_inputs_1_cmd_payload_write ), //i + .io_inputs_1_payload_address (io_inputs_1_cmd_payload_address[15:0] ), //i + .io_inputs_1_payload_data (io_inputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_1_payload_mask (io_inputs_1_cmd_payload_mask[3:0] ), //i + .io_output_valid (logic_arbiter_io_output_valid ), //o + .io_output_ready (streamFork_2__io_input_ready ), //i + .io_output_payload_write (logic_arbiter_io_output_payload_write ), //o + .io_output_payload_address (logic_arbiter_io_output_payload_address[15:0] ), //o + .io_output_payload_data (logic_arbiter_io_output_payload_data[31:0] ), //o + .io_output_payload_mask (logic_arbiter_io_output_payload_mask[3:0] ), //o + .io_chosen (logic_arbiter_io_chosen ), //o + .io_chosenOH (logic_arbiter_io_chosenOH[1:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFork streamFork_2_ ( + .io_input_valid (logic_arbiter_io_output_valid ), //i + .io_input_ready (streamFork_2__io_input_ready ), //o + .io_input_payload_write (logic_arbiter_io_output_payload_write ), //i + .io_input_payload_address (logic_arbiter_io_output_payload_address[15:0] ), //i + .io_input_payload_data (logic_arbiter_io_output_payload_data[31:0] ), //i + .io_input_payload_mask (logic_arbiter_io_output_payload_mask[3:0] ), //i + .io_outputs_0_valid (streamFork_2__io_outputs_0_valid ), //o + .io_outputs_0_ready (io_output_cmd_ready ), //i + .io_outputs_0_payload_write (streamFork_2__io_outputs_0_payload_write ), //o + .io_outputs_0_payload_address (streamFork_2__io_outputs_0_payload_address[15:0] ), //o + .io_outputs_0_payload_data (streamFork_2__io_outputs_0_payload_data[31:0] ), //o + .io_outputs_0_payload_mask (streamFork_2__io_outputs_0_payload_mask[3:0] ), //o + .io_outputs_1_valid (streamFork_2__io_outputs_1_valid ), //o + .io_outputs_1_ready (streamFork_2__io_outputs_1_translated_ready ), //i + .io_outputs_1_payload_write (streamFork_2__io_outputs_1_payload_write ), //o + .io_outputs_1_payload_address (streamFork_2__io_outputs_1_payload_address[15:0] ), //o + .io_outputs_1_payload_data (streamFork_2__io_outputs_1_payload_data[31:0] ), //o + .io_outputs_1_payload_mask (streamFork_2__io_outputs_1_payload_mask[3:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + StreamFifoLowLatency_1_ streamFork_2__io_outputs_1_translated_thrown_fifo ( + .io_push_valid (streamFork_2__io_outputs_1_translated_thrown_valid ), //i + .io_push_ready (streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready ), //o + .io_push_payload (streamFork_2__io_outputs_1_translated_thrown_payload[1:0] ), //i + .io_pop_valid (streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_valid ), //o + .io_pop_ready (io_output_rsp_valid ), //i + .io_pop_payload (streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload[1:0] ), //o + .io_flush (_zz_1_ ), //i + .io_occupancy (streamFork_2__io_outputs_1_translated_thrown_fifo_io_occupancy[2:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign io_inputs_0_cmd_ready = logic_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = logic_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = streamFork_2__io_outputs_0_valid; + assign io_output_cmd_payload_write = streamFork_2__io_outputs_0_payload_write; + assign io_output_cmd_payload_address = streamFork_2__io_outputs_0_payload_address; + assign io_output_cmd_payload_data = streamFork_2__io_outputs_0_payload_data; + assign io_output_cmd_payload_mask = streamFork_2__io_outputs_0_payload_mask; + assign streamFork_2__io_outputs_1_translated_valid = streamFork_2__io_outputs_1_valid; + assign streamFork_2__io_outputs_1_translated_payload = logic_arbiter_io_chosenOH; + always @ (*) begin + streamFork_2__io_outputs_1_translated_thrown_valid = streamFork_2__io_outputs_1_translated_valid; + if(streamFork_2__io_outputs_1_payload_write)begin + streamFork_2__io_outputs_1_translated_thrown_valid = 1'b0; + end + end + + always @ (*) begin + streamFork_2__io_outputs_1_translated_ready = streamFork_2__io_outputs_1_translated_thrown_ready; + if(streamFork_2__io_outputs_1_payload_write)begin + streamFork_2__io_outputs_1_translated_ready = 1'b1; + end + end + + assign streamFork_2__io_outputs_1_translated_thrown_payload = streamFork_2__io_outputs_1_translated_payload; + assign streamFork_2__io_outputs_1_translated_thrown_ready = streamFork_2__io_outputs_1_translated_thrown_fifo_io_push_ready; + assign logic_rspRouteOh = streamFork_2__io_outputs_1_translated_thrown_fifo_io_pop_payload; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && logic_rspRouteOh[0]); + assign io_inputs_0_rsp_payload_data = io_output_rsp_payload_data; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && logic_rspRouteOh[1]); + assign io_inputs_1_rsp_payload_data = io_output_rsp_payload_data; + assign _zz_1_ = 1'b0; + +endmodule +//PipelinedMemoryBusArbiter_2_ replaced by PipelinedMemoryBusArbiter_1_ + +module PQVexRiscvUlx3s ( + input io_asyncReset, + input io_mainClock, + output io_uart_txd, + input io_uart_rxd, + input io_jtag_tms, + input io_jtag_tdi, + output io_jtag_tdo, + input io_jtag_tck +); + wire _zz_36_; + wire _zz_37_; + wire [7:0] _zz_38_; + wire _zz_39_; + wire [4:0] _zz_40_; + wire [7:0] _zz_41_; + wire _zz_42_; + wire [15:0] _zz_43_; + wire [15:0] _zz_44_; + wire [15:0] _zz_45_; + wire [15:0] _zz_46_; + wire asyncReset_buffercc_io_dataOut; + wire core_cpu_iBus_cmd_valid; + wire [31:0] core_cpu_iBus_cmd_payload_pc; + wire core_cpu_debug_bus_cmd_ready; + wire [31:0] core_cpu_debug_bus_rsp_data; + wire core_cpu_debug_resetOut; + wire core_cpu_dBus_cmd_valid; + wire core_cpu_dBus_cmd_payload_wr; + wire [31:0] core_cpu_dBus_cmd_payload_address; + wire [31:0] core_cpu_dBus_cmd_payload_data; + wire [1:0] core_cpu_dBus_cmd_payload_size; + wire jtagBridge_1__io_jtag_tdo; + wire jtagBridge_1__io_remote_cmd_valid; + wire jtagBridge_1__io_remote_cmd_payload_last; + wire [0:0] jtagBridge_1__io_remote_cmd_payload_fragment; + wire jtagBridge_1__io_remote_rsp_ready; + wire systemDebugger_1__io_remote_cmd_ready; + wire systemDebugger_1__io_remote_rsp_valid; + wire systemDebugger_1__io_remote_rsp_payload_error; + wire [31:0] systemDebugger_1__io_remote_rsp_payload_data; + wire systemDebugger_1__io_mem_cmd_valid; + wire [31:0] systemDebugger_1__io_mem_cmd_payload_address; + wire [31:0] systemDebugger_1__io_mem_cmd_payload_data; + wire systemDebugger_1__io_mem_cmd_payload_wr; + wire [1:0] systemDebugger_1__io_mem_cmd_payload_size; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data; + wire [19:0] pipelinedMemoryBusToApbBridge_1__io_apb_PADDR; + wire [0:0] pipelinedMemoryBusToApbBridge_1__io_apb_PSEL; + wire pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE; + wire pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA; + wire apb3UartCtrl_1__io_apb_PREADY; + wire [31:0] apb3UartCtrl_1__io_apb_PRDATA; + wire apb3UartCtrl_1__io_uart_txd; + wire apb3UartCtrl_1__io_interrupt; + wire muraxApb3Timer_1__io_apb_PREADY; + wire [31:0] muraxApb3Timer_1__io_apb_PRDATA; + wire muraxApb3Timer_1__io_apb_PSLVERROR; + wire muraxApb3Timer_1__io_interrupt; + wire myMem_1__io_bus_PREADY; + wire [31:0] myMem_1__io_bus_PRDATA; + wire myMem_1__io_bus_PSLVERROR; + wire io_apb_decoder_io_input_PREADY; + wire [31:0] io_apb_decoder_io_input_PRDATA; + wire io_apb_decoder_io_input_PSLVERROR; + wire [19:0] io_apb_decoder_io_output_PADDR; + wire [2:0] io_apb_decoder_io_output_PSEL; + wire io_apb_decoder_io_output_PENABLE; + wire io_apb_decoder_io_output_PWRITE; + wire [31:0] io_apb_decoder_io_output_PWDATA; + wire apb3Router_1__io_input_PREADY; + wire [31:0] apb3Router_1__io_input_PRDATA; + wire apb3Router_1__io_input_PSLVERROR; + wire [19:0] apb3Router_1__io_outputs_0_PADDR; + wire [0:0] apb3Router_1__io_outputs_0_PSEL; + wire apb3Router_1__io_outputs_0_PENABLE; + wire apb3Router_1__io_outputs_0_PWRITE; + wire [31:0] apb3Router_1__io_outputs_0_PWDATA; + wire [19:0] apb3Router_1__io_outputs_1_PADDR; + wire [0:0] apb3Router_1__io_outputs_1_PSEL; + wire apb3Router_1__io_outputs_1_PENABLE; + wire apb3Router_1__io_outputs_1_PWRITE; + wire [31:0] apb3Router_1__io_outputs_1_PWDATA; + wire [19:0] apb3Router_1__io_outputs_2_PADDR; + wire [0:0] apb3Router_1__io_outputs_2_PSEL; + wire apb3Router_1__io_outputs_2_PENABLE; + wire apb3Router_1__io_outputs_2_PWRITE; + wire [31:0] apb3Router_1__io_outputs_2_PWDATA; + wire memory_ramBlocks_0_io_bus_cmd_ready; + wire memory_ramBlocks_0_io_bus_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_cmd_ready; + wire memory_ramBlocks_1_io_bus_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_rsp_payload_data; + wire core_dbus_decoder_io_input_cmd_ready; + wire core_dbus_decoder_io_input_rsp_valid; + wire [31:0] core_dbus_decoder_io_input_rsp_payload_data; + wire core_dbus_decoder_io_outputs_0_cmd_valid; + wire core_dbus_decoder_io_outputs_0_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_0_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_0_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_0_cmd_payload_mask; + wire core_dbus_decoder_io_outputs_1_cmd_valid; + wire core_dbus_decoder_io_outputs_1_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_1_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_1_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_1_cmd_payload_mask; + wire core_dbus_decoder_io_outputs_2_cmd_valid; + wire core_dbus_decoder_io_outputs_2_cmd_payload_write; + wire [31:0] core_dbus_decoder_io_outputs_2_cmd_payload_address; + wire [31:0] core_dbus_decoder_io_outputs_2_cmd_payload_data; + wire [3:0] core_dbus_decoder_io_outputs_2_cmd_payload_mask; + wire core_ibus_decoder_io_input_cmd_ready; + wire core_ibus_decoder_io_input_rsp_valid; + wire [31:0] core_ibus_decoder_io_input_rsp_payload_data; + wire core_ibus_decoder_io_outputs_0_cmd_valid; + wire core_ibus_decoder_io_outputs_0_cmd_payload_write; + wire [31:0] core_ibus_decoder_io_outputs_0_cmd_payload_address; + wire [31:0] core_ibus_decoder_io_outputs_0_cmd_payload_data; + wire [3:0] core_ibus_decoder_io_outputs_0_cmd_payload_mask; + wire core_ibus_decoder_io_outputs_1_cmd_valid; + wire core_ibus_decoder_io_outputs_1_cmd_payload_write; + wire [31:0] core_ibus_decoder_io_outputs_1_cmd_payload_address; + wire [31:0] core_ibus_decoder_io_outputs_1_cmd_payload_data; + wire [3:0] core_ibus_decoder_io_outputs_1_cmd_payload_mask; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid; + wire pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address; + wire [31:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data; + wire [3:0] pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready; + wire memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data; + wire memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid; + wire memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write; + wire [15:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address; + wire [31:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data; + wire [3:0] memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready; + wire memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data; + wire memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid; + wire memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write; + wire [15:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address; + wire [31:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data; + wire [3:0] memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask; + wire _zz_47_; + wire _zz_48_; + wire asyncReset; + wire mainClock; + wire resetCtrl_bufferedReset; + reg resetCtrl_mainClockReset; + reg resetCtrl_systemClockReset; + reg core_timerInterrupt; + reg core_externalInterrupt; + wire core_ibus_cmd_valid; + wire core_ibus_cmd_ready; + wire core_ibus_cmd_payload_write; + wire [31:0] core_ibus_cmd_payload_address; + wire [31:0] core_ibus_cmd_payload_data; + wire [3:0] core_ibus_cmd_payload_mask; + wire core_ibus_rsp_valid; + wire [31:0] core_ibus_rsp_payload_data; + wire core_dbus_cmd_valid; + wire core_dbus_cmd_ready; + wire core_dbus_cmd_payload_write; + wire [31:0] core_dbus_cmd_payload_address; + wire [31:0] core_dbus_cmd_payload_data; + wire [3:0] core_dbus_cmd_payload_mask; + wire core_dbus_rsp_valid; + wire [31:0] core_dbus_rsp_payload_data; + wire _zz_1_; + wire _zz_2_; + wire [31:0] _zz_3_; + wire _zz_4_; + reg _zz_5_; + reg _zz_6_; + reg [31:0] _zz_7_; + reg [31:0] _zz_8_; + reg [3:0] _zz_9_; + wire _zz_10_; + reg _zz_11_; + reg _zz_12_; + reg [31:0] _zz_13_; + reg [31:0] _zz_14_; + reg [3:0] _zz_15_; + wire _zz_16_; + wire _zz_17_; + wire _zz_18_; + wire [31:0] _zz_19_; + wire [31:0] _zz_20_; + wire [3:0] _zz_21_; + reg [3:0] _zz_22_; + wire _zz_23_; + reg _zz_24_; + reg _zz_25_; + reg [31:0] _zz_26_; + reg [31:0] _zz_27_; + reg [3:0] _zz_28_; + wire _zz_29_; + reg _zz_30_; + reg _zz_31_; + reg [31:0] _zz_32_; + reg [31:0] _zz_33_; + reg [3:0] _zz_34_; + reg core_cpu_debug_resetOut_regNext; + reg _zz_35_; + + assign _zz_47_ = (_zz_2_ && (! _zz_4_)); + assign _zz_48_ = (_zz_17_ && (! _zz_23_)); + BufferCC_2_ asyncReset_buffercc ( + .io_dataIn (asyncReset ), //i + .io_dataOut (asyncReset_buffercc_io_dataOut ), //o + .mainClock (mainClock ) //i + ); + VexRiscv core_cpu ( + .iBus_cmd_valid (core_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (_zz_2_ ), //i + .iBus_cmd_payload_pc (core_cpu_iBus_cmd_payload_pc[31:0] ), //o + .iBus_rsp_valid (core_ibus_rsp_valid ), //i + .iBus_rsp_payload_error (_zz_36_ ), //i + .iBus_rsp_payload_inst (core_ibus_rsp_payload_data[31:0] ), //i + .timerInterrupt (core_timerInterrupt ), //i + .externalInterrupt (core_externalInterrupt ), //i + .softwareInterrupt (_zz_37_ ), //i + .debug_bus_cmd_valid (systemDebugger_1__io_mem_cmd_valid ), //i + .debug_bus_cmd_ready (core_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (systemDebugger_1__io_mem_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (_zz_38_[7:0] ), //i + .debug_bus_cmd_payload_data (systemDebugger_1__io_mem_cmd_payload_data[31:0] ), //i + .debug_bus_rsp_data (core_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (core_cpu_debug_resetOut ), //o + .dBus_cmd_valid (core_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (_zz_17_ ), //i + .dBus_cmd_payload_wr (core_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_address (core_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (core_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_size (core_cpu_dBus_cmd_payload_size[1:0] ), //o + .dBus_rsp_ready (core_dbus_rsp_valid ), //i + .dBus_rsp_error (_zz_39_ ), //i + .dBus_rsp_data (core_dbus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + JtagBridge jtagBridge_1_ ( + .io_jtag_tms (io_jtag_tms ), //i + .io_jtag_tdi (io_jtag_tdi ), //i + .io_jtag_tdo (jtagBridge_1__io_jtag_tdo ), //o + .io_jtag_tck (io_jtag_tck ), //i + .io_remote_cmd_valid (jtagBridge_1__io_remote_cmd_valid ), //o + .io_remote_cmd_ready (systemDebugger_1__io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (jtagBridge_1__io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (jtagBridge_1__io_remote_cmd_payload_fragment ), //o + .io_remote_rsp_valid (systemDebugger_1__io_remote_rsp_valid ), //i + .io_remote_rsp_ready (jtagBridge_1__io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (systemDebugger_1__io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (systemDebugger_1__io_remote_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + SystemDebugger systemDebugger_1_ ( + .io_remote_cmd_valid (jtagBridge_1__io_remote_cmd_valid ), //i + .io_remote_cmd_ready (systemDebugger_1__io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (jtagBridge_1__io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (jtagBridge_1__io_remote_cmd_payload_fragment ), //i + .io_remote_rsp_valid (systemDebugger_1__io_remote_rsp_valid ), //o + .io_remote_rsp_ready (jtagBridge_1__io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (systemDebugger_1__io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (systemDebugger_1__io_remote_rsp_payload_data[31:0] ), //o + .io_mem_cmd_valid (systemDebugger_1__io_mem_cmd_valid ), //o + .io_mem_cmd_ready (core_cpu_debug_bus_cmd_ready ), //i + .io_mem_cmd_payload_address (systemDebugger_1__io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (systemDebugger_1__io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (systemDebugger_1__io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (systemDebugger_1__io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (_zz_35_ ), //i + .io_mem_rsp_payload (core_cpu_debug_bus_rsp_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_mainClockReset (resetCtrl_mainClockReset ) //i + ); + PipelinedMemoryBusToApbBridge pipelinedMemoryBusToApbBridge_1_ ( + .io_pipelinedMemoryBus_cmd_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid ), //i + .io_pipelinedMemoryBus_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready ), //o + .io_pipelinedMemoryBus_cmd_payload_write (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write ), //i + .io_pipelinedMemoryBus_cmd_payload_address (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address[31:0] ), //i + .io_pipelinedMemoryBus_cmd_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_pipelinedMemoryBus_cmd_payload_mask (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_pipelinedMemoryBus_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid ), //o + .io_pipelinedMemoryBus_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data[31:0] ), //o + .io_apb_PADDR (pipelinedMemoryBusToApbBridge_1__io_apb_PADDR[19:0] ), //o + .io_apb_PSEL (pipelinedMemoryBusToApbBridge_1__io_apb_PSEL ), //o + .io_apb_PENABLE (pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE ), //o + .io_apb_PREADY (io_apb_decoder_io_input_PREADY ), //i + .io_apb_PWRITE (pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE ), //o + .io_apb_PWDATA (pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA[31:0] ), //o + .io_apb_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //i + .io_apb_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Apb3UartCtrl apb3UartCtrl_1_ ( + .io_apb_PADDR (_zz_40_[4:0] ), //i + .io_apb_PSEL (apb3Router_1__io_outputs_0_PSEL ), //i + .io_apb_PENABLE (apb3Router_1__io_outputs_0_PENABLE ), //i + .io_apb_PREADY (apb3UartCtrl_1__io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1__io_outputs_0_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1__io_outputs_0_PWDATA[31:0] ), //i + .io_apb_PRDATA (apb3UartCtrl_1__io_apb_PRDATA[31:0] ), //o + .io_uart_txd (apb3UartCtrl_1__io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_interrupt (apb3UartCtrl_1__io_interrupt ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + MuraxApb3Timer muraxApb3Timer_1_ ( + .io_apb_PADDR (_zz_41_[7:0] ), //i + .io_apb_PSEL (apb3Router_1__io_outputs_1_PSEL ), //i + .io_apb_PENABLE (apb3Router_1__io_outputs_1_PENABLE ), //i + .io_apb_PREADY (muraxApb3Timer_1__io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1__io_outputs_1_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1__io_outputs_1_PWDATA[31:0] ), //i + .io_apb_PRDATA (muraxApb3Timer_1__io_apb_PRDATA[31:0] ), //o + .io_apb_PSLVERROR (muraxApb3Timer_1__io_apb_PSLVERROR ), //o + .io_interrupt (muraxApb3Timer_1__io_interrupt ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + MyMem myMem_1_ ( + .io_bus_PADDR (apb3Router_1__io_outputs_2_PADDR[19:0] ), //i + .io_bus_PSEL (apb3Router_1__io_outputs_2_PSEL ), //i + .io_bus_PENABLE (apb3Router_1__io_outputs_2_PENABLE ), //i + .io_bus_PREADY (myMem_1__io_bus_PREADY ), //o + .io_bus_PWRITE (apb3Router_1__io_outputs_2_PWRITE ), //i + .io_bus_PWDATA (apb3Router_1__io_outputs_2_PWDATA[31:0] ), //i + .io_bus_PRDATA (myMem_1__io_bus_PRDATA[31:0] ), //o + .io_bus_PSLVERROR (myMem_1__io_bus_PSLVERROR ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + Apb3Decoder io_apb_decoder ( + .io_input_PADDR (pipelinedMemoryBusToApbBridge_1__io_apb_PADDR[19:0] ), //i + .io_input_PSEL (pipelinedMemoryBusToApbBridge_1__io_apb_PSEL ), //i + .io_input_PENABLE (pipelinedMemoryBusToApbBridge_1__io_apb_PENABLE ), //i + .io_input_PREADY (io_apb_decoder_io_input_PREADY ), //o + .io_input_PWRITE (pipelinedMemoryBusToApbBridge_1__io_apb_PWRITE ), //i + .io_input_PWDATA (pipelinedMemoryBusToApbBridge_1__io_apb_PWDATA[31:0] ), //i + .io_input_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //o + .io_output_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //o + .io_output_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //o + .io_output_PENABLE (io_apb_decoder_io_output_PENABLE ), //o + .io_output_PREADY (apb3Router_1__io_input_PREADY ), //i + .io_output_PWRITE (io_apb_decoder_io_output_PWRITE ), //o + .io_output_PWDATA (io_apb_decoder_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (apb3Router_1__io_input_PRDATA[31:0] ), //i + .io_output_PSLVERROR (apb3Router_1__io_input_PSLVERROR ) //i + ); + Apb3Router apb3Router_1_ ( + .io_input_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //i + .io_input_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //i + .io_input_PENABLE (io_apb_decoder_io_output_PENABLE ), //i + .io_input_PREADY (apb3Router_1__io_input_PREADY ), //o + .io_input_PWRITE (io_apb_decoder_io_output_PWRITE ), //i + .io_input_PWDATA (io_apb_decoder_io_output_PWDATA[31:0] ), //i + .io_input_PRDATA (apb3Router_1__io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (apb3Router_1__io_input_PSLVERROR ), //o + .io_outputs_0_PADDR (apb3Router_1__io_outputs_0_PADDR[19:0] ), //o + .io_outputs_0_PSEL (apb3Router_1__io_outputs_0_PSEL ), //o + .io_outputs_0_PENABLE (apb3Router_1__io_outputs_0_PENABLE ), //o + .io_outputs_0_PREADY (apb3UartCtrl_1__io_apb_PREADY ), //i + .io_outputs_0_PWRITE (apb3Router_1__io_outputs_0_PWRITE ), //o + .io_outputs_0_PWDATA (apb3Router_1__io_outputs_0_PWDATA[31:0] ), //o + .io_outputs_0_PRDATA (apb3UartCtrl_1__io_apb_PRDATA[31:0] ), //i + .io_outputs_0_PSLVERROR (_zz_42_ ), //i + .io_outputs_1_PADDR (apb3Router_1__io_outputs_1_PADDR[19:0] ), //o + .io_outputs_1_PSEL (apb3Router_1__io_outputs_1_PSEL ), //o + .io_outputs_1_PENABLE (apb3Router_1__io_outputs_1_PENABLE ), //o + .io_outputs_1_PREADY (muraxApb3Timer_1__io_apb_PREADY ), //i + .io_outputs_1_PWRITE (apb3Router_1__io_outputs_1_PWRITE ), //o + .io_outputs_1_PWDATA (apb3Router_1__io_outputs_1_PWDATA[31:0] ), //o + .io_outputs_1_PRDATA (muraxApb3Timer_1__io_apb_PRDATA[31:0] ), //i + .io_outputs_1_PSLVERROR (muraxApb3Timer_1__io_apb_PSLVERROR ), //i + .io_outputs_2_PADDR (apb3Router_1__io_outputs_2_PADDR[19:0] ), //o + .io_outputs_2_PSEL (apb3Router_1__io_outputs_2_PSEL ), //o + .io_outputs_2_PENABLE (apb3Router_1__io_outputs_2_PENABLE ), //o + .io_outputs_2_PREADY (myMem_1__io_bus_PREADY ), //i + .io_outputs_2_PWRITE (apb3Router_1__io_outputs_2_PWRITE ), //o + .io_outputs_2_PWDATA (apb3Router_1__io_outputs_2_PWDATA[31:0] ), //o + .io_outputs_2_PRDATA (myMem_1__io_bus_PRDATA[31:0] ), //i + .io_outputs_2_PSLVERROR (myMem_1__io_bus_PSLVERROR ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusRamUlx3s memory_ramBlocks_0 ( + .io_bus_cmd_valid (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid ), //i + .io_bus_cmd_ready (memory_ramBlocks_0_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_write (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write ), //i + .io_bus_cmd_payload_address (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //i + .io_bus_cmd_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_bus_cmd_payload_mask (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_bus_rsp_valid (memory_ramBlocks_0_io_bus_rsp_valid ), //o + .io_bus_rsp_payload_data (memory_ramBlocks_0_io_bus_rsp_payload_data[31:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusRamUlx3s memory_ramBlocks_1 ( + .io_bus_cmd_valid (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid ), //i + .io_bus_cmd_ready (memory_ramBlocks_1_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_write (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write ), //i + .io_bus_cmd_payload_address (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //i + .io_bus_cmd_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //i + .io_bus_cmd_payload_mask (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //i + .io_bus_rsp_valid (memory_ramBlocks_1_io_bus_rsp_valid ), //o + .io_bus_rsp_payload_data (memory_ramBlocks_1_io_bus_rsp_payload_data[31:0] ), //o + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusDecoder core_dbus_decoder ( + .io_input_cmd_valid (core_dbus_cmd_valid ), //i + .io_input_cmd_ready (core_dbus_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_write (core_dbus_cmd_payload_write ), //i + .io_input_cmd_payload_address (core_dbus_cmd_payload_address[31:0] ), //i + .io_input_cmd_payload_data (core_dbus_cmd_payload_data[31:0] ), //i + .io_input_cmd_payload_mask (core_dbus_cmd_payload_mask[3:0] ), //i + .io_input_rsp_valid (core_dbus_decoder_io_input_rsp_valid ), //o + .io_input_rsp_payload_data (core_dbus_decoder_io_input_rsp_payload_data[31:0] ), //o + .io_outputs_0_cmd_valid (core_dbus_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_0_cmd_payload_write ), //o + .io_outputs_0_cmd_payload_address (core_dbus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //o + .io_outputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //o + .io_outputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //o + .io_outputs_0_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_0_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .io_outputs_1_cmd_valid (core_dbus_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_1_cmd_payload_write (core_dbus_decoder_io_outputs_1_cmd_payload_write ), //o + .io_outputs_1_cmd_payload_address (core_dbus_decoder_io_outputs_1_cmd_payload_address[31:0] ), //o + .io_outputs_1_cmd_payload_data (core_dbus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //o + .io_outputs_1_cmd_payload_mask (core_dbus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //o + .io_outputs_1_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_1_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .io_outputs_2_cmd_valid (core_dbus_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready ), //i + .io_outputs_2_cmd_payload_write (core_dbus_decoder_io_outputs_2_cmd_payload_write ), //o + .io_outputs_2_cmd_payload_address (core_dbus_decoder_io_outputs_2_cmd_payload_address[31:0] ), //o + .io_outputs_2_cmd_payload_data (core_dbus_decoder_io_outputs_2_cmd_payload_data[31:0] ), //o + .io_outputs_2_cmd_payload_mask (core_dbus_decoder_io_outputs_2_cmd_payload_mask[3:0] ), //o + .io_outputs_2_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid ), //i + .io_outputs_2_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusDecoder_1_ core_ibus_decoder ( + .io_input_cmd_valid (core_ibus_cmd_valid ), //i + .io_input_cmd_ready (core_ibus_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_write (core_ibus_cmd_payload_write ), //i + .io_input_cmd_payload_address (core_ibus_cmd_payload_address[31:0] ), //i + .io_input_cmd_payload_data (core_ibus_cmd_payload_data[31:0] ), //i + .io_input_cmd_payload_mask (core_ibus_cmd_payload_mask[3:0] ), //i + .io_input_rsp_valid (core_ibus_decoder_io_input_rsp_valid ), //o + .io_input_rsp_payload_data (core_ibus_decoder_io_input_rsp_payload_data[31:0] ), //o + .io_outputs_0_cmd_valid (core_ibus_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_write (core_ibus_decoder_io_outputs_0_cmd_payload_write ), //o + .io_outputs_0_cmd_payload_address (core_ibus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //o + .io_outputs_0_cmd_payload_data (core_ibus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //o + .io_outputs_0_cmd_payload_mask (core_ibus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //o + .io_outputs_0_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //i + .io_outputs_1_cmd_valid (core_ibus_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_1_cmd_payload_write ), //o + .io_outputs_1_cmd_payload_address (core_ibus_decoder_io_outputs_1_cmd_payload_address[31:0] ), //o + .io_outputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //o + .io_outputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //o + .io_outputs_1_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_1_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusArbiter pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_0_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_0_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (core_dbus_decoder_io_outputs_0_cmd_payload_address[31:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_cmd_ready ), //i + .io_output_cmd_payload_write (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_address[31:0] ), //o + .io_output_cmd_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_valid ), //i + .io_output_rsp_payload_data (pipelinedMemoryBusToApbBridge_1__io_pipelinedMemoryBus_rsp_payload_data[31:0] ) //i + ); + PipelinedMemoryBusArbiter_1_ memory_ramBlocks_0_io_bus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_1_cmd_valid ), //i + .io_inputs_0_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_1_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (_zz_43_[15:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_inputs_1_cmd_valid (core_ibus_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_0_cmd_payload_write ), //i + .io_inputs_1_cmd_payload_address (_zz_44_[15:0] ), //i + .io_inputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_0_cmd_payload_data[31:0] ), //i + .io_inputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_0_cmd_payload_mask[3:0] ), //i + .io_inputs_1_rsp_valid (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (memory_ramBlocks_0_io_bus_cmd_ready ), //i + .io_output_cmd_payload_write (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //o + .io_output_cmd_payload_data (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (memory_ramBlocks_0_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (memory_ramBlocks_0_io_bus_rsp_valid ), //i + .io_output_rsp_payload_data (memory_ramBlocks_0_io_bus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + PipelinedMemoryBusArbiter_1_ memory_ramBlocks_1_io_bus_arbiter ( + .io_inputs_0_cmd_valid (core_dbus_decoder_io_outputs_2_cmd_valid ), //i + .io_inputs_0_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_write (core_dbus_decoder_io_outputs_2_cmd_payload_write ), //i + .io_inputs_0_cmd_payload_address (_zz_45_[15:0] ), //i + .io_inputs_0_cmd_payload_data (core_dbus_decoder_io_outputs_2_cmd_payload_data[31:0] ), //i + .io_inputs_0_cmd_payload_mask (core_dbus_decoder_io_outputs_2_cmd_payload_mask[3:0] ), //i + .io_inputs_0_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_0_rsp_payload_data[31:0] ), //o + .io_inputs_1_cmd_valid (core_ibus_decoder_io_outputs_1_cmd_valid ), //i + .io_inputs_1_cmd_ready (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_write (core_ibus_decoder_io_outputs_1_cmd_payload_write ), //i + .io_inputs_1_cmd_payload_address (_zz_46_[15:0] ), //i + .io_inputs_1_cmd_payload_data (core_ibus_decoder_io_outputs_1_cmd_payload_data[31:0] ), //i + .io_inputs_1_cmd_payload_mask (core_ibus_decoder_io_outputs_1_cmd_payload_mask[3:0] ), //i + .io_inputs_1_rsp_valid (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_inputs_1_rsp_payload_data[31:0] ), //o + .io_output_cmd_valid (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (memory_ramBlocks_1_io_bus_cmd_ready ), //i + .io_output_cmd_payload_write (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_write ), //o + .io_output_cmd_payload_address (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_address[15:0] ), //o + .io_output_cmd_payload_data (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_data[31:0] ), //o + .io_output_cmd_payload_mask (memory_ramBlocks_1_io_bus_arbiter_io_output_cmd_payload_mask[3:0] ), //o + .io_output_rsp_valid (memory_ramBlocks_1_io_bus_rsp_valid ), //i + .io_output_rsp_payload_data (memory_ramBlocks_1_io_bus_rsp_payload_data[31:0] ), //i + .mainClock (mainClock ), //i + .resetCtrl_systemClockReset (resetCtrl_systemClockReset ) //i + ); + assign resetCtrl_bufferedReset = asyncReset_buffercc_io_dataOut; + always @ (*) begin + core_timerInterrupt = 1'b0; + if(muraxApb3Timer_1__io_interrupt)begin + core_timerInterrupt = 1'b1; + end + end + + always @ (*) begin + core_externalInterrupt = 1'b0; + if(apb3UartCtrl_1__io_interrupt)begin + core_externalInterrupt = 1'b1; + end + end + + assign _zz_1_ = core_cpu_iBus_cmd_valid; + assign _zz_3_ = core_cpu_iBus_cmd_payload_pc; + assign _zz_36_ = 1'b0; + assign _zz_2_ = (! _zz_5_); + assign _zz_4_ = ((1'b1 && (! _zz_10_)) || core_ibus_cmd_ready); + assign _zz_10_ = _zz_11_; + assign core_ibus_cmd_valid = _zz_10_; + assign core_ibus_cmd_payload_write = _zz_12_; + assign core_ibus_cmd_payload_address = _zz_13_; + assign core_ibus_cmd_payload_data = _zz_14_; + assign core_ibus_cmd_payload_mask = _zz_15_; + assign _zz_16_ = core_cpu_dBus_cmd_valid; + assign _zz_18_ = core_cpu_dBus_cmd_payload_wr; + assign _zz_19_ = core_cpu_dBus_cmd_payload_address; + assign _zz_20_ = core_cpu_dBus_cmd_payload_data; + always @ (*) begin + case(core_cpu_dBus_cmd_payload_size) + 2'b00 : begin + _zz_22_ = (4'b0001); + end + 2'b01 : begin + _zz_22_ = (4'b0011); + end + default : begin + _zz_22_ = (4'b1111); + end + endcase + end + + assign _zz_21_ = (_zz_22_ <<< core_cpu_dBus_cmd_payload_address[1 : 0]); + assign _zz_17_ = (! _zz_24_); + assign _zz_23_ = ((1'b1 && (! _zz_29_)) || core_dbus_cmd_ready); + assign _zz_29_ = _zz_30_; + assign core_dbus_cmd_valid = _zz_29_; + assign core_dbus_cmd_payload_write = _zz_31_; + assign core_dbus_cmd_payload_address = _zz_32_; + assign core_dbus_cmd_payload_data = _zz_33_; + assign core_dbus_cmd_payload_mask = _zz_34_; + assign _zz_39_ = 1'b0; + assign _zz_38_ = systemDebugger_1__io_mem_cmd_payload_address[7:0]; + assign _zz_40_ = apb3Router_1__io_outputs_0_PADDR[4:0]; + assign _zz_42_ = 1'b0; + assign _zz_41_ = apb3Router_1__io_outputs_1_PADDR[7:0]; + assign asyncReset = io_asyncReset; + assign mainClock = io_mainClock; + assign io_uart_txd = apb3UartCtrl_1__io_uart_txd; + assign io_jtag_tdo = jtagBridge_1__io_jtag_tdo; + assign core_dbus_cmd_ready = core_dbus_decoder_io_input_cmd_ready; + assign core_dbus_rsp_valid = core_dbus_decoder_io_input_rsp_valid; + assign core_dbus_rsp_payload_data = core_dbus_decoder_io_input_rsp_payload_data; + assign core_ibus_cmd_ready = core_ibus_decoder_io_input_cmd_ready; + assign core_ibus_rsp_valid = core_ibus_decoder_io_input_rsp_valid; + assign core_ibus_rsp_payload_data = core_ibus_decoder_io_input_rsp_payload_data; + assign _zz_43_ = core_dbus_decoder_io_outputs_1_cmd_payload_address[15:0]; + assign _zz_45_ = core_dbus_decoder_io_outputs_2_cmd_payload_address[15:0]; + assign _zz_44_ = core_ibus_decoder_io_outputs_0_cmd_payload_address[15:0]; + assign _zz_46_ = core_ibus_decoder_io_outputs_1_cmd_payload_address[15:0]; + assign _zz_37_ = 1'b0; + always @ (posedge mainClock) begin + resetCtrl_mainClockReset <= resetCtrl_bufferedReset; + resetCtrl_systemClockReset <= resetCtrl_bufferedReset; + if(core_cpu_debug_resetOut_regNext)begin + resetCtrl_systemClockReset <= 1'b1; + end + end + + always @ (posedge mainClock or posedge resetCtrl_systemClockReset) begin + if (resetCtrl_systemClockReset) begin + _zz_5_ <= 1'b0; + _zz_11_ <= 1'b0; + _zz_24_ <= 1'b0; + _zz_30_ <= 1'b0; + end else begin + if(_zz_4_)begin + _zz_5_ <= 1'b0; + end + if(_zz_47_)begin + _zz_5_ <= _zz_1_; + end + if(_zz_4_)begin + _zz_11_ <= (_zz_1_ || _zz_5_); + end + if(_zz_23_)begin + _zz_24_ <= 1'b0; + end + if(_zz_48_)begin + _zz_24_ <= _zz_16_; + end + if(_zz_23_)begin + _zz_30_ <= (_zz_16_ || _zz_24_); + end + end + end + + always @ (posedge mainClock) begin + if(_zz_47_)begin + _zz_6_ <= 1'b0; + _zz_7_ <= _zz_3_; + _zz_8_ <= 32'h0; + _zz_9_ <= (4'bxxxx); + end + if(_zz_4_)begin + _zz_12_ <= (_zz_5_ ? _zz_6_ : 1'b0); + _zz_13_ <= (_zz_5_ ? _zz_7_ : _zz_3_); + _zz_14_ <= (_zz_5_ ? _zz_8_ : 32'h0); + _zz_15_ <= (_zz_5_ ? _zz_9_ : (4'bxxxx)); + end + if(_zz_48_)begin + _zz_25_ <= _zz_18_; + _zz_26_ <= _zz_19_; + _zz_27_ <= _zz_20_; + _zz_28_ <= _zz_21_; + end + if(_zz_23_)begin + _zz_31_ <= (_zz_24_ ? _zz_25_ : _zz_18_); + _zz_32_ <= (_zz_24_ ? _zz_26_ : _zz_19_); + _zz_33_ <= (_zz_24_ ? _zz_27_ : _zz_20_); + _zz_34_ <= (_zz_24_ ? _zz_28_ : _zz_21_); + end + end + + always @ (posedge mainClock) begin + core_cpu_debug_resetOut_regNext <= core_cpu_debug_resetOut; + end + + always @ (posedge mainClock or posedge resetCtrl_mainClockReset) begin + if (resetCtrl_mainClockReset) begin + _zz_35_ <= 1'b0; + end else begin + _zz_35_ <= (systemDebugger_1__io_mem_cmd_valid && core_cpu_debug_bus_cmd_ready); + end + end + + +endmodule diff --git a/vexriscv/src/main/scala/mupq/MulPlugins.scala b/vexriscv/src/main/scala/quantumrisc/MulPlugins.scala similarity index 99% rename from vexriscv/src/main/scala/mupq/MulPlugins.scala rename to vexriscv/src/main/scala/quantumrisc/MulPlugins.scala index 568939d..7655527 100644 --- a/vexriscv/src/main/scala/mupq/MulPlugins.scala +++ b/vexriscv/src/main/scala/quantumrisc/MulPlugins.scala @@ -1,4 +1,4 @@ -package mupq +package quantumrisc import vexriscv._ import vexriscv.plugin._ diff --git a/vexriscv/src/main/scala/mupq/MyMem.scala b/vexriscv/src/main/scala/quantumrisc/MyMem.scala similarity index 98% rename from vexriscv/src/main/scala/mupq/MyMem.scala rename to vexriscv/src/main/scala/quantumrisc/MyMem.scala index 275e6df..e904ad8 100644 --- a/vexriscv/src/main/scala/mupq/MyMem.scala +++ b/vexriscv/src/main/scala/quantumrisc/MyMem.scala @@ -1,4 +1,4 @@ -package mupq +package quantumrisc import spinal.core._ import spinal.lib._ diff --git a/vexriscv/src/main/scala/mupq/PQVexRiscv.scala b/vexriscv/src/main/scala/quantumrisc/PQVexRiscv.scala similarity index 99% rename from vexriscv/src/main/scala/mupq/PQVexRiscv.scala rename to vexriscv/src/main/scala/quantumrisc/PQVexRiscv.scala index 98c326c..dccbfaf 100644 --- a/vexriscv/src/main/scala/mupq/PQVexRiscv.scala +++ b/vexriscv/src/main/scala/quantumrisc/PQVexRiscv.scala @@ -1,4 +1,4 @@ -package mupq +package quantumrisc import scala.collection.mutable.ArrayBuffer diff --git a/vexriscv/src/main/scala/mupq/PQVexRiscvSim.scala b/vexriscv/src/main/scala/quantumrisc/PQVexRiscvSim.scala similarity index 98% rename from vexriscv/src/main/scala/mupq/PQVexRiscvSim.scala rename to vexriscv/src/main/scala/quantumrisc/PQVexRiscvSim.scala index 9a15603..d08b326 100644 --- a/vexriscv/src/main/scala/mupq/PQVexRiscvSim.scala +++ b/vexriscv/src/main/scala/quantumrisc/PQVexRiscvSim.scala @@ -1,4 +1,4 @@ -package mupq +package quantumrisc import java.io.{File, FileInputStream, FileOutputStream, IOException, OutputStream} @@ -55,7 +55,7 @@ case class PipelinedMemoryBusRam(size : BigInt, initialContent : File = null) ex class PQVexRiscvSim( - val ramBlockSizes : Seq[BigInt] = Seq[BigInt](256 KiB, 128 KiB), + val ramBlockSizes : Seq[BigInt] = Seq[BigInt](64 KiB, 64 KiB), val initialContent : File = null, val coreFrequency : HertzNumber = 12 MHz, cpuPlugins : () => Seq[Plugin[VexRiscv]] = PQVexRiscv.withDSPMultiplier() diff --git a/vexriscv/src/main/scala/quantumrisc/PQVexRiscvUlx3s.scala b/vexriscv/src/main/scala/quantumrisc/PQVexRiscvUlx3s.scala new file mode 100644 index 0000000..593950c --- /dev/null +++ b/vexriscv/src/main/scala/quantumrisc/PQVexRiscvUlx3s.scala @@ -0,0 +1,98 @@ +package quantumrisc + +import java.io.{File, FileInputStream, FileOutputStream, IOException, OutputStream} + +import scopt.OptionParser + +import spinal.sim._ +import spinal.core._ +import spinal.lib._ +import spinal.core.sim._ + +import spinal.lib.bus.simple._ +import spinal.lib.bus.misc.SizeMapping +import spinal.lib.io.{TriStateArray, InOutWrapper} +import spinal.lib.com.jtag.Jtag +import spinal.lib.com.uart.Uart +import spinal.lib.com.jtag.sim.JtagTcp + +import vexriscv.VexRiscv +import vexriscv.plugin.Plugin + +case class PipelinedMemoryBusRamUlx3s(size : BigInt, initialContent : File = null) extends Component{ + require(size % 4 == 0, "Size must be multiple of 4 bytes") + require(size > 0, "Size must be greater than zero") + val busConfig = PipelinedMemoryBusConfig(log2Up(size), 32) + val io = new Bundle{ + val bus = slave(PipelinedMemoryBus(busConfig)) + } + + val ram = Mem(Bits(32 bits), size / 4) + io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.write) init(False) + io.bus.rsp.data := ram.readWriteSync( + address = io.bus.cmd.address >> 2, + data = io.bus.cmd.data, + enable = io.bus.cmd.valid, + write = io.bus.cmd.write, + mask = io.bus.cmd.mask + ) + io.bus.cmd.ready := True + + if (initialContent != null) { + val input = new FileInputStream(initialContent) + val initContent = Array.fill[BigInt](ram.wordCount)(0) + val fileContent = Array.ofDim[Byte](Seq(input.available, initContent.length * 4).min) + input.read(fileContent) + for ((byte, addr) <- fileContent.zipWithIndex) { + val l = java.lang.Byte.toUnsignedLong(byte) << ((addr & 3) * 8) + initContent(addr >> 2) |= BigInt(l) + } + ram.initBigInt(initContent) + } +} + + + + +class PQVexRiscvUlx3s( + val ramBlockSizes : Seq[BigInt] = Seq[BigInt](64 KiB, 64 KiB), + val initialContent : File = null, + val coreFrequency : HertzNumber = 25 MHz, + cpuPlugins : () => Seq[Plugin[VexRiscv]] = PQVexRiscv.withDSPMultiplier() +) extends PQVexRiscv( + cpuPlugins = cpuPlugins, + ibusRange = SizeMapping(0x80000000l, ramBlockSizes.reduce(_ + _)), + genTimer = true +) { + val io = new Bundle { + val asyncReset = in Bool + val mainClock = in Bool + val uart = master(Uart()) + val jtag = slave(Jtag()) + } + + asyncReset := io.asyncReset + mainClock := io.mainClock + + uart <> io.uart + jtag <> io.jtag + + val memory = new ClockingArea(systemClockDomain) { + val ramBlocks = ramBlockSizes.zipWithIndex.map(t => PipelinedMemoryBusRamUlx3s(t._1, if (t._2 == 0) initialContent else null)) + var curAddr : BigInt = 0x80000000l + for (block <- ramBlocks) { + busSlaves += block.io.bus -> SizeMapping(curAddr, block.size) + curAddr += block.size + } + } +} + + +object PQVexRiscvUlx3s { + def main(args: Array[String]) : Unit = { + SpinalConfig( + mode = Verilog + // targetDirectory = "rtl" + ).generate(new PQVexRiscvUlx3s).printPruned() + } +} diff --git a/vexriscv/tf2323h_openocd.cfg b/vexriscv/tf2323h_openocd.cfg new file mode 100644 index 0000000..2682caa --- /dev/null +++ b/vexriscv/tf2323h_openocd.cfg @@ -0,0 +1,19 @@ +# ---- FT232H Adapter ----- +interface ftdi +# source [find interface/ftdi/um232h.cfg] +# ftdi_serial "TN34GV0F" +ftdi_vid_pid 0x0403 0x6014 +ftdi_layout_init 0x0008 0x400b +adapter_khz 20000 +transport select jtag + + +# Adapt this to your favourite FTDI-based debugger +# source [find interface/ftdi/um232h.cfg] +# ftdi_serial "TN34GV0F" + +# The Murax target needs a YAML file, even if it is empty +set MURAX_CPU0_YAML cpu0.yaml + +# The Murax target should work for all PQVexRiscv based chips +source [find target/murax.cfg]