From e4e90fd17e9688ec50ee53c2e1b57279d7a7be1a Mon Sep 17 00:00:00 2001
From: Thorsten Knoll <thorsten_knoll@yahoo.de>
Date: Mon, 18 Jan 2021 08:11:18 +0100
Subject: [PATCH] update readme

---
 README.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/README.md b/README.md
index 74b92af..49c6bea 100644
--- a/README.md
+++ b/README.md
@@ -5,25 +5,25 @@ Use the Virtual Machine 1.5 from:
 [https://random-oracles.org/risc-v/](https://random-oracles.org/risc-v/)
 
 ### Starting the Vexriscv Simulation
-Open console, change to folder 'vexriscv' and run
+Open console, change to folder `vexriscv` and run
 ```
 sbt "runMain mupq.PQVexRiscvSim"
 ```
 
 ### Connecting openocd-vexriscv
-Open new console, change to folder 'vexriscv' and run
-'''
+Open new console, change to folder `vexriscv` and run
+```
 openocd-vexriscv -f vexriscvsim.cfg
-'''
+```
 
 ### Compile and run the C code
-Open new console (the third one), change to folder 'c_project' and compile the project:
-'''
+Open new console (the third one), change to folder `c_project` and compile the project:
+```
 make
-'''
+```
 Then load the created ELF file into the simulation via GDB:
-'''
+```
 riscv64-unknown-elf-gdb -tui -ex 'set remotetimeout 15' -ex 'target remote :3333' -ex 'load' -ex 'break main' -ex 'continue' main
-'''
+```
 Set some more breakpoints and step through the code with 'c' (continue). You will see the UART output in console 1 (vexriscv sim).