struct(C) and bundle(spinal) now equal and w/r enabled from both sides

c_project/bsp/vexriscv/main.c

@@ -1,29 +0,0 @@
-#include <stdbool.h>
-#include "hal.h"
-
-// typedef struct {
-//     volatile uint32_t state;
-// } My_Mem;
-
-// #define MY_MEM ((My_Mem*)(0xF0030000))
-
-int main(void)
-{
-    printf("HELLO WORLD\n");
-
-    uint32_t state = 10000;
-    // uint32_t state_return;
-
-    while (1)
-    {
-        printf("State in : %i\n", state);
-
-        // MY_MEM->state = state;
-        // state_return = MY_MEM->state;
-
-        state = state + 1;
-
-        printf("State out: %i\n", state);
-    }
-    return 0;
-}

c_project/bsp/vexriscv/pqvexriscvsim.ld

@@ -3,12 +3,12 @@ OUTPUT_ARCH(riscv)
 
 ENTRY( _start )
 
-__ram_size = 384K;
+__ram_size = 128K;
 
 MEMORY
 {
-  rom (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 256K
-  ram (wxa!ri) : ORIGIN = 0x80040000, LENGTH = 128K
+  rom (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
+  ram (wxa!ri) : ORIGIN = 0x80040000, LENGTH = 64K
 }
 
 INCLUDE nonvolatile.ld

c_project/main.c

@@ -2,60 +2,59 @@
 #include "hal.h"
 
 typedef struct {
-    volatile uint32_t state[4];
+    volatile uint32_t state[2];
+    volatile uint32_t key[2];
     volatile uint32_t status;
 } My_Mem;
 
 #define MY_MEM ((My_Mem*)(0xF0030000))
 
-void writeReadState(uint32_t * state)
-{
-    for(unsigned i = 0; i < 4; i++)
-    {
+void writeState(uint32_t * state) {
+    for(unsigned i = 0; i < 2; i++) {
         MY_MEM->state[i] = state[i];
     }
-    for(unsigned i = 0; i < 4; i++)
-    {
+}
+
+void readState(uint32_t * state) {
+    for(unsigned i = 0; i < 2; i++) {
         state[i] = MY_MEM->state[i];
     }
 }
 
-void printState(uint32_t * state)
-{
+void printState(uint32_t * state) {
     printf("State:\n");
-    for(unsigned i = 0; i<4; i++)
-    {
+    for(unsigned i = 0; i<2; i++) {
         printf("%i\n",state[i]);
     }
 }
 
-void printStatus(uint32_t status)
-{
-    printf("Status: %i\n", status);
+void writeKey(uint32_t * key) {
+    for (unsigned i = 0; i < 2; i++) {
+        MY_MEM->key[i] = key[i];
+    }
 }
 
-int main(void)
-{
+int main(void) {
     printf("HELLO WORLD\n");
 
-    uint32_t state[4] = {10000, 65, 4242, 85328};
-    uint32_t status = 12;
-    // MY_MEM->status = status;
+    uint32_t state[2] = {10000, 3000};
+    uint32_t key[2] = {64, 4};
 
-    while (1)
-    {
-        printState(state);
-        writeReadState(state);
+    while (1) {
         printState(state);
+        writeState(state);
 
-        // status = MY_MEM->status;
-        // printStatus(status);
+        writeKey(key);
 
-        for(unsigned i = 0; i < 4; i++)
-        {
+        MY_MEM->status = 1;
+        while (MY_MEM->status != 0);
+
+        readState(state);
+        printState(state);
+
+        for(unsigned i = 0; i < 2; i++) {
             state[i] = state[i]+1;
         }
-
     }
     return 0;
 }

vexriscv/src/main/scala/quantumrisc/MyMem.scala

@@ -16,42 +16,26 @@ class MyMem() extends Component {
         val bus = slave(Apb3(MyMem.getApb3Config))
     }
 
-    val myReg = Reg(Bits(128 bit))
-    val myStatus = Reg(Bits(32 bit))
-    // val myReg = Mem(Bits(32 bit), 4)
-    val busCtrl = Apb3SlaveFactory(io.bus)
-
-    // myStatus := U"32'h1A".asBits
-
-    // busCtrl.readAndWrite(myReg,address = 0x30000,bitOffset = 0)
-
-    busCtrl.readMultiWord(myReg,address = 0x30000)
-    busCtrl.writeMultiWord(myReg,address = 0x30000)
-
-    // busCtrl.readAndWrite(myStatus,address = 0x30128)
-    // busCtrl.readMultiWord(myStatus,address = 0x30128)
-    // busCtrl.writeMultiWord(myStatus,address = 0x30128)
-
-
+    // Define a bundle "mapMem" for the state and the status
+    case object mapMem extends Bundle {
+        val state = Reg(Bits(64 bit))
+        val key = Reg(Bits(64 bit))
+        val status = Reg(Bits(32 bit))
+        // val myKey = Reg(Bits(32 bit))
+    }
 
-    /**
-    val busReady = Reg(Bool) init(false)
-    val busAccess = io.bus.PENABLE && io.bus.PSEL(0)
-    io.bus.PRDATA := 0
-    busReady := busAccess && !busReady
-    io.bus.PREADY := busReady
+    // Create a BusslaveFactory on the io.bus
+    val busCtrl = Apb3SlaveFactory(io.bus)
 
+    // Register the bundle "myReg" to the BusSlaveFactory at address 0x30000
+    busCtrl.readMultiWord(mapMem,address = 0x30000)
+    busCtrl.writeMultiWord(mapMem,address = 0x30000)
 
-    when(busReady) {
-        when(io.bus.PWRITE) {
-            start := io.bus.PWDATA(0) // Set flags on write, will trigger the coprocessor
-            interruptEn := io.bus.PWDATA(2)
-        } otherwise {
-            io.bus.PRDATA(0) := busy // Assemble flags for read
-            io.bus.PRDATA(1) := interrupt
-            io.bus.PRDATA(2) := interruptEn
-            interrupt := False
-        }
+    // When state and key are loaded, the status becomes 1
+    // and the calculation can start (state = state XOR key).
+    // After the calcualtion is finished, the status is set to 0.
+    when (mapMem.status === 1){
+        mapMem.state := mapMem.state ^ mapMem.key
+        mapMem.status := 0
     }
-    **/
 }

vexriscv/src/main/scala/quantumrisc/PQVexRiscvSim.scala

@@ -92,7 +92,7 @@ object PQVexRiscvSim {
     case class PQVexRiscvSimConfig(
       uartOutFile: OutputStream = System.out,
       initFile: File = null,
-      ramBlocks: Seq[BigInt] = Seq(256 KiB, 128 KiB),
+      ramBlocks: Seq[BigInt] = Seq(64 KiB, 64 KiB),
       cpuPlugins: () => Seq[Plugin[VexRiscv]] = PQVexRiscv.withDSPMultiplier()
     )
     val optParser = new OptionParser[PQVexRiscvSimConfig]("PQVexRiscvSim") {

vexriscv/src/main/scala/quantumrisc/PQVexRiscvUlx3s.scala

@@ -55,7 +55,7 @@ case class PipelinedMemoryBusRamUlx3s(size : BigInt, initialContent : File = nul
 
 
 class PQVexRiscvUlx3s(
-  val ramBlockSizes : Seq[BigInt] = Seq[BigInt](64 KiB, 64 KiB),
+  val ramBlockSizes : Seq[BigInt] = Seq[BigInt](128 KiB, 128 KiB),
   val initialContent : File = null,
   val coreFrequency : HertzNumber = 25 MHz,
   cpuPlugins : () => Seq[Plugin[VexRiscv]] = PQVexRiscv.withDSPMultiplier()