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vexriscv_mem_mapped_example
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${ item.name }
Create branch ${ searchTerm }
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${ noResults }
vexriscv_mem_mapped_example/ulx3s/PQVexRiscvUlx3s.ys

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cleaned project for C in sim and ulx3s
4 years ago
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  1. read_verilog PQVexRiscvUlx3s.v
  2. synth_ecp5 -json PQVexRiscvUlx3s.json